OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [src/] [minsoc_bench.prj] - Blame information for rev 128

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 88 rfajardo
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
2
PROJECT_SRC=(minsoc_bench_defines.v
3 128 rfajardo
minsoc_bench_clock.v
4 88 rfajardo
minsoc_bench.v
5
minsoc_memory_model.v
6
dbg_comm_vpi.v
7
fpga_memory_primitives.v
8
timescale.v)
9
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.