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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Blame information for rev 42

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1 2 rfajardo
`include "minsoc_bench_defines.v"
2
`include "minsoc_defines.v"
3 10 rfajardo
`include "or1200_defines.v"
4 2 rfajardo
 
5
module minsoc_bench();
6
 
7
reg clock, reset;
8
 
9 17 rfajardo
//Debug interface
10 2 rfajardo
wire dbg_tms_i;
11
wire dbg_tck_i;
12
wire dbg_tdi_i;
13
wire dbg_tdo_o;
14
wire jtag_vref;
15
wire jtag_gnd;
16
 
17 17 rfajardo
//SPI wires
18 2 rfajardo
wire spi_mosi;
19
reg spi_miso;
20
wire spi_sclk;
21
wire [1:0] spi_ss;
22
 
23 17 rfajardo
//UART wires
24 2 rfajardo
wire uart_stx;
25 9 rfajardo
reg uart_srx;
26 2 rfajardo
 
27 17 rfajardo
//ETH wires
28
reg eth_col;
29
reg eth_crs;
30 2 rfajardo
wire eth_trst;
31 17 rfajardo
reg eth_tx_clk;
32 2 rfajardo
wire eth_tx_en;
33
wire eth_tx_er;
34
wire [3:0] eth_txd;
35 17 rfajardo
reg eth_rx_clk;
36
reg eth_rx_dv;
37
reg eth_rx_er;
38
reg [3:0] eth_rxd;
39
reg eth_fds_mdint;
40 2 rfajardo
wire eth_mdc;
41
wire eth_mdio;
42
 
43
//
44
//      TASKS registers to communicate with interfaces
45
//
46 17 rfajardo
`ifdef ETHERNET
47 28 rfajardo
reg [7:0] eth_rx_data [0:1535];            //receive buffer ETH (max packet 1536)
48 17 rfajardo
reg [7:0] eth_tx_data [0:1535];     //send buffer ETH (max packet 1536)
49
localparam ETH_HDR = 14;
50
localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
51
`endif
52 2 rfajardo
 
53
 
54
//
55
// Testbench mechanics
56
//
57 4 rfajardo
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
58 2 rfajardo
integer initialize, final, ptr;
59
reg [8*64:0] file_name;
60
reg load_file;
61 8 rfajardo
 
62 2 rfajardo
initial begin
63 8 rfajardo
    reset = 1'b0;
64
    clock = 1'b0;
65 28 rfajardo
 
66
`ifndef NO_CLOCK_DIVISION
67
    minsoc_top_0.clk_adjust.clk_int = 1'b0;
68
    minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;
69
`endif
70 17 rfajardo
 
71 11 rfajardo
    uart_srx = 1'b1;
72 17 rfajardo
 
73
        eth_col = 1'b0;
74
        eth_crs = 1'b0;
75
        eth_fds_mdint = 1'b1;
76
        eth_rx_er = 1'b0;
77
 
78
        eth_tx_clk = 1'b0;
79
        eth_rx_clk = 1'b0;
80
        eth_rxd = 4'h0;
81
        eth_rx_dv = 1'b0;
82
 
83 8 rfajardo
 
84 17 rfajardo
//dual and two port rams from FPGA memory instances have to be initialized to 0
85 10 rfajardo
    init_fpga_memory();
86
 
87 2 rfajardo
        load_file = 1'b0;
88
`ifdef INITIALIZE_MEMORY_MODEL
89
        load_file = 1'b1;
90
`endif
91
`ifdef START_UP
92
        load_file = 1'b1;
93
`endif
94 8 rfajardo
 
95 2 rfajardo
        //get firmware hex file from command line input
96
        if ( load_file ) begin
97
                if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
98
                        $display("ERROR: please specify an input file to start.");
99
                        $finish;
100
                end
101
                $readmemh(file_name, program_mem);
102
                // First word comprehends size of program
103
                final = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };
104
        end
105
 
106
`ifdef INITIALIZE_MEMORY_MODEL
107
        // Initialize memory with firmware
108
        initialize = 0;
109
        while ( initialize < final ) begin
110
                minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];
111
                minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];
112
                minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];
113
                minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];
114
        initialize = initialize + 4;
115
        end
116
        $display("Memory model initialized with firmware:");
117
        $display("%s", file_name);
118
        $display("%d Bytes loaded from %d ...", initialize , final);
119
`endif
120
 
121
    // Reset controller
122
    repeat (2) @ (negedge clock);
123
    reset = 1'b1;
124
    repeat (16) @ (negedge clock);
125
    reset = 1'b0;
126
 
127
`ifdef START_UP
128
        // Pass firmware over spi to or1k_startup
129
        ptr = 0;
130
        //read dummy
131
        send_spi(program_mem[ptr]);
132
        send_spi(program_mem[ptr]);
133
        send_spi(program_mem[ptr]);
134
        send_spi(program_mem[ptr]);
135
        //~read dummy
136
        while ( ptr < final ) begin
137
                send_spi(program_mem[ptr]);
138
                ptr = ptr + 1;
139
        end
140
        $display("Memory start-up completed...");
141
        $display("Loaded firmware:");
142
        $display("%s", file_name);
143
`endif
144 17 rfajardo
 
145
 
146 2 rfajardo
        //
147
    // Testbench START
148
        //
149 17 rfajardo
 
150
    fork
151
        begin
152
`ifdef ETHERNET
153
            get_mac();
154
 
155
            if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 )
156
                $display("eth-nocache firmware started.");
157
`endif
158
        end
159
        begin
160
                #2000000;
161
`ifdef UART
162
            uart_send(8'h41);       //Character A
163
`endif
164
`ifdef ETHERNET
165
                eth_tx_data[ETH_HDR+0] = 8'hBA;
166
                eth_tx_data[ETH_HDR+1] = 8'h87;
167
                eth_tx_data[ETH_HDR+2] = 8'hAA;
168
                eth_tx_data[ETH_HDR+3] = 8'hBB;
169
                eth_tx_data[ETH_HDR+4] = 8'hCC;
170
                eth_tx_data[ETH_HDR+5] = 8'hDD;
171 2 rfajardo
 
172 17 rfajardo
                send_mac(6);
173
`endif
174
        end
175
    join
176 2 rfajardo
 
177
end
178
 
179
 
180
//
181
// Modules instantiations
182
//
183
minsoc_top minsoc_top_0(
184
   .clk(clock),
185
   .reset(reset)
186
 
187
   //JTAG ports
188
`ifdef GENERIC_TAP
189
   , .jtag_tdi(dbg_tdi_i),
190
   .jtag_tms(dbg_tms_i),
191
   .jtag_tck(dbg_tck_i),
192
   .jtag_tdo(dbg_tdo_o),
193
   .jtag_vref(jtag_vref),
194
   .jtag_gnd(jtag_gnd)
195
`endif
196
 
197
   //SPI ports
198
`ifdef START_UP
199
   , .spi_flash_mosi(spi_mosi),
200
   .spi_flash_miso(spi_miso),
201
   .spi_flash_sclk(spi_sclk),
202
   .spi_flash_ss(spi_ss)
203
`endif
204
 
205
   //UART ports
206
`ifdef UART
207
   , .uart_stx(uart_stx),
208
   .uart_srx(uart_srx)
209
`endif // !UART
210
 
211
        // Ethernet ports
212
`ifdef ETHERNET
213
        , .eth_col(eth_col),
214
    .eth_crs(eth_crs),
215
    .eth_trste(eth_trst),
216
    .eth_tx_clk(eth_tx_clk),
217
        .eth_tx_en(eth_tx_en),
218
    .eth_tx_er(eth_tx_er),
219
    .eth_txd(eth_txd),
220
    .eth_rx_clk(eth_rx_clk),
221
        .eth_rx_dv(eth_rx_dv),
222
    .eth_rx_er(eth_rx_er),
223
    .eth_rxd(eth_rxd),
224
    .eth_fds_mdint(eth_fds_mdint),
225
        .eth_mdc(eth_mdc),
226
    .eth_mdio(eth_mdio)
227
`endif // !ETHERNET
228
);
229
 
230
`ifdef VPI_DEBUG
231
        dbg_comm_vpi dbg_if(
232
                .SYS_CLK(clock),
233
                .P_TMS(dbg_tms_i),
234
                .P_TCK(dbg_tck_i),
235
                .P_TRST(),
236
                .P_TDI(dbg_tdi_i),
237
                .P_TDO(dbg_tdo_o)
238
        );
239
`else
240
   assign dbg_tdi_i = 1;
241
   assign dbg_tck_i = 0;
242
   assign dbg_tms_i = 1;
243
`endif
244
 
245
 
246
//
247 8 rfajardo
//      Regular clocking and output
248 2 rfajardo
//
249
always begin
250
    #((`CLK_PERIOD)/2) clock <= ~clock;
251
end
252
 
253
`ifdef VCD_OUTPUT
254
initial begin
255
        $dumpfile("../results/minsoc_wave.vcd");
256
        $dumpvars();
257
end
258
`endif
259
 
260
 
261
//
262
//      Functionalities tasks: SPI Startup and UART Monitor
263
//
264
//SPI START_UP
265
`ifdef START_UP
266 28 rfajardo
task send_spi;
267
    input [7:0] data_in;
268
    integer i;
269 2 rfajardo
    begin
270 28 rfajardo
        i = 7;
271
        for ( i = 7 ; i >= 0; i = i - 1 ) begin
272 2 rfajardo
                spi_miso = data_in[i];
273 28 rfajardo
                        @ (posedge spi_sclk);
274
            end
275
    end
276 2 rfajardo
endtask
277
`endif
278
//~SPI START_UP
279
 
280 17 rfajardo
//UART
281 2 rfajardo
`ifdef UART
282 28 rfajardo
localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE);
283 2 rfajardo
 
284 17 rfajardo
task uart_send;
285
    input [7:0] data;
286
    integer i;
287
    begin
288
        uart_srx = 1'b0;
289
            #UART_TX_WAIT;
290
        for ( i = 0; i < 8 ; i = i + 1 ) begin
291
                    uart_srx = data[i];
292
                    #UART_TX_WAIT;
293
            end
294
        uart_srx = 1'b0;
295
            #UART_TX_WAIT;
296
            uart_srx = 1'b1;
297
    end
298
endtask
299
 
300
//UART Monitor (prints uart output on the terminal)
301 2 rfajardo
// Something to trigger the task
302
always @(posedge clock)
303
        uart_decoder;
304
 
305
task uart_decoder;
306
        integer i;
307
        reg [7:0] tx_byte;
308
        begin
309
 
310
        // Wait for start bit
311
        while (uart_stx == 1'b1)
312
                @(uart_stx);
313
 
314
        #(UART_TX_WAIT+(UART_TX_WAIT/2));
315
 
316
    for ( i = 0; i < 8 ; i = i + 1 ) begin
317
                tx_byte[i] = uart_stx;
318
                #UART_TX_WAIT;
319
        end
320
 
321
        //Check for stop bit
322
        if (uart_stx == 1'b0) begin
323
                  //$display("* WARNING: user stop bit not received when expected at time %d__", $time);
324
          // Wait for return to idle
325
                while (uart_stx == 1'b0)
326
                        @(uart_stx);
327
          //$display("* USER UART returned to idle at time %d",$time);
328
        end
329
        // display the char
330
        $write("%c", tx_byte);
331
        end
332
endtask
333 17 rfajardo
//~UART Monitor
334 2 rfajardo
`endif // !UART
335 17 rfajardo
//~UART
336 2 rfajardo
 
337
 
338
//
339
//      TASKS to communicate with interfaces
340
//
341 28 rfajardo
//MAC_DATA
342 2 rfajardo
//
343 28 rfajardo
`ifdef ETHERNET
344 17 rfajardo
reg [31:0] crc32_result;
345 28 rfajardo
 
346
task get_mac;
347
    integer conta;
348
    reg LSB;
349
    begin
350
        conta = 0;
351
        LSB = 1;
352 17 rfajardo
        @ ( posedge eth_tx_en);
353
 
354
        repeat (16) @ (negedge eth_tx_clk);  //8 bytes, preamble (7 bytes) + start of frame (1 byte)
355 28 rfajardo
 
356
        while ( eth_tx_en == 1'b1 ) begin
357
            @ (negedge eth_tx_clk) begin
358
                if ( LSB == 1'b1 )
359
                    eth_rx_data[conta][3:0] = eth_txd;
360
                else begin
361
                    eth_rx_data[conta][7:4] = eth_txd;
362
                    conta = conta + 1;
363
                end
364
                LSB = ~LSB;
365
            end
366
        end
367
    end
368
endtask
369
 
370 17 rfajardo
task send_mac;              //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
371 28 rfajardo
    input [31:0] length;    //ETH_PAYLOAD_MAX_LENGTH 1518
372
    integer conta;
373 17 rfajardo
    begin
374 28 rfajardo
        if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin
375
            //DEST MAC
376
            eth_tx_data[0] = 8'h55;
377
            eth_tx_data[1] = 8'h47;
378
            eth_tx_data[2] = 8'h34;
379
            eth_tx_data[3] = 8'h22;
380
            eth_tx_data[4] = 8'h88;
381
            eth_tx_data[5] = 8'h92;
382
 
383
            //SOURCE MAC
384
            eth_tx_data[6] = 8'h3D;
385
            eth_tx_data[7] = 8'h4F;
386
            eth_tx_data[8] = 8'h1A;
387
            eth_tx_data[9] = 8'hBE;
388
            eth_tx_data[10] = 8'h68;
389
            eth_tx_data[11] = 8'h72;
390
 
391
            //LEN
392
            eth_tx_data[12] = length[7:4];
393
            eth_tx_data[13] = length[3:0];
394
 
395
            //DATA input by task caller
396
 
397
            //PAD
398
            for ( conta = length+14; conta < 60; conta = conta + 1 ) begin
399
                eth_tx_data[conta] = 8'h00;
400
            end
401
 
402
            gencrc32(conta);
403
 
404
            eth_tx_data[conta] = crc32_result[31:24];
405
            eth_tx_data[conta+1] = crc32_result[23:16];
406
            eth_tx_data[conta+2] = crc32_result[15:8];
407
            eth_tx_data[conta+3] = crc32_result[7:0];
408
 
409 17 rfajardo
            send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 );
410
        end
411
        else
412 28 rfajardo
            $display("Warning: Ethernet packet is to big to be sent.");
413
    end
414 17 rfajardo
 
415 28 rfajardo
endtask
416
 
417 17 rfajardo
task send_rx_packet;
418
  input  [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
419
  input   [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7 
420
  input   [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
421
  input  [31:0] start_addr; // start address
422
  input  [31:0] len; // length of frame in Bytes (without preamble and SFD)
423
  input         plus_drible_nibble; // if length is longer for one nibble
424
  integer       rx_cnt;
425
  reg    [31:0] eth_tx_data_addr_in; // address for reading from RX memory       
426
  reg     [7:0] eth_tx_data_data_out; // data for reading from RX memory
427
begin
428
      @(posedge eth_rx_clk);
429
      #1 eth_rx_dv = 1;
430
 
431
      // set initial rx memory address
432
      eth_tx_data_addr_in = start_addr;
433
 
434
      // send preamble
435
      for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
436
      begin
437
        #1 eth_rxd = preamble_data[3:0];
438
        #1 preamble_data = preamble_data >> 4;
439
        @(posedge eth_rx_clk);
440
      end
441
 
442
      // send SFD
443
      for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
444
      begin
445
        #1 eth_rxd = sfd_data[3:0];
446
        #1 sfd_data = sfd_data >> 4;
447
        @(posedge eth_rx_clk);
448
      end
449
 
450
      // send packet's addresses, type/length, data and FCS
451
      for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
452
      begin
453
        #1;
454
        eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
455
        eth_rxd = eth_tx_data_data_out[3:0];
456
        @(posedge eth_rx_clk);
457
        #1;
458
        eth_rxd = eth_tx_data_data_out[7:4];
459
        eth_tx_data_addr_in = eth_tx_data_addr_in + 1;
460
        @(posedge eth_rx_clk);
461
        #1;
462
      end
463
      if (plus_drible_nibble)
464
      begin
465
        eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
466
        eth_rxd = eth_tx_data_data_out[3:0];
467
        @(posedge eth_rx_clk);
468
      end
469
 
470
      #1 eth_rx_dv = 0;
471
      @(posedge eth_rx_clk);
472
 
473
end
474
endtask // send_rx_packet
475 28 rfajardo
 
476
//CRC32
477
localparam [31:0] CRC32_POLY = 32'h04C11DB7;
478
 
479 17 rfajardo
task gencrc32;
480
    input [31:0] crc32_length;
481 28 rfajardo
 
482
    integer     byte, bit;
483
    reg         msb;
484
    reg [7:0]    current_byte;
485
    reg [31:0]   temp;
486
 
487
    begin
488
        crc32_result = 32'hffffffff;
489
        for (byte = 0; byte < crc32_length; byte = byte + 1) begin
490
            current_byte = eth_tx_data[byte];
491
            for (bit = 0; bit < 8; bit = bit + 1) begin
492
                msb = crc32_result[31];
493
                crc32_result = crc32_result << 1;
494
                if (msb != current_byte[bit]) begin
495
                    crc32_result = crc32_result ^ CRC32_POLY;
496
                    crc32_result[0] = 1;
497
                end
498
            end
499
        end
500
 
501
        // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
502
        //
503
        // Mirror:
504
        for (bit = 0; bit < 32; bit = bit + 1)
505
            temp[31-bit] = crc32_result[bit];
506
 
507
        // Swap and Complement:
508
        crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
509
    end
510
endtask
511 17 rfajardo
//~CRC32
512
 
513
//Generate tx and rx clocks
514
always begin
515
        #((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
516
end
517
always begin
518
        #((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
519
end
520
//~Generate tx and rx clocks
521 28 rfajardo
 
522
`endif // !ETHERNET
523 2 rfajardo
//~MAC_DATA
524
 
525
 
526 10 rfajardo
 
527
//
528
// TASK to initialize instantiated FPGA dual and two port memory to 0
529
//
530
task init_fpga_memory;
531
    integer i;
532
    begin
533
`ifdef OR1200_RFRAM_TWOPORT
534
`ifdef OR1200_XILINX_RAMB4
535
    for ( i = 0; i < (1<<8); i = i + 1 ) begin
536
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_0.mem[i] = 16'h0000;
537
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_1.mem[i] = 16'h0000;
538
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_0.mem[i] = 16'h0000;
539
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_1.mem[i] = 16'h0000;
540
    end
541
`elsif OR1200_XILINX_RAMB16
542
    for ( i = 0; i < (1<<9); i = i + 1 ) begin
543
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
544
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
545
    end
546
`elsif OR1200_ALTERA_LPM
547
`ifndef OR1200_ALTERA_LPM_XXX
548
    $display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
549
    $display("It uses GENERIC memory instead.");
550
    $display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
551
`endif
552
`ifdef OR1200_ALTERA_LPM_XXX
553
    $display("...Using ALTERA memory for TWOPORT RFRAM!");
554
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
555
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
556
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
557
    end
558
`else
559
    $display("...Using GENERIC memory!");
560
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
561
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
562
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
563
    end
564
`endif
565
`elsif OR1200_XILINX_RAM32X1D
566
    $display("Definition OR1200_XILINX_RAM32X1D in or1200_defines.v does not enable FPGA memory for TWO port RFRAM");
567
    $display("It uses GENERIC memory instead.");
568
    $display("FPGA memory can be used if you choose OR1200_RFRAM_DUALPORT");
569
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
570
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
571
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
572
    end
573
`else
574
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
575
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
576
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
577
    end
578
`endif
579
`elsif OR1200_RFRAM_DUALPORT
580
`ifdef OR1200_XILINX_RAMB4
581
    for ( i = 0; i < (1<<8); i = i + 1 ) begin
582
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[i] = 16'h0000;
583
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[i] = 16'h0000;
584
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_0.mem[i] = 16'h0000;
585
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_1.mem[i] = 16'h0000;
586
    end
587
`elsif OR1200_XILINX_RAMB16
588
    for ( i = 0; i < (1<<9); i = i + 1 ) begin
589
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
590
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
591
    end
592
`elsif OR1200_ALTERA_LPM
593
`ifndef OR1200_ALTERA_LPM_XXX
594
    $display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
595
    $display("It uses GENERIC memory instead.");
596
    $display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
597
`endif
598
`ifdef OR1200_ALTERA_LPM_XXX
599
    $display("...Using ALTERA memory for DUALPORT RFRAM!");
600
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
601
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
602
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
603
    end
604
`else
605
    $display("...Using GENERIC memory!");
606
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
607
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
608
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
609
    end
610
`endif
611
`elsif OR1200_XILINX_RAM32X1D
612
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
613
    for ( i = 0; i < (1<<4); i = i + 1 ) begin
614
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
615
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
616
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
617
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
618
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
619
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
620
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
621
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
622
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
623
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
624
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
625
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
626
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
627
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
628
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
629
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
630
 
631
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
632
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
633
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
634
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
635
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
636
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
637
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
638
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
639
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
640
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
641
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
642
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
643
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
644
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
645
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
646
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
647
 
648
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
649
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
650
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
651
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
652
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
653
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
654
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
655
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
656
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
657
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
658
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
659
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
660
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
661
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
662
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
663
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
664
 
665
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
666
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
667
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
668
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
669
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
670
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
671
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
672
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
673
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
674
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
675
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
676
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
677
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
678
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
679
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
680
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
681
 
682
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
683
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
684
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
685
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
686
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
687
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
688
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
689
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
690
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
691
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
692
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
693
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
694
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
695
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
696
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
697
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
698
 
699
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
700
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
701
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
702
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
703
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
704
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
705
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
706
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
707
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
708
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
709
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
710
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
711
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
712
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
713
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
714
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
715
 
716
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
717
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
718
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
719
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
720
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
721
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
722
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
723
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
724
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
725
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
726
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
727
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
728
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
729
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
730
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
731
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
732
 
733
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
734
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
735
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
736
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
737
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
738
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
739
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
740
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
741
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
742
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
743
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
744
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
745
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
746
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
747
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
748
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
749
    end
750
`else
751
    for ( i = 0; i < (1<<4); i = i + 1 ) begin
752
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
753
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
754
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
755
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
756
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
757
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
758
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
759
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
760
 
761
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
762
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
763
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
764
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
765
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
766
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
767
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
768
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
769
 
770
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
771
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
772
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
773
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
774
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
775
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
776
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
777
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
778
 
779
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
780
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
781
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
782
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
783
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
784
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
785
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
786
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
787
 
788
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
789
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
790
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
791
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
792
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
793
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
794
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
795
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
796
 
797
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
798
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
799
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
800
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
801
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
802
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
803
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
804
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
805
 
806
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
807
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
808
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
809
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
810
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
811
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
812
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
813
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
814
 
815
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
816
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
817
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
818
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
819
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
820
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
821
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
822
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
823
    end
824
`endif
825
`else
826
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
827
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
828
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
829
    end
830
`endif
831
`endif
832
    end
833
endtask
834
 
835
 
836
 
837 2 rfajardo
endmodule
838
 

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