1 |
2 |
rfajardo |
`include "minsoc_bench_defines.v"
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2 |
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`include "minsoc_defines.v"
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3 |
10 |
rfajardo |
`include "or1200_defines.v"
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4 |
2 |
rfajardo |
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5 |
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module minsoc_bench();
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6 |
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7 |
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reg clock, reset;
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8 |
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9 |
17 |
rfajardo |
//Debug interface
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10 |
2 |
rfajardo |
wire dbg_tms_i;
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11 |
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wire dbg_tck_i;
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12 |
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wire dbg_tdi_i;
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13 |
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wire dbg_tdo_o;
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14 |
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wire jtag_vref;
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15 |
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wire jtag_gnd;
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16 |
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17 |
17 |
rfajardo |
//SPI wires
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18 |
2 |
rfajardo |
wire spi_mosi;
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19 |
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reg spi_miso;
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20 |
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wire spi_sclk;
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21 |
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wire [1:0] spi_ss;
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22 |
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23 |
17 |
rfajardo |
//UART wires
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24 |
2 |
rfajardo |
wire uart_stx;
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25 |
9 |
rfajardo |
reg uart_srx;
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26 |
2 |
rfajardo |
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27 |
17 |
rfajardo |
//ETH wires
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28 |
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reg eth_col;
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29 |
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reg eth_crs;
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30 |
2 |
rfajardo |
wire eth_trst;
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31 |
17 |
rfajardo |
reg eth_tx_clk;
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32 |
2 |
rfajardo |
wire eth_tx_en;
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33 |
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wire eth_tx_er;
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34 |
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wire [3:0] eth_txd;
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35 |
17 |
rfajardo |
reg eth_rx_clk;
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36 |
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reg eth_rx_dv;
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37 |
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reg eth_rx_er;
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38 |
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reg [3:0] eth_rxd;
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39 |
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reg eth_fds_mdint;
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40 |
2 |
rfajardo |
wire eth_mdc;
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41 |
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wire eth_mdio;
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42 |
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43 |
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//
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44 |
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// TASKS registers to communicate with interfaces
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45 |
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//
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46 |
17 |
rfajardo |
`ifdef ETHERNET
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47 |
28 |
rfajardo |
reg [7:0] eth_rx_data [0:1535]; //receive buffer ETH (max packet 1536)
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48 |
17 |
rfajardo |
reg [7:0] eth_tx_data [0:1535]; //send buffer ETH (max packet 1536)
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49 |
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localparam ETH_HDR = 14;
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50 |
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localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
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`endif
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52 |
2 |
rfajardo |
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53 |
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54 |
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//
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55 |
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// Testbench mechanics
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56 |
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//
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57 |
4 |
rfajardo |
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
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58 |
2 |
rfajardo |
integer initialize, final, ptr;
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59 |
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reg [8*64:0] file_name;
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60 |
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reg load_file;
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61 |
8 |
rfajardo |
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62 |
2 |
rfajardo |
initial begin
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63 |
8 |
rfajardo |
reset = 1'b0;
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64 |
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clock = 1'b0;
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65 |
28 |
rfajardo |
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66 |
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`ifndef NO_CLOCK_DIVISION
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67 |
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minsoc_top_0.clk_adjust.clk_int = 1'b0;
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68 |
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minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;
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69 |
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`endif
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70 |
17 |
rfajardo |
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71 |
11 |
rfajardo |
uart_srx = 1'b1;
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72 |
17 |
rfajardo |
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73 |
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eth_col = 1'b0;
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74 |
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eth_crs = 1'b0;
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75 |
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eth_fds_mdint = 1'b1;
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76 |
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eth_rx_er = 1'b0;
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77 |
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78 |
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eth_tx_clk = 1'b0;
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eth_rx_clk = 1'b0;
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80 |
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eth_rxd = 4'h0;
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81 |
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eth_rx_dv = 1'b0;
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8 |
rfajardo |
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84 |
17 |
rfajardo |
//dual and two port rams from FPGA memory instances have to be initialized to 0
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85 |
10 |
rfajardo |
init_fpga_memory();
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86 |
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87 |
2 |
rfajardo |
load_file = 1'b0;
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88 |
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`ifdef INITIALIZE_MEMORY_MODEL
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load_file = 1'b1;
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`endif
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91 |
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`ifdef START_UP
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load_file = 1'b1;
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93 |
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`endif
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94 |
8 |
rfajardo |
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95 |
2 |
rfajardo |
//get firmware hex file from command line input
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96 |
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if ( load_file ) begin
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97 |
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if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
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$display("ERROR: please specify an input file to start.");
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$finish;
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100 |
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end
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101 |
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$readmemh(file_name, program_mem);
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102 |
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// First word comprehends size of program
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103 |
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final = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };
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end
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106 |
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`ifdef INITIALIZE_MEMORY_MODEL
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// Initialize memory with firmware
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initialize = 0;
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109 |
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while ( initialize < final ) begin
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110 |
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minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];
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minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];
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112 |
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minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];
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113 |
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minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];
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initialize = initialize + 4;
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115 |
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end
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116 |
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$display("Memory model initialized with firmware:");
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$display("%s", file_name);
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118 |
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$display("%d Bytes loaded from %d ...", initialize , final);
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119 |
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`endif
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120 |
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121 |
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// Reset controller
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122 |
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repeat (2) @ (negedge clock);
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123 |
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reset = 1'b1;
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124 |
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repeat (16) @ (negedge clock);
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125 |
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reset = 1'b0;
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126 |
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127 |
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`ifdef START_UP
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128 |
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// Pass firmware over spi to or1k_startup
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129 |
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ptr = 0;
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130 |
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//read dummy
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131 |
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send_spi(program_mem[ptr]);
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132 |
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send_spi(program_mem[ptr]);
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133 |
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send_spi(program_mem[ptr]);
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134 |
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send_spi(program_mem[ptr]);
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135 |
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//~read dummy
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136 |
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while ( ptr < final ) begin
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137 |
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send_spi(program_mem[ptr]);
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138 |
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ptr = ptr + 1;
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139 |
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end
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140 |
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$display("Memory start-up completed...");
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141 |
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$display("Loaded firmware:");
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142 |
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$display("%s", file_name);
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143 |
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`endif
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144 |
17 |
rfajardo |
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145 |
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146 |
2 |
rfajardo |
//
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147 |
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// Testbench START
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148 |
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//
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149 |
17 |
rfajardo |
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150 |
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fork
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151 |
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begin
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152 |
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`ifdef ETHERNET
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153 |
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get_mac();
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154 |
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155 |
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if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 )
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156 |
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$display("eth-nocache firmware started.");
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157 |
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`endif
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158 |
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end
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159 |
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begin
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160 |
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#2000000;
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161 |
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`ifdef UART
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162 |
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uart_send(8'h41); //Character A
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163 |
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`endif
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164 |
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`ifdef ETHERNET
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165 |
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eth_tx_data[ETH_HDR+0] = 8'hBA;
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166 |
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eth_tx_data[ETH_HDR+1] = 8'h87;
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167 |
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eth_tx_data[ETH_HDR+2] = 8'hAA;
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168 |
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eth_tx_data[ETH_HDR+3] = 8'hBB;
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169 |
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eth_tx_data[ETH_HDR+4] = 8'hCC;
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170 |
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eth_tx_data[ETH_HDR+5] = 8'hDD;
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171 |
2 |
rfajardo |
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172 |
17 |
rfajardo |
send_mac(6);
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173 |
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`endif
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174 |
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end
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175 |
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join
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176 |
2 |
rfajardo |
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177 |
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end
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178 |
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180 |
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//
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181 |
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// Modules instantiations
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//
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183 |
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minsoc_top minsoc_top_0(
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.clk(clock),
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.reset(reset)
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186 |
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187 |
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//JTAG ports
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188 |
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`ifdef GENERIC_TAP
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189 |
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, .jtag_tdi(dbg_tdi_i),
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190 |
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.jtag_tms(dbg_tms_i),
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.jtag_tck(dbg_tck_i),
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.jtag_tdo(dbg_tdo_o),
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.jtag_vref(jtag_vref),
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.jtag_gnd(jtag_gnd)
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195 |
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`endif
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196 |
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197 |
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//SPI ports
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198 |
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`ifdef START_UP
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199 |
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, .spi_flash_mosi(spi_mosi),
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200 |
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.spi_flash_miso(spi_miso),
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201 |
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.spi_flash_sclk(spi_sclk),
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202 |
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.spi_flash_ss(spi_ss)
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203 |
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`endif
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204 |
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205 |
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//UART ports
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206 |
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`ifdef UART
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207 |
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, .uart_stx(uart_stx),
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208 |
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.uart_srx(uart_srx)
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209 |
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`endif // !UART
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210 |
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211 |
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// Ethernet ports
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212 |
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`ifdef ETHERNET
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213 |
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, .eth_col(eth_col),
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214 |
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.eth_crs(eth_crs),
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215 |
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.eth_trste(eth_trst),
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216 |
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.eth_tx_clk(eth_tx_clk),
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217 |
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.eth_tx_en(eth_tx_en),
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218 |
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.eth_tx_er(eth_tx_er),
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219 |
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.eth_txd(eth_txd),
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220 |
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.eth_rx_clk(eth_rx_clk),
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221 |
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.eth_rx_dv(eth_rx_dv),
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222 |
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.eth_rx_er(eth_rx_er),
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223 |
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.eth_rxd(eth_rxd),
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224 |
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.eth_fds_mdint(eth_fds_mdint),
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225 |
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.eth_mdc(eth_mdc),
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226 |
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.eth_mdio(eth_mdio)
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227 |
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`endif // !ETHERNET
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228 |
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);
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229 |
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230 |
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`ifdef VPI_DEBUG
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231 |
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dbg_comm_vpi dbg_if(
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232 |
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.SYS_CLK(clock),
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233 |
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.P_TMS(dbg_tms_i),
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234 |
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.P_TCK(dbg_tck_i),
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235 |
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.P_TRST(),
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236 |
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.P_TDI(dbg_tdi_i),
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237 |
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.P_TDO(dbg_tdo_o)
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238 |
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);
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239 |
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`else
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240 |
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assign dbg_tdi_i = 1;
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241 |
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assign dbg_tck_i = 0;
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242 |
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assign dbg_tms_i = 1;
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243 |
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`endif
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244 |
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245 |
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246 |
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//
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247 |
8 |
rfajardo |
// Regular clocking and output
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248 |
2 |
rfajardo |
//
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249 |
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always begin
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250 |
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#((`CLK_PERIOD)/2) clock <= ~clock;
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251 |
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end
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252 |
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253 |
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`ifdef VCD_OUTPUT
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254 |
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initial begin
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255 |
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$dumpfile("../results/minsoc_wave.vcd");
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256 |
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$dumpvars();
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257 |
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end
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258 |
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`endif
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259 |
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260 |
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261 |
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//
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262 |
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// Functionalities tasks: SPI Startup and UART Monitor
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263 |
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//
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264 |
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//SPI START_UP
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265 |
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`ifdef START_UP
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266 |
28 |
rfajardo |
task send_spi;
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267 |
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input [7:0] data_in;
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268 |
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integer i;
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269 |
2 |
rfajardo |
begin
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270 |
28 |
rfajardo |
i = 7;
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271 |
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for ( i = 7 ; i >= 0; i = i - 1 ) begin
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272 |
2 |
rfajardo |
spi_miso = data_in[i];
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273 |
28 |
rfajardo |
@ (posedge spi_sclk);
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274 |
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end
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275 |
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end
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276 |
2 |
rfajardo |
endtask
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277 |
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`endif
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278 |
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//~SPI START_UP
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279 |
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280 |
17 |
rfajardo |
//UART
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281 |
2 |
rfajardo |
`ifdef UART
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282 |
28 |
rfajardo |
localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE);
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283 |
2 |
rfajardo |
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284 |
17 |
rfajardo |
task uart_send;
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285 |
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input [7:0] data;
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286 |
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integer i;
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287 |
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begin
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288 |
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uart_srx = 1'b0;
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289 |
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#UART_TX_WAIT;
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290 |
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for ( i = 0; i < 8 ; i = i + 1 ) begin
|
291 |
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uart_srx = data[i];
|
292 |
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#UART_TX_WAIT;
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293 |
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end
|
294 |
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uart_srx = 1'b0;
|
295 |
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#UART_TX_WAIT;
|
296 |
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uart_srx = 1'b1;
|
297 |
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end
|
298 |
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endtask
|
299 |
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|
300 |
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//UART Monitor (prints uart output on the terminal)
|
301 |
2 |
rfajardo |
// Something to trigger the task
|
302 |
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always @(posedge clock)
|
303 |
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uart_decoder;
|
304 |
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305 |
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task uart_decoder;
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306 |
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integer i;
|
307 |
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reg [7:0] tx_byte;
|
308 |
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begin
|
309 |
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310 |
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// Wait for start bit
|
311 |
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while (uart_stx == 1'b1)
|
312 |
|
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@(uart_stx);
|
313 |
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|
314 |
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#(UART_TX_WAIT+(UART_TX_WAIT/2));
|
315 |
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|
316 |
|
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for ( i = 0; i < 8 ; i = i + 1 ) begin
|
317 |
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tx_byte[i] = uart_stx;
|
318 |
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#UART_TX_WAIT;
|
319 |
|
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end
|
320 |
|
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|
321 |
|
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//Check for stop bit
|
322 |
|
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if (uart_stx == 1'b0) begin
|
323 |
|
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//$display("* WARNING: user stop bit not received when expected at time %d__", $time);
|
324 |
|
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// Wait for return to idle
|
325 |
|
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while (uart_stx == 1'b0)
|
326 |
|
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@(uart_stx);
|
327 |
|
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//$display("* USER UART returned to idle at time %d",$time);
|
328 |
|
|
end
|
329 |
|
|
// display the char
|
330 |
|
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$write("%c", tx_byte);
|
331 |
|
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end
|
332 |
|
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endtask
|
333 |
17 |
rfajardo |
//~UART Monitor
|
334 |
2 |
rfajardo |
`endif // !UART
|
335 |
17 |
rfajardo |
//~UART
|
336 |
2 |
rfajardo |
|
337 |
|
|
|
338 |
|
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//
|
339 |
|
|
// TASKS to communicate with interfaces
|
340 |
|
|
//
|
341 |
28 |
rfajardo |
//MAC_DATA
|
342 |
2 |
rfajardo |
//
|
343 |
28 |
rfajardo |
`ifdef ETHERNET
|
344 |
17 |
rfajardo |
reg [31:0] crc32_result;
|
345 |
28 |
rfajardo |
|
346 |
|
|
task get_mac;
|
347 |
|
|
integer conta;
|
348 |
|
|
reg LSB;
|
349 |
|
|
begin
|
350 |
|
|
conta = 0;
|
351 |
|
|
LSB = 1;
|
352 |
17 |
rfajardo |
@ ( posedge eth_tx_en);
|
353 |
|
|
|
354 |
|
|
repeat (16) @ (negedge eth_tx_clk); //8 bytes, preamble (7 bytes) + start of frame (1 byte)
|
355 |
28 |
rfajardo |
|
356 |
|
|
while ( eth_tx_en == 1'b1 ) begin
|
357 |
|
|
@ (negedge eth_tx_clk) begin
|
358 |
|
|
if ( LSB == 1'b1 )
|
359 |
|
|
eth_rx_data[conta][3:0] = eth_txd;
|
360 |
|
|
else begin
|
361 |
|
|
eth_rx_data[conta][7:4] = eth_txd;
|
362 |
|
|
conta = conta + 1;
|
363 |
|
|
end
|
364 |
|
|
LSB = ~LSB;
|
365 |
|
|
end
|
366 |
|
|
end
|
367 |
|
|
end
|
368 |
|
|
endtask
|
369 |
|
|
|
370 |
17 |
rfajardo |
task send_mac; //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
|
371 |
28 |
rfajardo |
input [31:0] length; //ETH_PAYLOAD_MAX_LENGTH 1518
|
372 |
|
|
integer conta;
|
373 |
17 |
rfajardo |
begin
|
374 |
28 |
rfajardo |
if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin
|
375 |
|
|
//DEST MAC
|
376 |
|
|
eth_tx_data[0] = 8'h55;
|
377 |
|
|
eth_tx_data[1] = 8'h47;
|
378 |
|
|
eth_tx_data[2] = 8'h34;
|
379 |
|
|
eth_tx_data[3] = 8'h22;
|
380 |
|
|
eth_tx_data[4] = 8'h88;
|
381 |
|
|
eth_tx_data[5] = 8'h92;
|
382 |
|
|
|
383 |
|
|
//SOURCE MAC
|
384 |
|
|
eth_tx_data[6] = 8'h3D;
|
385 |
|
|
eth_tx_data[7] = 8'h4F;
|
386 |
|
|
eth_tx_data[8] = 8'h1A;
|
387 |
|
|
eth_tx_data[9] = 8'hBE;
|
388 |
|
|
eth_tx_data[10] = 8'h68;
|
389 |
|
|
eth_tx_data[11] = 8'h72;
|
390 |
|
|
|
391 |
|
|
//LEN
|
392 |
|
|
eth_tx_data[12] = length[7:4];
|
393 |
|
|
eth_tx_data[13] = length[3:0];
|
394 |
|
|
|
395 |
|
|
//DATA input by task caller
|
396 |
|
|
|
397 |
|
|
//PAD
|
398 |
|
|
for ( conta = length+14; conta < 60; conta = conta + 1 ) begin
|
399 |
|
|
eth_tx_data[conta] = 8'h00;
|
400 |
|
|
end
|
401 |
|
|
|
402 |
|
|
gencrc32(conta);
|
403 |
|
|
|
404 |
|
|
eth_tx_data[conta] = crc32_result[31:24];
|
405 |
|
|
eth_tx_data[conta+1] = crc32_result[23:16];
|
406 |
|
|
eth_tx_data[conta+2] = crc32_result[15:8];
|
407 |
|
|
eth_tx_data[conta+3] = crc32_result[7:0];
|
408 |
|
|
|
409 |
17 |
rfajardo |
send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 );
|
410 |
|
|
end
|
411 |
|
|
else
|
412 |
28 |
rfajardo |
$display("Warning: Ethernet packet is to big to be sent.");
|
413 |
|
|
end
|
414 |
17 |
rfajardo |
|
415 |
28 |
rfajardo |
endtask
|
416 |
|
|
|
417 |
17 |
rfajardo |
task send_rx_packet;
|
418 |
|
|
input [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
|
419 |
|
|
input [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7
|
420 |
|
|
input [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
|
421 |
|
|
input [31:0] start_addr; // start address
|
422 |
|
|
input [31:0] len; // length of frame in Bytes (without preamble and SFD)
|
423 |
|
|
input plus_drible_nibble; // if length is longer for one nibble
|
424 |
|
|
integer rx_cnt;
|
425 |
|
|
reg [31:0] eth_tx_data_addr_in; // address for reading from RX memory
|
426 |
|
|
reg [7:0] eth_tx_data_data_out; // data for reading from RX memory
|
427 |
|
|
begin
|
428 |
|
|
@(posedge eth_rx_clk);
|
429 |
|
|
#1 eth_rx_dv = 1;
|
430 |
|
|
|
431 |
|
|
// set initial rx memory address
|
432 |
|
|
eth_tx_data_addr_in = start_addr;
|
433 |
|
|
|
434 |
|
|
// send preamble
|
435 |
|
|
for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
|
436 |
|
|
begin
|
437 |
|
|
#1 eth_rxd = preamble_data[3:0];
|
438 |
|
|
#1 preamble_data = preamble_data >> 4;
|
439 |
|
|
@(posedge eth_rx_clk);
|
440 |
|
|
end
|
441 |
|
|
|
442 |
|
|
// send SFD
|
443 |
|
|
for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
|
444 |
|
|
begin
|
445 |
|
|
#1 eth_rxd = sfd_data[3:0];
|
446 |
|
|
#1 sfd_data = sfd_data >> 4;
|
447 |
|
|
@(posedge eth_rx_clk);
|
448 |
|
|
end
|
449 |
|
|
|
450 |
|
|
// send packet's addresses, type/length, data and FCS
|
451 |
|
|
for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
|
452 |
|
|
begin
|
453 |
|
|
#1;
|
454 |
|
|
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
|
455 |
|
|
eth_rxd = eth_tx_data_data_out[3:0];
|
456 |
|
|
@(posedge eth_rx_clk);
|
457 |
|
|
#1;
|
458 |
|
|
eth_rxd = eth_tx_data_data_out[7:4];
|
459 |
|
|
eth_tx_data_addr_in = eth_tx_data_addr_in + 1;
|
460 |
|
|
@(posedge eth_rx_clk);
|
461 |
|
|
#1;
|
462 |
|
|
end
|
463 |
|
|
if (plus_drible_nibble)
|
464 |
|
|
begin
|
465 |
|
|
eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
|
466 |
|
|
eth_rxd = eth_tx_data_data_out[3:0];
|
467 |
|
|
@(posedge eth_rx_clk);
|
468 |
|
|
end
|
469 |
|
|
|
470 |
|
|
#1 eth_rx_dv = 0;
|
471 |
|
|
@(posedge eth_rx_clk);
|
472 |
|
|
|
473 |
|
|
end
|
474 |
|
|
endtask // send_rx_packet
|
475 |
28 |
rfajardo |
|
476 |
|
|
//CRC32
|
477 |
|
|
localparam [31:0] CRC32_POLY = 32'h04C11DB7;
|
478 |
|
|
|
479 |
17 |
rfajardo |
task gencrc32;
|
480 |
|
|
input [31:0] crc32_length;
|
481 |
28 |
rfajardo |
|
482 |
|
|
integer byte, bit;
|
483 |
|
|
reg msb;
|
484 |
|
|
reg [7:0] current_byte;
|
485 |
|
|
reg [31:0] temp;
|
486 |
|
|
|
487 |
|
|
begin
|
488 |
|
|
crc32_result = 32'hffffffff;
|
489 |
|
|
for (byte = 0; byte < crc32_length; byte = byte + 1) begin
|
490 |
|
|
current_byte = eth_tx_data[byte];
|
491 |
|
|
for (bit = 0; bit < 8; bit = bit + 1) begin
|
492 |
|
|
msb = crc32_result[31];
|
493 |
|
|
crc32_result = crc32_result << 1;
|
494 |
|
|
if (msb != current_byte[bit]) begin
|
495 |
|
|
crc32_result = crc32_result ^ CRC32_POLY;
|
496 |
|
|
crc32_result[0] = 1;
|
497 |
|
|
end
|
498 |
|
|
end
|
499 |
|
|
end
|
500 |
|
|
|
501 |
|
|
// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
|
502 |
|
|
//
|
503 |
|
|
// Mirror:
|
504 |
|
|
for (bit = 0; bit < 32; bit = bit + 1)
|
505 |
|
|
temp[31-bit] = crc32_result[bit];
|
506 |
|
|
|
507 |
|
|
// Swap and Complement:
|
508 |
|
|
crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
|
509 |
|
|
end
|
510 |
|
|
endtask
|
511 |
17 |
rfajardo |
//~CRC32
|
512 |
|
|
|
513 |
|
|
//Generate tx and rx clocks
|
514 |
|
|
always begin
|
515 |
|
|
#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
|
516 |
|
|
end
|
517 |
|
|
always begin
|
518 |
|
|
#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
|
519 |
|
|
end
|
520 |
|
|
//~Generate tx and rx clocks
|
521 |
28 |
rfajardo |
|
522 |
|
|
`endif // !ETHERNET
|
523 |
2 |
rfajardo |
//~MAC_DATA
|
524 |
|
|
|
525 |
|
|
|
526 |
10 |
rfajardo |
|
527 |
|
|
//
|
528 |
|
|
// TASK to initialize instantiated FPGA dual and two port memory to 0
|
529 |
|
|
//
|
530 |
|
|
task init_fpga_memory;
|
531 |
|
|
integer i;
|
532 |
|
|
begin
|
533 |
|
|
`ifdef OR1200_RFRAM_TWOPORT
|
534 |
|
|
`ifdef OR1200_XILINX_RAMB4
|
535 |
|
|
for ( i = 0; i < (1<<8); i = i + 1 ) begin
|
536 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_0.mem[i] = 16'h0000;
|
537 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_1.mem[i] = 16'h0000;
|
538 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_0.mem[i] = 16'h0000;
|
539 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_1.mem[i] = 16'h0000;
|
540 |
|
|
end
|
541 |
|
|
`elsif OR1200_XILINX_RAMB16
|
542 |
|
|
for ( i = 0; i < (1<<9); i = i + 1 ) begin
|
543 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
|
544 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
|
545 |
|
|
end
|
546 |
|
|
`elsif OR1200_ALTERA_LPM
|
547 |
|
|
`ifndef OR1200_ALTERA_LPM_XXX
|
548 |
|
|
$display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
|
549 |
|
|
$display("It uses GENERIC memory instead.");
|
550 |
|
|
$display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
|
551 |
|
|
`endif
|
552 |
|
|
`ifdef OR1200_ALTERA_LPM_XXX
|
553 |
|
|
$display("...Using ALTERA memory for TWOPORT RFRAM!");
|
554 |
|
|
for ( i = 0; i < (1<<5); i = i + 1 ) begin
|
555 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
|
556 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
|
557 |
|
|
end
|
558 |
|
|
`else
|
559 |
|
|
$display("...Using GENERIC memory!");
|
560 |
|
|
for ( i = 0; i < (1<<5); i = i + 1 ) begin
|
561 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
|
562 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
|
563 |
|
|
end
|
564 |
|
|
`endif
|
565 |
|
|
`elsif OR1200_XILINX_RAM32X1D
|
566 |
|
|
$display("Definition OR1200_XILINX_RAM32X1D in or1200_defines.v does not enable FPGA memory for TWO port RFRAM");
|
567 |
|
|
$display("It uses GENERIC memory instead.");
|
568 |
|
|
$display("FPGA memory can be used if you choose OR1200_RFRAM_DUALPORT");
|
569 |
|
|
for ( i = 0; i < (1<<5); i = i + 1 ) begin
|
570 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
|
571 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
|
572 |
|
|
end
|
573 |
|
|
`else
|
574 |
|
|
for ( i = 0; i < (1<<5); i = i + 1 ) begin
|
575 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
|
576 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
|
577 |
|
|
end
|
578 |
|
|
`endif
|
579 |
|
|
`elsif OR1200_RFRAM_DUALPORT
|
580 |
|
|
`ifdef OR1200_XILINX_RAMB4
|
581 |
|
|
for ( i = 0; i < (1<<8); i = i + 1 ) begin
|
582 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[i] = 16'h0000;
|
583 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[i] = 16'h0000;
|
584 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_0.mem[i] = 16'h0000;
|
585 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_1.mem[i] = 16'h0000;
|
586 |
|
|
end
|
587 |
|
|
`elsif OR1200_XILINX_RAMB16
|
588 |
|
|
for ( i = 0; i < (1<<9); i = i + 1 ) begin
|
589 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
|
590 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
|
591 |
|
|
end
|
592 |
|
|
`elsif OR1200_ALTERA_LPM
|
593 |
|
|
`ifndef OR1200_ALTERA_LPM_XXX
|
594 |
|
|
$display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
|
595 |
|
|
$display("It uses GENERIC memory instead.");
|
596 |
|
|
$display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
|
597 |
|
|
`endif
|
598 |
|
|
`ifdef OR1200_ALTERA_LPM_XXX
|
599 |
|
|
$display("...Using ALTERA memory for DUALPORT RFRAM!");
|
600 |
|
|
for ( i = 0; i < (1<<5); i = i + 1 ) begin
|
601 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
|
602 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
|
603 |
|
|
end
|
604 |
|
|
`else
|
605 |
|
|
$display("...Using GENERIC memory!");
|
606 |
|
|
for ( i = 0; i < (1<<5); i = i + 1 ) begin
|
607 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
|
608 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
|
609 |
|
|
end
|
610 |
|
|
`endif
|
611 |
|
|
`elsif OR1200_XILINX_RAM32X1D
|
612 |
|
|
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
|
613 |
|
|
for ( i = 0; i < (1<<4); i = i + 1 ) begin
|
614 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
|
615 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
|
616 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
|
617 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
|
618 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
|
619 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
|
620 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
|
621 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
|
622 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
|
623 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
|
624 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
|
625 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
|
626 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
|
627 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
|
628 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
|
629 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
|
630 |
|
|
|
631 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
|
632 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
|
633 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
|
634 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
|
635 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
|
636 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
|
637 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
|
638 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
|
639 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
|
640 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
|
641 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
|
642 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
|
643 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
|
644 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
|
645 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
|
646 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
|
647 |
|
|
|
648 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
|
649 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
|
650 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
|
651 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
|
652 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
|
653 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
|
654 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
|
655 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
|
656 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
|
657 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
|
658 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
|
659 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
|
660 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
|
661 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
|
662 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
|
663 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
|
664 |
|
|
|
665 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
|
666 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
|
667 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
|
668 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
|
669 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
|
670 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
|
671 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
|
672 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
|
673 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
|
674 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
|
675 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
|
676 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
|
677 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
|
678 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
|
679 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
|
680 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
|
681 |
|
|
|
682 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
|
683 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
|
684 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
|
685 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
|
686 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
|
687 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
|
688 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
|
689 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
|
690 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
|
691 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
|
692 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
|
693 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
|
694 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
|
695 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
|
696 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
|
697 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
|
698 |
|
|
|
699 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
|
700 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
|
701 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
|
702 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
|
703 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
|
704 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
|
705 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
|
706 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
|
707 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
|
708 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
|
709 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
|
710 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
|
711 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
|
712 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
|
713 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
|
714 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
|
715 |
|
|
|
716 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
|
717 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
|
718 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
|
719 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
|
720 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
|
721 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
|
722 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
|
723 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
|
724 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
|
725 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
|
726 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
|
727 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
|
728 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
|
729 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
|
730 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
|
731 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
|
732 |
|
|
|
733 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
|
734 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
|
735 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
|
736 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
|
737 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
|
738 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
|
739 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
|
740 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
|
741 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
|
742 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
|
743 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
|
744 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
|
745 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
|
746 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
|
747 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
|
748 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
|
749 |
|
|
end
|
750 |
|
|
`else
|
751 |
|
|
for ( i = 0; i < (1<<4); i = i + 1 ) begin
|
752 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
|
753 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
|
754 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
|
755 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
|
756 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
|
757 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
|
758 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
|
759 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
|
760 |
|
|
|
761 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
|
762 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
|
763 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
|
764 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
|
765 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
|
766 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
|
767 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
|
768 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
|
769 |
|
|
|
770 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
|
771 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
|
772 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
|
773 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
|
774 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
|
775 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
|
776 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
|
777 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
|
778 |
|
|
|
779 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
|
780 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
|
781 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
|
782 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
|
783 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
|
784 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
|
785 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
|
786 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
|
787 |
|
|
|
788 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
|
789 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
|
790 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
|
791 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
|
792 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
|
793 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
|
794 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
|
795 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
|
796 |
|
|
|
797 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
|
798 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
|
799 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
|
800 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
|
801 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
|
802 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
|
803 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
|
804 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
|
805 |
|
|
|
806 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
|
807 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
|
808 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
|
809 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
|
810 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
|
811 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
|
812 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
|
813 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
|
814 |
|
|
|
815 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
|
816 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
|
817 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
|
818 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
|
819 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
|
820 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
|
821 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
|
822 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
|
823 |
|
|
end
|
824 |
|
|
`endif
|
825 |
|
|
`else
|
826 |
|
|
for ( i = 0; i < (1<<5); i = i + 1 ) begin
|
827 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
|
828 |
|
|
minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
|
829 |
|
|
end
|
830 |
|
|
`endif
|
831 |
|
|
`endif
|
832 |
|
|
end
|
833 |
|
|
endtask
|
834 |
|
|
|
835 |
|
|
|
836 |
|
|
|
837 |
2 |
rfajardo |
endmodule
|
838 |
|
|
|