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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Blame information for rev 4

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`include "minsoc_bench_defines.v"
`include "minsoc_defines.v"
 
module minsoc_bench();
 
reg clock, reset;
 
wire dbg_tms_i;
wire dbg_tck_i;
wire dbg_tdi_i;
wire dbg_tdo_o;
wire jtag_vref;
wire jtag_gnd;
 
wire spi_mosi;
reg spi_miso;
wire spi_sclk;
wire [1:0] spi_ss;
 
wire uart_stx;
wire uart_srx;
 
wire eth_col;
wire eth_crs;
wire eth_trst;
wire eth_tx_clk;
wire eth_tx_en;
wire eth_tx_er;
wire [3:0] eth_txd;
wire eth_rx_clk;
wire eth_rx_dv;
wire eth_rx_er;
wire [3:0] eth_rxd;
wire eth_fds_mdint;
wire eth_mdc;
wire eth_mdio;
 
//
//      TASKS registers to communicate with interfaces
//
reg [7:0] tx_data [0:1518];               //receive buffer
reg [31:0] data_in [1023:0];              //send buffer
 
 
//
// Testbench mechanics
//
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
integer initialize, final, ptr;
reg [8*64:0] file_name;
reg load_file;
initial begin
        load_file = 1'b0;
`ifdef INITIALIZE_MEMORY_MODEL
        load_file = 1'b1;
`endif
`ifdef START_UP
        load_file = 1'b1;
`endif
        //get firmware hex file from command line input
        if ( load_file ) begin
                if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
                        $display("ERROR: please specify an input file to start.");
                        $finish;
                end
                $readmemh(file_name, program_mem);
                // First word comprehends size of program
                final = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };
        end
 
`ifdef INITIALIZE_MEMORY_MODEL
        // Initialize memory with firmware
        initialize = 0;
        while ( initialize < final ) begin
                minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];
                minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];
                minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];
                minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];
        initialize = initialize + 4;
        end
        $display("Memory model initialized with firmware:");
        $display("%s", file_name);
        $display("%d Bytes loaded from %d ...", initialize , final);
`endif
 
    // Reset controller
    repeat (2) @ (negedge clock);
    reset = 1'b1;
    repeat (16) @ (negedge clock);
    reset = 1'b0;
 
`ifdef START_UP
        // Pass firmware over spi to or1k_startup
        ptr = 0;
        //read dummy
        send_spi(program_mem[ptr]);
        send_spi(program_mem[ptr]);
        send_spi(program_mem[ptr]);
        send_spi(program_mem[ptr]);
        //~read dummy
        while ( ptr < final ) begin
                send_spi(program_mem[ptr]);
                ptr = ptr + 1;
        end
        $display("Memory start-up completed...");
        $display("Loaded firmware:");
        $display("%s", file_name);
`endif
        //
    // Testbench START
        //
 
 
end
 
 
//
// Modules instantiations
//
minsoc_top minsoc_top_0(
   .clk(clock),
   .reset(reset)
 
   //JTAG ports
`ifdef GENERIC_TAP
   , .jtag_tdi(dbg_tdi_i),
   .jtag_tms(dbg_tms_i),
   .jtag_tck(dbg_tck_i),
   .jtag_tdo(dbg_tdo_o),
   .jtag_vref(jtag_vref),
   .jtag_gnd(jtag_gnd)
`endif
 
   //SPI ports
`ifdef START_UP
   , .spi_flash_mosi(spi_mosi),
   .spi_flash_miso(spi_miso),
   .spi_flash_sclk(spi_sclk),
   .spi_flash_ss(spi_ss)
`endif
 
   //UART ports
`ifdef UART
   , .uart_stx(uart_stx),
   .uart_srx(uart_srx)
`endif // !UART
 
        // Ethernet ports
`ifdef ETHERNET
        , .eth_col(eth_col),
    .eth_crs(eth_crs),
    .eth_trste(eth_trst),
    .eth_tx_clk(eth_tx_clk),
        .eth_tx_en(eth_tx_en),
    .eth_tx_er(eth_tx_er),
    .eth_txd(eth_txd),
    .eth_rx_clk(eth_rx_clk),
        .eth_rx_dv(eth_rx_dv),
    .eth_rx_er(eth_rx_er),
    .eth_rxd(eth_rxd),
    .eth_fds_mdint(eth_fds_mdint),
        .eth_mdc(eth_mdc),
    .eth_mdio(eth_mdio)
`endif // !ETHERNET
);
 
`ifdef VPI_DEBUG
        dbg_comm_vpi dbg_if(
                .SYS_CLK(clock),
                .P_TMS(dbg_tms_i),
                .P_TCK(dbg_tck_i),
                .P_TRST(),
                .P_TDI(dbg_tdi_i),
                .P_TDO(dbg_tdo_o)
        );
`else
   assign dbg_tdi_i = 1;
   assign dbg_tck_i = 0;
   assign dbg_tms_i = 1;
`endif
 
`ifdef ETHERNET
eth_phy my_phy // This PHY model simulate simplified Intel LXT971A PHY
(
          // COMMON
          .m_rst_n_i(1'b1),
 
          // MAC TX
          .mtx_clk_o(eth_tx_clk),
          .mtxd_i(eth_txd),
          .mtxen_i(eth_tx_en),
          .mtxerr_i(eth_tx_er),
 
          // MAC RX
          .mrx_clk_o(eth_rx_clk),
          .mrxd_o(eth_rxd),
          .mrxdv_o(eth_rx_dv),
          .mrxerr_o(eth_rx_er),
 
          .mcoll_o(eth_col),
          .mcrs_o(eth_crs),
 
          // MIIM
          .mdc_i(eth_mdc),
          .md_io(eth_mdio),
 
          // SYSTEM
          .phy_log()
);
`endif // !ETHERNET
 
 
//
//      Regular clocking, reset and output
//
initial begin
    clock <= 1'b0;
    reset <= 1'b0;
 
end
 
always begin
    #((`CLK_PERIOD)/2) clock <= ~clock;
end
 
 
`ifdef VCD_OUTPUT
initial begin
        $dumpfile("../results/minsoc_wave.vcd");
        $dumpvars();
end
`endif
 
 
//
//      Functionalities tasks: SPI Startup and UART Monitor
//
//SPI START_UP
`ifdef START_UP
task send_spi;
    input [7:0] data_in;
    integer i;
    begin
        i = 7;
        for ( i = 7 ; i >= 0; i = i - 1 ) begin
                spi_miso = data_in[i];
                        @ (posedge spi_sclk);
            end
    end
endtask
`endif
//~SPI START_UP
 
//UART Monitor (prints uart output on the terminal)
`ifdef UART
parameter UART_TX_WAIT = (`FREQ / `UART_BAUDRATE) * `CLK_PERIOD;
 
// Something to trigger the task
always @(posedge clock)
        uart_decoder;
 
task uart_decoder;
        integer i;
        reg [7:0] tx_byte;
        begin
 
        // Wait for start bit
        while (uart_stx == 1'b1)
                @(uart_stx);
 
        #(UART_TX_WAIT+(UART_TX_WAIT/2));
 
    for ( i = 0; i < 8 ; i = i + 1 ) begin
                tx_byte[i] = uart_stx;
                #UART_TX_WAIT;
        end
 
        //Check for stop bit
        if (uart_stx == 1'b0) begin
                  //$display("* WARNING: user stop bit not received when expected at time %d__", $time);
          // Wait for return to idle
                while (uart_stx == 1'b0)
                        @(uart_stx);
          //$display("* USER UART returned to idle at time %d",$time);
        end
        // display the char
        $write("%c", tx_byte);
        end
endtask
`endif // !UART
//~UART Monitor
 
 
//
//      TASKS to communicate with interfaces
//
//MAC_DATA
//
`ifdef ETHERNET
reg [31:0] crc32_result;
 
task get_mac;
    integer conta;
    reg LSB;
    begin
        conta = 0;
        LSB = 1;
        @ ( posedge eth_tx_en);
        while ( eth_tx_en == 1'b1 ) begin
            @ (negedge eth_tx_clk) begin
                if ( LSB == 1'b1 )
                    tx_data[conta][3:0] = eth_txd;
                else begin
                    tx_data[conta][7:4] = eth_txd;
                    conta = conta + 1;
                end
                LSB = ~LSB;
            end
        end
    end
endtask
 
task send_mac;
    input [11:0] command;
    input [31:0] param1;
    input [31:0] param2;
    input [223:0] data;
 
    integer conta;
 
    begin
        //DEST MAC
        my_phy.rx_mem[0] = 8'h55;
        my_phy.rx_mem[1] = 8'h47;
        my_phy.rx_mem[2] = 8'h34;
        my_phy.rx_mem[3] = 8'h22;
        my_phy.rx_mem[4] = 8'h88;
        my_phy.rx_mem[5] = 8'h92;
 
        //SOURCE MAC
        my_phy.rx_mem[6] = 8'h00;
        my_phy.rx_mem[7] = 8'h00;
        my_phy.rx_mem[8] = 8'hC0;
        my_phy.rx_mem[9] = 8'h41;
        my_phy.rx_mem[10] = 8'h36;
        my_phy.rx_mem[11] = 8'hD3;
 
        //LEN
        my_phy.rx_mem[12] = 8'h00;
        my_phy.rx_mem[13] = 8'h04;
 
        //DATA
        my_phy.rx_mem[14] = 8'hFF;
        my_phy.rx_mem[15] = 8'hFA;
        my_phy.rx_mem[16] = command[11:4];
        my_phy.rx_mem[17] = { command[3:0] , 4'h7 };
 
        my_phy.rx_mem[18] = 8'hAA;
        my_phy.rx_mem[19] = 8'hAA;
 
        //parameter 1
        my_phy.rx_mem[20] = param1[31:24];
        my_phy.rx_mem[21] = param1[23:16];
        my_phy.rx_mem[22] = param1[15:8];
        my_phy.rx_mem[23] = param1[7:0];
 
        //parameter 2
        my_phy.rx_mem[24] = param2[31:24];
        my_phy.rx_mem[25] = param2[23:16];
        my_phy.rx_mem[26] = param2[15:8];
        my_phy.rx_mem[27] = param2[7:0];
 
        //data
        my_phy.rx_mem[28] = data[223:216];
        my_phy.rx_mem[29] = data[215:208];
        my_phy.rx_mem[30] = data[207:200];
        my_phy.rx_mem[31] = data[199:192];
        my_phy.rx_mem[32] = data[191:184];
        my_phy.rx_mem[33] = data[183:176];
        my_phy.rx_mem[34] = data[175:168];
        my_phy.rx_mem[35] = data[167:160];
        my_phy.rx_mem[36] = data[159:152];
        my_phy.rx_mem[37] = data[151:144];
        my_phy.rx_mem[38] = data[143:136];
        my_phy.rx_mem[39] = data[135:128];
        my_phy.rx_mem[40] = data[127:120];
        my_phy.rx_mem[41] = data[119:112];
        my_phy.rx_mem[42] = data[111:104];
        my_phy.rx_mem[43] = data[103:96];
        my_phy.rx_mem[44] = data[95:88];
        my_phy.rx_mem[45] = data[87:80];
        my_phy.rx_mem[46] = data[79:72];
        my_phy.rx_mem[47] = data[71:64];
        my_phy.rx_mem[48] = data[63:56];
        my_phy.rx_mem[49] = data[55:48];
        my_phy.rx_mem[50] = data[47:40];
        my_phy.rx_mem[51] = data[39:32];
        my_phy.rx_mem[52] = data[31:24];
        my_phy.rx_mem[53] = data[23:16];
        my_phy.rx_mem[54] = data[15:8];
        my_phy.rx_mem[55] = data[7:0];
 
        //PAD
        for ( conta = 56; conta < 60; conta = conta + 1 ) begin
            my_phy.rx_mem[conta] = 8'h00;
        end
 
        gencrc32;
 
        my_phy.rx_mem[60] = crc32_result[31:24];
        my_phy.rx_mem[61] = crc32_result[23:16];
        my_phy.rx_mem[62] = crc32_result[15:8];
        my_phy.rx_mem[63] = crc32_result[7:0];
 
        my_phy.send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, 32'h0000_0040, 1'b0 );
    end
 
endtask
 
//CRC32
parameter [31:0] CRC32_POLY = 32'h04C11DB7;
 
task gencrc32;
    integer     byte, bit;
    reg         msb;
    reg [7:0]    current_byte;
    reg [31:0]   temp;
 
    integer crc32_length;
 
    begin
        crc32_length = 60;
        crc32_result = 32'hffffffff;
        for (byte = 0; byte < crc32_length; byte = byte + 1) begin
            current_byte = my_phy.rx_mem[byte];
            for (bit = 0; bit < 8; bit = bit + 1) begin
                msb = crc32_result[31];
                crc32_result = crc32_result << 1;
                if (msb != current_byte[bit]) begin
                    crc32_result = crc32_result ^ CRC32_POLY;
                    crc32_result[0] = 1;
                end
            end
        end
 
        // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
        //
        // Mirror:
        for (bit = 0; bit < 32; bit = bit + 1)
            temp[31-bit] = crc32_result[bit];
 
        // Swap and Complement:
        crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
    end
endtask
//~CRC32
`endif // !ETHERNET
//~MAC_DATA
 
 
endmodule
 

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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	rfajardo	`include "minsoc_bench_defines.v"
2			`include "minsoc_defines.v"
3
4			`module minsoc_bench();`
5
6			`reg clock, reset;`
7
8			`wire dbg_tms_i;`
9			`wire dbg_tck_i;`
10			`wire dbg_tdi_i;`
11			`wire dbg_tdo_o;`
12			`wire jtag_vref;`
13			`wire jtag_gnd;`
14
15			`wire spi_mosi;`
16			`reg spi_miso;`
17			`wire spi_sclk;`
18			`wire [1:0] spi_ss;`
19
20			`wire uart_stx;`
21			`wire uart_srx;`
22
23			`wire eth_col;`
24			`wire eth_crs;`
25			`wire eth_trst;`
26			`wire eth_tx_clk;`
27			`wire eth_tx_en;`
28			`wire eth_tx_er;`
29			`wire [3:0] eth_txd;`
30			`wire eth_rx_clk;`
31			`wire eth_rx_dv;`
32			`wire eth_rx_er;`
33			`wire [3:0] eth_rxd;`
34			`wire eth_fds_mdint;`
35			`wire eth_mdc;`
36			`wire eth_mdio;`
37
38			`//`
39			`// TASKS registers to communicate with interfaces`
40			`//`
41			`reg [7:0] tx_data [0:1518]; //receive buffer`
42			`reg [31:0] data_in [1023:0]; //send buffer`
43
44
45			`//`
46			`// Testbench mechanics`
47			`//`
48	4	rfajardo	reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
49	2	rfajardo	`integer initialize, final, ptr;`
50			`reg [8*64:0] file_name;`
51			`reg load_file;`
52			`initial begin`
53			`load_file = 1'b0;`
54			`ifdef INITIALIZE_MEMORY_MODEL
55			`load_file = 1'b1;`
56			`endif
57			`ifdef START_UP
58			`load_file = 1'b1;`
59			`endif
60			`//get firmware hex file from command line input`
61			`if ( load_file ) begin`
62			`if ( ! $value$plusargs("file_name=%s", file_name) \|\| file_name == 0 ) begin`
63			`$display("ERROR: please specify an input file to start.");`
64			`$finish;`
65			`end`
66			`$readmemh(file_name, program_mem);`
67			`// First word comprehends size of program`
68			`final = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };`
69			`end`
70
71			`ifdef INITIALIZE_MEMORY_MODEL
72			`// Initialize memory with firmware`
73			`initialize = 0;`
74			`while ( initialize < final ) begin`
75			`minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];`
76			`minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];`
77			`minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];`
78			`minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];`
79			`initialize = initialize + 4;`
80			`end`
81			`$display("Memory model initialized with firmware:");`
82			`$display("%s", file_name);`
83			`$display("%d Bytes loaded from %d ...", initialize , final);`
84			`endif
85
86			`// Reset controller`
87			`repeat (2) @ (negedge clock);`
88			`reset = 1'b1;`
89			`repeat (16) @ (negedge clock);`
90			`reset = 1'b0;`
91
92			`ifdef START_UP
93			`// Pass firmware over spi to or1k_startup`
94			`ptr = 0;`
95			`//read dummy`
96			`send_spi(program_mem[ptr]);`
97			`send_spi(program_mem[ptr]);`
98			`send_spi(program_mem[ptr]);`
99			`send_spi(program_mem[ptr]);`
100			`//~read dummy`
101			`while ( ptr < final ) begin`
102			`send_spi(program_mem[ptr]);`
103			`ptr = ptr + 1;`
104			`end`
105			`$display("Memory start-up completed...");`
106			`$display("Loaded firmware:");`
107			`$display("%s", file_name);`
108			`endif
109			`//`
110			`// Testbench START`
111			`//`
112
113
114			`end`
115
116
117			`//`
118			`// Modules instantiations`
119			`//`
120			`minsoc_top minsoc_top_0(`
121			`.clk(clock),`
122			`.reset(reset)`
123
124			`//JTAG ports`
125			`ifdef GENERIC_TAP
126			`, .jtag_tdi(dbg_tdi_i),`
127			`.jtag_tms(dbg_tms_i),`
128			`.jtag_tck(dbg_tck_i),`
129			`.jtag_tdo(dbg_tdo_o),`
130			`.jtag_vref(jtag_vref),`
131			`.jtag_gnd(jtag_gnd)`
132			`endif
133
134			`//SPI ports`
135			`ifdef START_UP
136			`, .spi_flash_mosi(spi_mosi),`
137			`.spi_flash_miso(spi_miso),`
138			`.spi_flash_sclk(spi_sclk),`
139			`.spi_flash_ss(spi_ss)`
140			`endif
141
142			`//UART ports`
143			`ifdef UART
144			`, .uart_stx(uart_stx),`
145			`.uart_srx(uart_srx)`
146			`endif // !UART
147
148			`// Ethernet ports`
149			`ifdef ETHERNET
150			`, .eth_col(eth_col),`
151			`.eth_crs(eth_crs),`
152			`.eth_trste(eth_trst),`
153			`.eth_tx_clk(eth_tx_clk),`
154			`.eth_tx_en(eth_tx_en),`
155			`.eth_tx_er(eth_tx_er),`
156			`.eth_txd(eth_txd),`
157			`.eth_rx_clk(eth_rx_clk),`
158			`.eth_rx_dv(eth_rx_dv),`
159			`.eth_rx_er(eth_rx_er),`
160			`.eth_rxd(eth_rxd),`
161			`.eth_fds_mdint(eth_fds_mdint),`
162			`.eth_mdc(eth_mdc),`
163			`.eth_mdio(eth_mdio)`
164			`endif // !ETHERNET
165			`);`
166
167			`ifdef VPI_DEBUG
168			`dbg_comm_vpi dbg_if(`
169			`.SYS_CLK(clock),`
170			`.P_TMS(dbg_tms_i),`
171			`.P_TCK(dbg_tck_i),`
172			`.P_TRST(),`
173			`.P_TDI(dbg_tdi_i),`
174			`.P_TDO(dbg_tdo_o)`
175			`);`
176			`else
177			`assign dbg_tdi_i = 1;`
178			`assign dbg_tck_i = 0;`
179			`assign dbg_tms_i = 1;`
180			`endif
181
182			`ifdef ETHERNET
183			`eth_phy my_phy // This PHY model simulate simplified Intel LXT971A PHY`
184			`(`
185			`// COMMON`
186			`.m_rst_n_i(1'b1),`
187
188			`// MAC TX`
189			`.mtx_clk_o(eth_tx_clk),`
190			`.mtxd_i(eth_txd),`
191			`.mtxen_i(eth_tx_en),`
192			`.mtxerr_i(eth_tx_er),`
193
194			`// MAC RX`
195			`.mrx_clk_o(eth_rx_clk),`
196			`.mrxd_o(eth_rxd),`
197			`.mrxdv_o(eth_rx_dv),`
198			`.mrxerr_o(eth_rx_er),`
199
200			`.mcoll_o(eth_col),`
201			`.mcrs_o(eth_crs),`
202
203			`// MIIM`
204			`.mdc_i(eth_mdc),`
205			`.md_io(eth_mdio),`
206
207			`// SYSTEM`
208			`.phy_log()`
209			`);`
210			`endif // !ETHERNET
211
212
213			`//`
214			`// Regular clocking, reset and output`
215			`//`
216			`initial begin`
217			`clock <= 1'b0;`
218			`reset <= 1'b0;`
219
220			`end`
221
222			`always begin`
223			#((`CLK_PERIOD)/2) clock <= ~clock;
224			`end`
225
226
227			`ifdef VCD_OUTPUT
228			`initial begin`
229			`$dumpfile("../results/minsoc_wave.vcd");`
230			`$dumpvars();`
231			`end`
232			`endif
233
234
235			`//`
236			`// Functionalities tasks: SPI Startup and UART Monitor`
237			`//`
238			`//SPI START_UP`
239			`ifdef START_UP
240			`task send_spi;`
241			`input [7:0] data_in;`
242			`integer i;`
243			`begin`
244			`i = 7;`
245			`for ( i = 7 ; i >= 0; i = i - 1 ) begin`
246			`spi_miso = data_in[i];`
247			`@ (posedge spi_sclk);`
248			`end`
249			`end`
250			`endtask`
251			`endif
252			`//~SPI START_UP`
253
254			`//UART Monitor (prints uart output on the terminal)`
255			`ifdef UART
256			parameter UART_TX_WAIT = (`FREQ / `UART_BAUDRATE) * `CLK_PERIOD;
257
258			`// Something to trigger the task`
259			`always @(posedge clock)`
260			`uart_decoder;`
261
262			`task uart_decoder;`
263			`integer i;`
264			`reg [7:0] tx_byte;`
265			`begin`
266
267			`// Wait for start bit`
268			`while (uart_stx == 1'b1)`
269			`@(uart_stx);`
270
271			`#(UART_TX_WAIT+(UART_TX_WAIT/2));`
272
273			`for ( i = 0; i < 8 ; i = i + 1 ) begin`
274			`tx_byte[i] = uart_stx;`
275			`#UART_TX_WAIT;`
276			`end`
277
278			`//Check for stop bit`
279			`if (uart_stx == 1'b0) begin`
280			`//$display("* WARNING: user stop bit not received when expected at time %d__", $time);`
281			`// Wait for return to idle`
282			`while (uart_stx == 1'b0)`
283			`@(uart_stx);`
284			`//$display("* USER UART returned to idle at time %d",$time);`
285			`end`
286			`// display the char`
287			`$write("%c", tx_byte);`
288			`end`
289			`endtask`
290			`endif // !UART
291			`//~UART Monitor`
292
293
294			`//`
295			`// TASKS to communicate with interfaces`
296			`//`
297			`//MAC_DATA`
298			`//`
299			`ifdef ETHERNET
300			`reg [31:0] crc32_result;`
301
302			`task get_mac;`
303			`integer conta;`
304			`reg LSB;`
305			`begin`
306			`conta = 0;`
307			`LSB = 1;`
308			`@ ( posedge eth_tx_en);`
309			`while ( eth_tx_en == 1'b1 ) begin`
310			`@ (negedge eth_tx_clk) begin`
311			`if ( LSB == 1'b1 )`
312			`tx_data[conta][3:0] = eth_txd;`
313			`else begin`
314			`tx_data[conta][7:4] = eth_txd;`
315			`conta = conta + 1;`
316			`end`
317			`LSB = ~LSB;`
318			`end`
319			`end`
320			`end`
321			`endtask`
322
323			`task send_mac;`
324			`input [11:0] command;`
325			`input [31:0] param1;`
326			`input [31:0] param2;`
327			`input [223:0] data;`
328
329			`integer conta;`
330
331			`begin`
332			`//DEST MAC`
333			`my_phy.rx_mem[0] = 8'h55;`
334			`my_phy.rx_mem[1] = 8'h47;`
335			`my_phy.rx_mem[2] = 8'h34;`
336			`my_phy.rx_mem[3] = 8'h22;`
337			`my_phy.rx_mem[4] = 8'h88;`
338			`my_phy.rx_mem[5] = 8'h92;`
339
340			`//SOURCE MAC`
341			`my_phy.rx_mem[6] = 8'h00;`
342			`my_phy.rx_mem[7] = 8'h00;`
343			`my_phy.rx_mem[8] = 8'hC0;`
344			`my_phy.rx_mem[9] = 8'h41;`
345			`my_phy.rx_mem[10] = 8'h36;`
346			`my_phy.rx_mem[11] = 8'hD3;`
347
348			`//LEN`
349			`my_phy.rx_mem[12] = 8'h00;`
350			`my_phy.rx_mem[13] = 8'h04;`
351
352			`//DATA`
353			`my_phy.rx_mem[14] = 8'hFF;`
354			`my_phy.rx_mem[15] = 8'hFA;`
355			`my_phy.rx_mem[16] = command[11:4];`
356			`my_phy.rx_mem[17] = { command[3:0] , 4'h7 };`
357
358			`my_phy.rx_mem[18] = 8'hAA;`
359			`my_phy.rx_mem[19] = 8'hAA;`
360
361			`//parameter 1`
362			`my_phy.rx_mem[20] = param1[31:24];`
363			`my_phy.rx_mem[21] = param1[23:16];`
364			`my_phy.rx_mem[22] = param1[15:8];`
365			`my_phy.rx_mem[23] = param1[7:0];`
366
367			`//parameter 2`
368			`my_phy.rx_mem[24] = param2[31:24];`
369			`my_phy.rx_mem[25] = param2[23:16];`
370			`my_phy.rx_mem[26] = param2[15:8];`
371			`my_phy.rx_mem[27] = param2[7:0];`
372
373			`//data`
374			`my_phy.rx_mem[28] = data[223:216];`
375			`my_phy.rx_mem[29] = data[215:208];`
376			`my_phy.rx_mem[30] = data[207:200];`
377			`my_phy.rx_mem[31] = data[199:192];`
378			`my_phy.rx_mem[32] = data[191:184];`
379			`my_phy.rx_mem[33] = data[183:176];`
380			`my_phy.rx_mem[34] = data[175:168];`
381			`my_phy.rx_mem[35] = data[167:160];`
382			`my_phy.rx_mem[36] = data[159:152];`
383			`my_phy.rx_mem[37] = data[151:144];`
384			`my_phy.rx_mem[38] = data[143:136];`
385			`my_phy.rx_mem[39] = data[135:128];`
386			`my_phy.rx_mem[40] = data[127:120];`
387			`my_phy.rx_mem[41] = data[119:112];`
388			`my_phy.rx_mem[42] = data[111:104];`
389			`my_phy.rx_mem[43] = data[103:96];`
390			`my_phy.rx_mem[44] = data[95:88];`
391			`my_phy.rx_mem[45] = data[87:80];`
392			`my_phy.rx_mem[46] = data[79:72];`
393			`my_phy.rx_mem[47] = data[71:64];`
394			`my_phy.rx_mem[48] = data[63:56];`
395			`my_phy.rx_mem[49] = data[55:48];`
396			`my_phy.rx_mem[50] = data[47:40];`
397			`my_phy.rx_mem[51] = data[39:32];`
398			`my_phy.rx_mem[52] = data[31:24];`
399			`my_phy.rx_mem[53] = data[23:16];`
400			`my_phy.rx_mem[54] = data[15:8];`
401			`my_phy.rx_mem[55] = data[7:0];`
402
403			`//PAD`
404			`for ( conta = 56; conta < 60; conta = conta + 1 ) begin`
405			`my_phy.rx_mem[conta] = 8'h00;`
406			`end`
407
408			`gencrc32;`
409
410			`my_phy.rx_mem[60] = crc32_result[31:24];`
411			`my_phy.rx_mem[61] = crc32_result[23:16];`
412			`my_phy.rx_mem[62] = crc32_result[15:8];`
413			`my_phy.rx_mem[63] = crc32_result[7:0];`
414
415			`my_phy.send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, 32'h0000_0040, 1'b0 );`
416			`end`
417
418			`endtask`
419
420			`//CRC32`
421			`parameter [31:0] CRC32_POLY = 32'h04C11DB7;`
422
423			`task gencrc32;`
424			`integer byte, bit;`
425			`reg msb;`
426			`reg [7:0] current_byte;`
427			`reg [31:0] temp;`
428
429			`integer crc32_length;`
430
431			`begin`
432			`crc32_length = 60;`
433			`crc32_result = 32'hffffffff;`
434			`for (byte = 0; byte < crc32_length; byte = byte + 1) begin`
435			`current_byte = my_phy.rx_mem[byte];`
436			`for (bit = 0; bit < 8; bit = bit + 1) begin`
437			`msb = crc32_result[31];`
438			`crc32_result = crc32_result << 1;`
439			`if (msb != current_byte[bit]) begin`
440			`crc32_result = crc32_result ^ CRC32_POLY;`
441			`crc32_result[0] = 1;`
442			`end`
443			`end`
444			`end`
445
446			`// Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.`
447			`//`
448			`// Mirror:`
449			`for (bit = 0; bit < 32; bit = bit + 1)`
450			`temp[31-bit] = crc32_result[bit];`
451
452			`// Swap and Complement:`
453			`crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};`
454			`end`
455			`endtask`
456			`//~CRC32`
457			`endif // !ETHERNET
458			`//~MAC_DATA`
459
460
461			`endmodule`
462