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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench_defines.v] - Blame information for rev 42

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Line No. Rev Author Line
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`timescale 1ns/100ps
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//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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`define GENERIC_FPGA
6 28 rfajardo
`define NO_CLOCK_DIVISION   //if commented out, generic clock division is implemented (odd divisors are rounded down)
7 7 rfajardo
`define POSITIVE_RESET
8 2 rfajardo
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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10 28 rfajardo
`define FREQ_NUM_FOR_NS 1000000000
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`define FREQ 25000000
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`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
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15 17 rfajardo
`define ETH_PHY_FREQ  25000000
16 28 rfajardo
`define ETH_PHY_PERIOD  (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ)    //40ns
17 2 rfajardo
 
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`define UART_BAUDRATE 115200
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20 17 rfajardo
`define VPI_DEBUG
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22 2 rfajardo
//`define VCD_OUTPUT
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//`define START_UP                                              //pass firmware over spi to or1k_startup
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`define INITIALIZE_MEMORY_MODEL                 //instantaneously initialize memory model with firmware
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                                                                                //only use with the memory model (it is safe to 
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                                                                                //comment this and include the original memory instead)

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