OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [backend/] [de2_115_board/] [minsoc_defines.v] - Blame information for rev 168

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 158 rfajardo
//
2
// Define FPGA manufacturer: DE2_115 board
3
//
4
//`define GENERIC_FPGA
5
`define ALTERA_FPGA
6
//`define XILINX_FPGA
7
 
8
// 
9
// Define Xilinx FPGA family
10
//
11
`ifdef XILINX_FPGA
12
//`define SPARTAN2
13
//`define SPARTAN3
14
//`define SPARTAN3E
15
`define SPARTAN3A
16
//`define VIRTEX
17
//`define VIRTEX2
18
//`define VIRTEX4
19
//`define VIRTEX5
20
 
21
//
22
// Define Altera FPGA family
23
//
24
`elsif ALTERA_FPGA
25
//`define ARRIA_GX
26
//`define ARRIA_II_GX
27
//`define CYCLONE_I
28
//`define CYCLONE_II
29
//`define CYCLONE_III
30
//`define CYCLONE_III_LS
31
`define CYCLONE_IV_E
32
//`define CYCLONE_IV_GS
33
//`define MAX_II
34
//`define MAX_V
35
//`define MAX3000A
36
//`define MAX7000AE
37
//`define MAX7000B
38
//`define MAX7000S
39
//`define STRATIX
40
//`define STRATIX_II
41
//`define STRATIX_II_GX
42
//`define STRATIX_III
43
`endif
44
 
45
//
46
// Memory
47
//
48
`define MEMORY_ADR_WIDTH   13   //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, 
49
                                //memory is composed by blocks of address width 11
50
                                                                //Address width of memory -> select memory depth, 
51
                                //2 powers MEMORY_ADR_WIDTH defines the memory depth 
52
                                                                //the memory data width is 32 bit, 
53
                                //memory amount in Bytes = 4*memory depth
54
 
55
//
56
// Memory type  (uncomment something if ASIC or generic memory)
57
//
58
//`define GENERIC_MEMORY
59
//`define AVANT_ATP
60
//`define VIRAGE_SSP
61
//`define VIRTUALSILICON_SSP
62
 
63
 
64
//
65
// TAP selection
66
//
67
//`define GENERIC_TAP
68
`define FPGA_TAP
69
 
70
//
71
// Clock Division selection
72
//
73
//`define NO_CLOCK_DIVISION
74
//`define GENERIC_CLOCK_DIVISION
75
`define FPGA_CLOCK_DIVISION             // For Altera ALTPLL, only CYCLONE_III family has been tested.
76
 
77
//
78
// Define division
79
//
80
`define CLOCK_DIVISOR 2         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded 
81
                            //down to an even value in FPGA case, check minsoc_clock_manager 
82
                            //for allowed divisors.
83
                                            //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION 
84
                            //INSTEAD.
85
 
86
//
87
// Reset polarity
88
//
89
`define NEGATIVE_RESET      //rstn
90
//`define POSITIVE_RESET      //rst
91
 
92
//
93
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
94
//
95
//`define START_UP
96
 
97
//
98
// Connected modules
99
//
100
`define UART
101
`define JSP
102
//`define ETHERNET
103
 
104
//
105
// Ethernet reset
106
//
107
//`define ETH_RESET     1'b0
108
`define ETH_RESET       1'b1
109
 
110
//
111
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
112
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
113
//
114
`ifdef GENERIC_FPGA
115
    `undef FPGA_TAP
116
    `undef FPGA_CLOCK_DIVISION
117
    `undef ALTERA_FPGA
118
    `undef CYCLONE_IV_E
119
 
120
        `define GENERIC_TAP
121
        `define GENERIC_MEMORY
122
        `ifndef NO_CLOCK_DIVISION
123
                `define GENERIC_CLOCK_DIVISION
124
        `endif
125
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.