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[/] [minsoc/] [trunk/] [backend/] [ml509/] [ml509.ucf] - Blame information for rev 64

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1 40 rfajardo
NET  clk        LOC="AH15" | PERIOD=10ns | IOSTANDARD=LVCMOS33;  # Bank 4, Vcco=3.3V, No DCI
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NET  reset      LOC="E9" | PULLUP | IOSTANDARD=LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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NET  uart_srx   LOC="AG15" | IOSTANDARD=LVCMOS33;  # Bank 4, Vcco=3.3V, No DCI
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NET  uart_stx   LOC="AG20" | IOSTANDARD=LVCMOS33;  # Bank 4, Vcco=3.3V, No DCI
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## #------------------------------------------------------------------------------
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## # IO Pad Location Constraints / Properties for Ethernet
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## #------------------------------------------------------------------------------
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#NET eth_col        LOC = B32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
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#NET eth_crs        LOC = E34 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
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#NET eth_rx_dv         LOC = E32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
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#NET eth_rx_clk     LOC = H17 | IOSTANDARD = LVCMOS25;
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#NET eth_rxd<3> LOC = C32 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
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#NET eth_rxd<2> LOC = C33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
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#NET eth_rxd<1> LOC = B33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
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#NET eth_rxd<0> LOC = A33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
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#NET eth_rx_er      LOC = E33 | IOSTANDARD = LVCMOS25 | IOBDELAY=NONE;
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#NET eth_tx_clk     LOC = K17 | IOSTANDARD = LVCMOS25;
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#NET eth_trste    LOC = J14  | IOSTANDARD = LVCMOS25 | PULLUP | TIG; # PHY_RESET pin on phy
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#NET eth_txd<3> LOC = AH10 | IOSTANDARD = LVDCI_33;
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#NET eth_txd<2> LOC = AH9 | IOSTANDARD = LVDCI_33;
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#NET eth_txd<1> LOC = AE11 | IOSTANDARD = LVDCI_33;
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#NET eth_txd<0> LOC = AF11 | IOSTANDARD = LVDCI_33;
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#NET eth_tx_en      LOC = AJ10 | IOSTANDARD = LVDCI_33;
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#NET eth_tx_er      LOC = AJ9 | IOSTANDARD = LVDCI_33;
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## PHY Serial Management Interface pins
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#NET eth_mdc   LOC = H19 | IOSTANDARD = LVCMOS25;
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#NET eth_mdio   LOC = H13 | IOSTANDARD = LVCMOS25;
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## # Timing Constraints (these are recommended in documentation and
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## # are unaltered except for the TIG)
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#NET "eth_rx_clk_BUFGP" TNM_NET = "RXCLK_GRP";
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#NET "eth_tx_clk_BUFGP" TNM_NET = "TXCLK_GRP";
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#TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
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#TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
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## # Timing ignores (to specify unconstrained paths)
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#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock
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#TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
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#TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
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#TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
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#TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;

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