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[/] [minsoc/] [trunk/] [backend/] [nexys2_1200/] [nexys2_1200.ucf] - Blame information for rev 165

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Line No. Rev Author Line
1 165 rfajardo
#
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# Soldered 50MHz clock.
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#
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NET "clk" LOC = "B8";
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#
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# Use button "BTN0" as reset.
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#
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NET "reset" LOC = "B18" | PULLDOWN ;
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#
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# UART serial port (RS232 DCE) - connector DB9 female.
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#
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NET "uart_srx" LOC = "U6";
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NET "uart_stx" LOC = "P9" | DRIVE = 8 | SLEW = SLOW ;
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# Pins below are probably invalid since they are simply a copy of spartan3e_starter_kit configuration.
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# They are still kept here because the signal list is still useful for adaptations.
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###########################
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##
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## ETH
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##
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#NET "eth_txd(3)" LOC = "t5";
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#NET "eth_txd(2)" LOC = "r5";
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#NET "eth_txd(1)" LOC = "t15";
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#NET "eth_txd(0)" LOC = "r11";
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#
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#NET "eth_tx_en" LOC = "p15";
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#NET "eth_tx_clk" LOC = "t7" | CLOCK_DEDICATED_ROUTE = FALSE;
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#NET "eth_tx_er" LOC = "r6";
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#
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#NET "eth_rxd(3)" LOC = "v14";
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#NET "eth_rxd(2)" LOC = "u11";
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#NET "eth_rxd(1)" LOC = "t11";
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#NET "eth_rxd(0)" LOC = "v8";
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#
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#NET "eth_rx_er" LOC = "u14";
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#NET "eth_rx_dv" LOC = "v2";
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#
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#NET "eth_rx_clk" LOC = "v3" | CLOCK_DEDICATED_ROUTE = FALSE;
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#
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#NET "eth_mdio" LOC = "u5" | PULLUP;
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#NET "eth_crs" LOC = "u13";
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#NET "eth_col" LOC = "u6";
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#NET "eth_mdc" LOC = "p9";
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#
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#NET "eth_trste" LOC = "p13";                   #put it to a non connected FPGA pin (starter kit schematic BANK3)
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#
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#NET "eth_fds_mdint" LOC = "r13" | PULLUP;      #put it to a non connected FPGA pin (starter kit schematic BANK3)(pullup not to generate interrupts)
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###########################
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#
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# JTAG signals - on J4 6-pin accessory header.
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#
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#NET "jtag_tms"  LOC = "D7" | PULLDOWN ;
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#NET "jtag_tdi"  LOC = "C7" | PULLDOWN ;
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#NET "jtag_tdo"  LOC = "F8" | SLEW = FAST | DRIVE = 8 ;
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#NET "jtag_tck"  LOC = "E8" | PULLDOWN ;
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#net "jtag_gnd" loc = "k2";                     #put it to a non connected FPGA pin (starter kit schematic BANK3)
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#net "jtag_vref" loc = "k7";                    #put it to a non connected FPGA pin (starter kit schematic BANK3)
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#
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# End of file.
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#

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