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[/] [minsoc/] [trunk/] [backend/] [nexys3/] [minsoc_defines.v] - Blame information for rev 173

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Line No. Rev Author Line
1 173 rfajardo
//
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// Define FPGA manufacturer
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//
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//`define GENERIC_FPGA
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//`define ALTERA_FPGA
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`define XILINX_FPGA
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// 
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// Define Xilinx FPGA family
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//
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`ifdef XILINX_FPGA
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//`define SPARTAN2
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//`define SPARTAN3
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//`define SPARTAN3E
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//`define SPARTAN3A
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`define SPARTAN6
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//`define VIRTEX
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//`define VIRTEX2
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//`define VIRTEX4
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//`define VIRTEX5
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//
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// Define Altera FPGA family
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//
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`elsif ALTERA_FPGA
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//`define ARRIA_GX
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//`define ARRIA_II_GX
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//`define CYCLONE_I
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//`define CYCLONE_II
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`define CYCLONE_III
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//`define CYCLONE_III_LS
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//`define CYCLONE_IV_E
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//`define CYCLONE_IV_GS
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//`define MAX_II
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//`define MAX_V
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//`define MAX3000A
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//`define MAX7000AE
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//`define MAX7000B
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//`define MAX7000S
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//`define STRATIX
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//`define STRATIX_II
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//`define STRATIX_II_GX
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//`define STRATIX_III
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`endif
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//
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// Memory
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//
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`define MEMORY_ADR_WIDTH   13   //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, 
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                                //memory is composed by blocks of address width 11
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                                                                //Address width of memory -> select memory depth, 
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                                //2 powers MEMORY_ADR_WIDTH defines the memory depth 
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                                                                //the memory data width is 32 bit, 
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                                //memory amount in Bytes = 4*memory depth
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//
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// Memory type  (uncomment something if ASIC or generic memory)
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//
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//`define GENERIC_MEMORY
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//`define AVANT_ATP
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//`define VIRAGE_SSP
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//`define VIRTUALSILICON_SSP
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//
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// TAP selection
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//
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//`define GENERIC_TAP
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`define FPGA_TAP
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//
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// Clock Division selection
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//
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//`define NO_CLOCK_DIVISION
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//`define GENERIC_CLOCK_DIVISION
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`define FPGA_CLOCK_DIVISION             // For Altera ALTPLL, only CYCLONE_III family has been tested.
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//
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// Define division
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//
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`define CLOCK_DIVISOR 5         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded 
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                            //down to an even value in FPGA case, check minsoc_clock_manager 
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                            //for allowed divisors.
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                                            //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION 
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                            //INSTEAD.
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//
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// Reset polarity
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//
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`define NEGATIVE_RESET      //rstn
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//`define POSITIVE_RESET      //rst
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//
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// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
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//
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//`define START_UP
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//
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// Connected modules
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//
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`define UART
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//`define JSP
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//`define ETHERNET
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//
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// Ethernet reset
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//
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//`define ETH_RESET     1'b0
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`define ETH_RESET       1'b1
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//
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// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
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// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
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//
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`ifdef GENERIC_FPGA
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    `undef FPGA_TAP
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    `undef FPGA_CLOCK_DIVISION
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    `undef XILINX_FPGA
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    `undef SPARTAN6
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        `define GENERIC_TAP
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        `define GENERIC_MEMORY
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        `ifndef NO_CLOCK_DIVISION
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                `define GENERIC_CLOCK_DIVISION
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        `endif
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`endif

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