OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit/] [or1200_defines.v] - Blame information for rev 92

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 66 rfajardo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's definitions                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://opencores.org/project,or1k                           ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Defines for the OR1200 core                                 ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add parameters that are missing                          ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// $Log: or1200_defines.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, bugs fixed. 
48
 
49
//
50
// Dump VCD
51
//
52
//`define OR1200_VCD_DUMP
53
 
54
//
55
// Generate debug messages during simulation
56
//
57
//`define OR1200_VERBOSE
58
 
59
//  `define OR1200_ASIC
60
////////////////////////////////////////////////////////
61
//
62
// Typical configuration for an ASIC
63
//
64
`ifdef OR1200_ASIC
65
 
66
//
67
// Target ASIC memories
68
//
69
//`define OR1200_ARTISAN_SSP
70
//`define OR1200_ARTISAN_SDP
71
//`define OR1200_ARTISAN_STP
72
`define OR1200_VIRTUALSILICON_SSP
73
//`define OR1200_VIRTUALSILICON_STP_T1
74
//`define OR1200_VIRTUALSILICON_STP_T2
75
 
76
//
77
// Do not implement Data cache
78
//
79
//`define OR1200_NO_DC
80
 
81
//
82
// Do not implement Insn cache
83
//
84
//`define OR1200_NO_IC
85
 
86
//
87
// Do not implement Data MMU
88
//
89
//`define OR1200_NO_DMMU
90
 
91
//
92
// Do not implement Insn MMU
93
//
94
//`define OR1200_NO_IMMU
95
 
96
//
97
// Select between ASIC optimized and generic multiplier
98
//
99
//`define OR1200_ASIC_MULTP2_32X32
100
`define OR1200_GENERIC_MULTP2_32X32
101
 
102
//
103
// Size/type of insn/data cache if implemented
104
//
105
// `define OR1200_IC_1W_512B
106
// `define OR1200_IC_1W_4KB
107
`define OR1200_IC_1W_8KB
108
// `define OR1200_DC_1W_4KB
109
`define OR1200_DC_1W_8KB
110
 
111
`else
112
 
113
 
114
/////////////////////////////////////////////////////////
115
//
116
// Typical configuration for an FPGA
117
//
118
 
119
//
120
// Target FPGA memories
121
//
122
//`define OR1200_ALTERA_LPM
123
//`define OR1200_XILINX_RAMB16
124
//`define OR1200_XILINX_RAMB4
125
//`define OR1200_XILINX_RAM32X1D
126
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
127
// Generic models should infer RAM blocks at synthesis time (not only effects 
128
// single port ram.)
129
`define OR1200_GENERIC
130
 
131
//
132
// Do not implement Data cache
133
//
134
`define OR1200_NO_DC
135
 
136
//
137
// Do not implement Insn cache
138
//
139
`define OR1200_NO_IC
140
 
141
//
142
// Do not implement Data MMU
143
//
144
`define OR1200_NO_DMMU
145
 
146
//
147
// Do not implement Insn MMU
148
//
149
`define OR1200_NO_IMMU
150
 
151
//
152
// Select between ASIC and generic multiplier
153
//
154
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
155
//
156
//`define OR1200_ASIC_MULTP2_32X32
157
`define OR1200_GENERIC_MULTP2_32X32
158
 
159
//
160
// Size/type of insn/data cache if implemented
161
// (consider available FPGA memory resources)
162
//
163
//`define OR1200_IC_1W_512B
164
//`define OR1200_IC_1W_4KB
165
`define OR1200_IC_1W_8KB
166
//`define OR1200_IC_1W_16KB
167
//`define OR1200_IC_1W_32KB
168
//`define OR1200_DC_1W_4KB
169
`define OR1200_DC_1W_8KB
170
//`define OR1200_DC_1W_16KB
171
//`define OR1200_DC_1W_32KB
172
 
173
`endif
174
 
175
 
176
//////////////////////////////////////////////////////////
177
//
178
// Do not change below unless you know what you are doing
179
//
180
 
181
//
182
// Reset active low
183
//
184
//`define OR1200_RST_ACT_LOW
185
 
186
//
187
// Enable RAM BIST
188
//
189
// At the moment this only works for Virtual Silicon
190
// single port RAMs. For other RAMs it has not effect.
191
// Special wrapper for VS RAMs needs to be provided
192
// with scan flops to facilitate bist scan.
193
//
194
//`define OR1200_BIST
195
 
196
//
197
// Register OR1200 WISHBONE outputs
198
// (must be defined/enabled)
199
//
200
`define OR1200_REGISTERED_OUTPUTS
201
 
202
//
203
// Register OR1200 WISHBONE inputs
204
//
205
// (must be undefined/disabled)
206
//
207
//`define OR1200_REGISTERED_INPUTS
208
 
209
//
210
// Disable bursts if they are not supported by the
211
// memory subsystem (only affect cache line fill)
212
//
213
//`define OR1200_NO_BURSTS
214
//
215
 
216
//
217
// WISHBONE retry counter range
218
//
219
// 2^value range for retry counter. Retry counter
220
// is activated whenever *wb_rty_i is asserted and
221
// until retry counter expires, corresponding
222
// WISHBONE interface is deactivated.
223
//
224
// To disable retry counters and *wb_rty_i all together,
225
// undefine this macro.
226
//
227
//`define OR1200_WB_RETRY 7
228
 
229
//
230
// WISHBONE Consecutive Address Burst
231
//
232
// This was used prior to WISHBONE B3 specification
233
// to identify bursts. It is no longer needed but
234
// remains enabled for compatibility with old designs.
235
//
236
// To remove *wb_cab_o ports undefine this macro.
237
//
238
//`define OR1200_WB_CAB
239
 
240
//
241
// WISHBONE B3 compatible interface
242
//
243
// This follows the WISHBONE B3 specification.
244
// It is not enabled by default because most
245
// designs still don't use WB b3.
246
//
247
// To enable *wb_cti_o/*wb_bte_o ports,
248
// define this macro.
249
//
250
`define OR1200_WB_B3
251
 
252
//
253
// LOG all WISHBONE accesses
254
//
255
`define OR1200_LOG_WB_ACCESS
256
 
257
//
258
// Enable additional synthesis directives if using
259
// _Synopsys_ synthesis tool
260
//
261
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
262
 
263
//
264
// Enables default statement in some case blocks
265
// and disables Synopsys synthesis directive full_case
266
//
267
// By default it is enabled. When disabled it
268
// can increase clock frequency.
269
//
270
`define OR1200_CASE_DEFAULT
271
 
272
//
273
// Operand width / register file address width
274
//
275
// (DO NOT CHANGE)
276
//
277
`define OR1200_OPERAND_WIDTH            32
278
`define OR1200_REGFILE_ADDR_WIDTH       5
279
 
280
//
281
// l.add/l.addi/l.and and optional l.addc/l.addic
282
// also set (compare) flag when result of their
283
// operation equals zero
284
//
285
// At the time of writing this, default or32
286
// C/C++ compiler doesn't generate code that
287
// would benefit from this optimization.
288
//
289
// By default this optimization is disabled to
290
// save area.
291
//
292
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
293
 
294
//
295
// Implement l.addc/l.addic instructions
296
//
297
// By default implementation of l.addc/l.addic
298
// instructions is enabled in case you need them.
299
// If you don't use them, then disable implementation
300
// to save area.
301
//
302 92 rfajardo
`define OR1200_IMPL_ADDC
303 66 rfajardo
 
304
//
305
// Implement l.sub instruction
306
//
307
// By default implementation of l.sub instructions
308
// is enabled to be compliant with the simulator.
309
// If you don't use carry bit, then disable
310
// implementation to save area.
311
//
312
`define OR1200_IMPL_SUB
313
 
314
//
315
// Implement carry bit SR[CY]
316
//
317
//
318
// By default implementation of SR[CY] is enabled
319
// to be compliant with the simulator. However SR[CY]
320
// is explicitly only used by l.addc/l.addic/l.sub
321
// instructions and if these three insns are not
322
// implemented there is not much point having SR[CY].
323
//
324 92 rfajardo
`define OR1200_IMPL_CY
325 66 rfajardo
 
326
//
327 92 rfajardo
// Implement carry bit SR[OV]
328
//
329
// Compiler doesn't use this, but other code may like
330
// to.
331
//
332
`define OR1200_IMPL_OV
333
 
334
//
335
// Implement carry bit SR[OVE]
336
//
337
// Overflow interrupt indicator. When enabled, SR[OV] flag
338
// does not remain asserted after exception.
339
//
340
`define OR1200_IMPL_OVE
341
 
342
 
343
//
344 66 rfajardo
// Implement rotate in the ALU
345
//
346
// At the time of writing this, or32
347
// C/C++ compiler doesn't generate rotate
348
// instructions. However or32 assembler
349
// can assemble code that uses rotate insn.
350
// This means that rotate instructions
351
// must be used manually inserted.
352
//
353
// By default implementation of rotate
354
// is disabled to save area and increase
355
// clock frequency.
356
//
357
//`define OR1200_IMPL_ALU_ROTATE
358
 
359
//
360
// Type of ALU compare to implement
361
//
362 92 rfajardo
// Try to find which synthesizes with
363
// most efficient logic use or highest speed.
364 66 rfajardo
//
365
//`define OR1200_IMPL_ALU_COMP1
366 92 rfajardo
//`define OR1200_IMPL_ALU_COMP2
367
`define OR1200_IMPL_ALU_COMP3
368 66 rfajardo
 
369
//
370
// Implement Find First/Last '1'
371
//
372
`define OR1200_IMPL_ALU_FFL1
373
 
374
//
375 92 rfajardo
// Implement l.cust5 ALU instruction
376
//
377
//`define OR1200_IMPL_ALU_CUST5
378
 
379
//
380
// Implement l.extXs and l.extXz instructions
381
//
382
`define OR1200_IMPL_ALU_EXT
383
 
384
//
385 66 rfajardo
// Implement multiplier
386
//
387
// By default multiplier is implemented
388
//
389
`define OR1200_MULT_IMPLEMENTED
390
 
391
//
392
// Implement multiply-and-accumulate
393
//
394
// By default MAC is implemented. To
395
// implement MAC, multiplier (non-serial) needs to be
396
// implemented.
397
//
398
//`define OR1200_MAC_IMPLEMENTED
399
 
400
//
401
// Implement optional l.div/l.divu instructions
402
//
403
// By default divide instructions are not implemented
404
// to save area.
405
//
406
//
407
`define OR1200_DIV_IMPLEMENTED
408
 
409
//
410
// Serial multiplier.
411
//
412
//`define OR1200_MULT_SERIAL
413
 
414
//
415
// Serial divider.
416
// Uncomment to use a serial divider, otherwise will
417
// be a generic parallel implementation.
418
//
419
`define OR1200_DIV_SERIAL
420
 
421
//
422
// Implement HW Single Precision FPU
423
//
424
//`define OR1200_FPU_IMPLEMENTED
425
 
426
//
427
// Clock ratio RISC clock versus WB clock
428
//
429
// If you plan to run WB:RISC clock fixed to 1:1, disable
430
// both defines
431
//
432
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
433
// and use clmode to set ratio
434
//
435
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
436
// clmode to set ratio
437
//
438
//`define OR1200_CLKDIV_2_SUPPORTED
439
//`define OR1200_CLKDIV_4_SUPPORTED
440
 
441
//
442
// Type of register file RAM
443
//
444
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
445
//`define OR1200_RFRAM_TWOPORT
446
//
447
// Memory macro dual port (see or1200_dpram.v)
448
`define OR1200_RFRAM_DUALPORT
449
 
450
//
451
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
452
//`define OR1200_RFRAM_GENERIC
453
//  Generic register file supports - 16 registers 
454
`ifdef OR1200_RFRAM_GENERIC
455
//    `define OR1200_RFRAM_16REG
456
`endif
457
 
458
//
459
// Type of mem2reg aligner to implement.
460
//
461
// Once OR1200_IMPL_MEM2REG2 yielded faster
462
// circuit, however with today tools it will
463
// most probably give you slower circuit.
464
//
465
`define OR1200_IMPL_MEM2REG1
466
//`define OR1200_IMPL_MEM2REG2
467
 
468
//
469
// Reset value and event
470
//
471
`ifdef OR1200_RST_ACT_LOW
472
  `define OR1200_RST_VALUE      (1'b0)
473
  `define OR1200_RST_EVENT      negedge
474
`else
475
  `define OR1200_RST_VALUE      (1'b1)
476
  `define OR1200_RST_EVENT      posedge
477
`endif
478
 
479
//
480
// ALUOPs
481
//
482 92 rfajardo
`define OR1200_ALUOP_WIDTH      5
483
`define OR1200_ALUOP_NOP        5'b0_0100
484
/* LS-nibble encodings correspond to bits [3:0] of instruction */
485
`define OR1200_ALUOP_ADD        5'b0_0000 // 0
486
`define OR1200_ALUOP_ADDC       5'b0_0001 // 1
487
`define OR1200_ALUOP_SUB        5'b0_0010 // 2
488
`define OR1200_ALUOP_AND        5'b0_0011 // 3
489
`define OR1200_ALUOP_OR         5'b0_0100 // 4
490
`define OR1200_ALUOP_XOR        5'b0_0101 // 5
491
`define OR1200_ALUOP_MUL        5'b0_0110 // 6
492
`define OR1200_ALUOP_RESERVED   5'b0_0111 // 7
493
`define OR1200_ALUOP_SHROT      5'b0_1000 // 8
494
`define OR1200_ALUOP_DIV        5'b0_1001 // 9
495
`define OR1200_ALUOP_DIVU       5'b0_1010 // a
496
`define OR1200_ALUOP_MULU       5'b0_1011 // b
497
`define OR1200_ALUOP_EXTHB      5'b0_1100 // c
498
`define OR1200_ALUOP_EXTW       5'b0_1101 // d
499
`define OR1200_ALUOP_CMOV       5'b0_1110 // e
500
`define OR1200_ALUOP_FFL1       5'b0_1111 // f
501 66 rfajardo
 
502 92 rfajardo
/* Values sent to ALU from decode unit - not defined by ISA */
503
`define OR1200_ALUOP_COMP       5'b1_0000 // Comparison
504
`define OR1200_ALUOP_MOVHI      5'b1_0001 // Move-high
505
`define OR1200_ALUOP_CUST5      5'b1_0010 // l.cust5
506 66 rfajardo
 
507 92 rfajardo
// ALU instructions second opcode field
508
`define OR1200_ALUOP2_POS       9:6
509
`define OR1200_ALUOP2_WIDTH     4
510 66 rfajardo
 
511
//
512
// MACOPs
513
//
514
`define OR1200_MACOP_WIDTH      3
515
`define OR1200_MACOP_NOP        3'b000
516
`define OR1200_MACOP_MAC        3'b001
517
`define OR1200_MACOP_MSB        3'b010
518
 
519
//
520
// Shift/rotate ops
521
//
522 92 rfajardo
`define OR1200_SHROTOP_WIDTH    4
523
`define OR1200_SHROTOP_NOP      4'd0
524
`define OR1200_SHROTOP_SLL      4'd0
525
`define OR1200_SHROTOP_SRL      4'd1
526
`define OR1200_SHROTOP_SRA      4'd2
527
`define OR1200_SHROTOP_ROR      4'd3
528 66 rfajardo
 
529 92 rfajardo
//
530
// Zero/Sign Extend ops
531
//
532
`define OR1200_EXTHBOP_WIDTH      4
533
`define OR1200_EXTHBOP_BS         4'h1
534
`define OR1200_EXTHBOP_HS         4'h0
535
`define OR1200_EXTHBOP_BZ         4'h3
536
`define OR1200_EXTHBOP_HZ         4'h2
537
`define OR1200_EXTWOP_WIDTH       4
538
`define OR1200_EXTWOP_WS          4'h0
539
`define OR1200_EXTWOP_WZ          4'h1
540
 
541 66 rfajardo
// Execution cycles per instruction
542
`define OR1200_MULTICYCLE_WIDTH 3
543
`define OR1200_ONE_CYCLE                3'd0
544
`define OR1200_TWO_CYCLES               3'd1
545
 
546
// Execution control which will "wait on" a module to finish
547
`define OR1200_WAIT_ON_WIDTH 2
548 92 rfajardo
`define OR1200_WAIT_ON_NOTHING    `OR1200_WAIT_ON_WIDTH'd0
549
`define OR1200_WAIT_ON_MULTMAC    `OR1200_WAIT_ON_WIDTH'd1
550
`define OR1200_WAIT_ON_FPU        `OR1200_WAIT_ON_WIDTH'd2
551
`define OR1200_WAIT_ON_MTSPR      `OR1200_WAIT_ON_WIDTH'd3
552 66 rfajardo
 
553 92 rfajardo
 
554 66 rfajardo
// Operand MUX selects
555
`define OR1200_SEL_WIDTH                2
556
`define OR1200_SEL_RF                   2'd0
557
`define OR1200_SEL_IMM                  2'd1
558
`define OR1200_SEL_EX_FORW              2'd2
559
`define OR1200_SEL_WB_FORW              2'd3
560
 
561
//
562
// BRANCHOPs
563
//
564
`define OR1200_BRANCHOP_WIDTH           3
565
`define OR1200_BRANCHOP_NOP             3'd0
566
`define OR1200_BRANCHOP_J               3'd1
567
`define OR1200_BRANCHOP_JR              3'd2
568
`define OR1200_BRANCHOP_BAL             3'd3
569
`define OR1200_BRANCHOP_BF              3'd4
570
`define OR1200_BRANCHOP_BNF             3'd5
571
`define OR1200_BRANCHOP_RFE             3'd6
572
 
573
//
574
// LSUOPs
575
//
576
// Bit 0: sign extend
577
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
578
// Bit 3: 0 load, 1 store
579
`define OR1200_LSUOP_WIDTH              4
580
`define OR1200_LSUOP_NOP                4'b0000
581
`define OR1200_LSUOP_LBZ                4'b0010
582
`define OR1200_LSUOP_LBS                4'b0011
583
`define OR1200_LSUOP_LHZ                4'b0100
584
`define OR1200_LSUOP_LHS                4'b0101
585
`define OR1200_LSUOP_LWZ                4'b0110
586
`define OR1200_LSUOP_LWS                4'b0111
587
`define OR1200_LSUOP_LD                 4'b0001
588
`define OR1200_LSUOP_SD                 4'b1000
589
`define OR1200_LSUOP_SB                 4'b1010
590
`define OR1200_LSUOP_SH                 4'b1100
591
`define OR1200_LSUOP_SW                 4'b1110
592
 
593
// Number of bits of load/store EA precalculated in ID stage
594
// for balancing ID and EX stages.
595
//
596
// Valid range: 2,3,...,30,31
597
`define OR1200_LSUEA_PRECALC            2
598
 
599
// FETCHOPs
600
`define OR1200_FETCHOP_WIDTH            1
601
`define OR1200_FETCHOP_NOP              1'b0
602
`define OR1200_FETCHOP_LW               1'b1
603
 
604
//
605
// Register File Write-Back OPs
606
//
607
// Bit 0: register file write enable
608
// Bits 3-1: write-back mux selects
609
//
610
`define OR1200_RFWBOP_WIDTH             4
611
`define OR1200_RFWBOP_NOP               4'b0000
612
`define OR1200_RFWBOP_ALU               3'b000
613
`define OR1200_RFWBOP_LSU               3'b001
614
`define OR1200_RFWBOP_SPRS              3'b010
615
`define OR1200_RFWBOP_LR                3'b011
616
`define OR1200_RFWBOP_FPU               3'b100
617
 
618
// Compare instructions
619
`define OR1200_COP_SFEQ       3'b000
620
`define OR1200_COP_SFNE       3'b001
621
`define OR1200_COP_SFGT       3'b010
622
`define OR1200_COP_SFGE       3'b011
623
`define OR1200_COP_SFLT       3'b100
624
`define OR1200_COP_SFLE       3'b101
625
`define OR1200_COP_X          3'b111
626
`define OR1200_SIGNED_COMPARE 'd3
627
`define OR1200_COMPOP_WIDTH     4
628
 
629
//
630
// FP OPs
631
//
632
// MSbit indicates FPU operation valid
633
//
634
`define OR1200_FPUOP_WIDTH      8
635
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
636
`define OR1200_FPUOP_CYCLES 3'd4
637
// FP instruction is double precision if bit 4 is set. We're a 32-bit 
638
// implementation thus do not support double precision FP 
639
`define OR1200_FPUOP_DOUBLE_BIT 4
640
`define OR1200_FPUOP_ADD  8'b0000_0000
641
`define OR1200_FPUOP_SUB  8'b0000_0001
642
`define OR1200_FPUOP_MUL  8'b0000_0010
643
`define OR1200_FPUOP_DIV  8'b0000_0011
644
`define OR1200_FPUOP_ITOF 8'b0000_0100
645
`define OR1200_FPUOP_FTOI 8'b0000_0101
646
`define OR1200_FPUOP_REM  8'b0000_0110
647
`define OR1200_FPUOP_RESERVED  8'b0000_0111
648
// FP Compare instructions
649
`define OR1200_FPCOP_SFEQ 8'b0000_1000
650
`define OR1200_FPCOP_SFNE 8'b0000_1001
651
`define OR1200_FPCOP_SFGT 8'b0000_1010
652
`define OR1200_FPCOP_SFGE 8'b0000_1011
653
`define OR1200_FPCOP_SFLT 8'b0000_1100
654
`define OR1200_FPCOP_SFLE 8'b0000_1101
655
 
656
//
657
// TAGs for instruction bus
658
//
659
`define OR1200_ITAG_IDLE        4'h0    // idle bus
660
`define OR1200_ITAG_NI          4'h1    // normal insn
661
`define OR1200_ITAG_BE          4'hb    // Bus error exception
662
`define OR1200_ITAG_PE          4'hc    // Page fault exception
663
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
664
 
665
//
666
// TAGs for data bus
667
//
668
`define OR1200_DTAG_IDLE        4'h0    // idle bus
669
`define OR1200_DTAG_ND          4'h1    // normal data
670
`define OR1200_DTAG_AE          4'ha    // Alignment exception
671
`define OR1200_DTAG_BE          4'hb    // Bus error exception
672
`define OR1200_DTAG_PE          4'hc    // Page fault exception
673
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
674
 
675
 
676
//////////////////////////////////////////////
677
//
678
// ORBIS32 ISA specifics
679
//
680
 
681
// SHROT_OP position in machine word
682
`define OR1200_SHROTOP_POS              7:6
683
 
684
//
685
// Instruction opcode groups (basic)
686
//
687
`define OR1200_OR32_J                 6'b000000
688
`define OR1200_OR32_JAL               6'b000001
689
`define OR1200_OR32_BNF               6'b000011
690
`define OR1200_OR32_BF                6'b000100
691
`define OR1200_OR32_NOP               6'b000101
692
`define OR1200_OR32_MOVHI             6'b000110
693 92 rfajardo
`define OR1200_OR32_MACRC             6'b000110
694 66 rfajardo
`define OR1200_OR32_XSYNC             6'b001000
695
`define OR1200_OR32_RFE               6'b001001
696
/* */
697
`define OR1200_OR32_JR                6'b010001
698
`define OR1200_OR32_JALR              6'b010010
699
`define OR1200_OR32_MACI              6'b010011
700
/* */
701
`define OR1200_OR32_LWZ               6'b100001
702
`define OR1200_OR32_LBZ               6'b100011
703
`define OR1200_OR32_LBS               6'b100100
704
`define OR1200_OR32_LHZ               6'b100101
705
`define OR1200_OR32_LHS               6'b100110
706
`define OR1200_OR32_ADDI              6'b100111
707
`define OR1200_OR32_ADDIC             6'b101000
708
`define OR1200_OR32_ANDI              6'b101001
709
`define OR1200_OR32_ORI               6'b101010
710
`define OR1200_OR32_XORI              6'b101011
711
`define OR1200_OR32_MULI              6'b101100
712
`define OR1200_OR32_MFSPR             6'b101101
713
`define OR1200_OR32_SH_ROTI           6'b101110
714
`define OR1200_OR32_SFXXI             6'b101111
715
/* */
716
`define OR1200_OR32_MTSPR             6'b110000
717
`define OR1200_OR32_MACMSB            6'b110001
718
`define OR1200_OR32_FLOAT             6'b110010
719
/* */
720
`define OR1200_OR32_SW                6'b110101
721
`define OR1200_OR32_SB                6'b110110
722
`define OR1200_OR32_SH                6'b110111
723
`define OR1200_OR32_ALU               6'b111000
724
`define OR1200_OR32_SFXX              6'b111001
725 92 rfajardo
`define OR1200_OR32_CUST5             6'b111100
726 66 rfajardo
 
727
/////////////////////////////////////////////////////
728
//
729
// Exceptions
730
//
731
 
732
//
733
// Exception vectors per OR1K architecture:
734
// 0xPPPPP100 - reset
735
// 0xPPPPP200 - bus error
736
// ... etc
737
// where P represents exception prefix.
738
//
739
// Exception vectors can be customized as per
740
// the following formula:
741
// 0xPPPPPNVV - exception N
742
//
743
// P represents exception prefix
744
// N represents exception N
745
// VV represents length of the individual vector space,
746
//   usually it is 8 bits wide and starts with all bits zero
747
//
748
 
749
//
750
// PPPPP and VV parts
751
//
752
// Sum of these two defines needs to be 28
753
//
754
`define OR1200_EXCEPT_EPH0_P    20'h00000
755
`define OR1200_EXCEPT_EPH1_P    20'hF0000
756
`define OR1200_EXCEPT_V             8'h00
757
 
758
//
759
// N part width
760
//
761
`define OR1200_EXCEPT_WIDTH 4
762
 
763
//
764
// Definition of exception vectors
765
//
766
// To avoid implementation of a certain exception,
767
// simply comment out corresponding line
768
//
769
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
770
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
771
`define OR1200_EXCEPT_FLOAT             `OR1200_EXCEPT_WIDTH'hd
772
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
773
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
774
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
775
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
776
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
777
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
778
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
779
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
780
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
781
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
782
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
783
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
784
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
785
 
786
 
787
/////////////////////////////////////////////////////
788
//
789
// SPR groups
790
//
791
 
792
// Bits that define the group
793
`define OR1200_SPR_GROUP_BITS   15:11
794
 
795
// Width of the group bits
796
`define OR1200_SPR_GROUP_WIDTH  5
797
 
798
// Bits that define offset inside the group
799
`define OR1200_SPR_OFS_BITS 10:0
800
 
801
// List of groups
802
`define OR1200_SPR_GROUP_SYS    5'd00
803
`define OR1200_SPR_GROUP_DMMU   5'd01
804
`define OR1200_SPR_GROUP_IMMU   5'd02
805
`define OR1200_SPR_GROUP_DC     5'd03
806
`define OR1200_SPR_GROUP_IC     5'd04
807
`define OR1200_SPR_GROUP_MAC    5'd05
808
`define OR1200_SPR_GROUP_DU     5'd06
809
`define OR1200_SPR_GROUP_PM     5'd08
810
`define OR1200_SPR_GROUP_PIC    5'd09
811
`define OR1200_SPR_GROUP_TT     5'd10
812
`define OR1200_SPR_GROUP_FPU    5'd11
813
 
814
/////////////////////////////////////////////////////
815
//
816
// System group
817
//
818
 
819
//
820
// System registers
821
//
822
`define OR1200_SPR_CFGR         7'd0
823
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
824
`define OR1200_SPR_NPC          11'd16
825
`define OR1200_SPR_SR           11'd17
826
`define OR1200_SPR_PPC          11'd18
827
`define OR1200_SPR_FPCSR        11'd20
828
`define OR1200_SPR_EPCR         11'd32
829
`define OR1200_SPR_EEAR         11'd48
830
`define OR1200_SPR_ESR          11'd64
831
 
832
//
833
// SR bits
834
//
835
`define OR1200_SR_WIDTH 17
836
`define OR1200_SR_SM   0
837
`define OR1200_SR_TEE  1
838
`define OR1200_SR_IEE  2
839
`define OR1200_SR_DCE  3
840
`define OR1200_SR_ICE  4
841
`define OR1200_SR_DME  5
842
`define OR1200_SR_IME  6
843
`define OR1200_SR_LEE  7
844
`define OR1200_SR_CE   8
845
`define OR1200_SR_F    9
846 92 rfajardo
`define OR1200_SR_CY   10       // Optional
847
`define OR1200_SR_OV   11       // Optional
848
`define OR1200_SR_OVE  12       // Optional
849 66 rfajardo
`define OR1200_SR_DSX  13       // Unused
850
`define OR1200_SR_EPH  14
851
`define OR1200_SR_FO   15
852
`define OR1200_SR_TED  16
853
`define OR1200_SR_CID  31:28    // Unimplemented
854
 
855
//
856
// Bits that define offset inside the group
857
//
858
`define OR1200_SPROFS_BITS 10:0
859
 
860
//
861
// Default Exception Prefix
862
//
863
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
864
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
865
//
866
`define OR1200_SR_EPH_DEF       1'b0
867
 
868
 
869
//
870
// FPCSR bits
871
//
872
`define OR1200_FPCSR_WIDTH 12
873
`define OR1200_FPCSR_FPEE  0
874
`define OR1200_FPCSR_RM    2:1
875
`define OR1200_FPCSR_OVF   3
876
`define OR1200_FPCSR_UNF   4
877
`define OR1200_FPCSR_SNF   5
878
`define OR1200_FPCSR_QNF   6
879
`define OR1200_FPCSR_ZF    7
880
`define OR1200_FPCSR_IXF   8
881
`define OR1200_FPCSR_IVF   9
882
`define OR1200_FPCSR_INF   10
883
`define OR1200_FPCSR_DZF   11
884
`define OR1200_FPCSR_RES   31:12
885
 
886
/////////////////////////////////////////////////////
887
//
888
// Power Management (PM)
889
//
890
 
891
// Define it if you want PM implemented
892
//`define OR1200_PM_IMPLEMENTED
893
 
894
// Bit positions inside PMR (don't change)
895
`define OR1200_PM_PMR_SDF 3:0
896
`define OR1200_PM_PMR_DME 4
897
`define OR1200_PM_PMR_SME 5
898
`define OR1200_PM_PMR_DCGE 6
899
`define OR1200_PM_PMR_UNUSED 31:7
900
 
901
// PMR offset inside PM group of registers
902
`define OR1200_PM_OFS_PMR 11'b0
903
 
904
// PM group
905
`define OR1200_SPRGRP_PM 5'd8
906
 
907
// Define if PMR can be read/written at any address inside PM group
908
`define OR1200_PM_PARTIAL_DECODING
909
 
910
// Define if reading PMR is allowed
911
`define OR1200_PM_READREGS
912
 
913
// Define if unused PMR bits should be zero
914
`define OR1200_PM_UNUSED_ZERO
915
 
916
 
917
/////////////////////////////////////////////////////
918
//
919
// Debug Unit (DU)
920
//
921
 
922
// Define it if you want DU implemented
923
`define OR1200_DU_IMPLEMENTED
924
 
925
//
926
// Define if you want HW Breakpoints
927
// (if HW breakpoints are not implemented
928
// only default software trapping is
929
// possible with l.trap insn - this is
930
// however already enough for use
931
// with or32 gdb)
932
//
933
//`define OR1200_DU_HWBKPTS
934
 
935
// Number of DVR/DCR pairs if HW breakpoints enabled
936
//      Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
937
//      DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
938
`define OR1200_DU_DVRDCR_PAIRS 8
939
 
940
// Define if you want trace buffer
941
//      (for now only available for Xilinx Virtex FPGAs)
942
//`define OR1200_DU_TB_IMPLEMENTED
943
 
944
 
945
//
946
// Address offsets of DU registers inside DU group
947
//
948
// To not implement a register, doq not define its address
949
//
950
`ifdef OR1200_DU_HWBKPTS
951
`define OR1200_DU_DVR0          11'd0
952
`define OR1200_DU_DVR1          11'd1
953
`define OR1200_DU_DVR2          11'd2
954
`define OR1200_DU_DVR3          11'd3
955
`define OR1200_DU_DVR4          11'd4
956
`define OR1200_DU_DVR5          11'd5
957
`define OR1200_DU_DVR6          11'd6
958
`define OR1200_DU_DVR7          11'd7
959
`define OR1200_DU_DCR0          11'd8
960
`define OR1200_DU_DCR1          11'd9
961
`define OR1200_DU_DCR2          11'd10
962
`define OR1200_DU_DCR3          11'd11
963
`define OR1200_DU_DCR4          11'd12
964
`define OR1200_DU_DCR5          11'd13
965
`define OR1200_DU_DCR6          11'd14
966
`define OR1200_DU_DCR7          11'd15
967
`endif
968
`define OR1200_DU_DMR1          11'd16
969
`ifdef OR1200_DU_HWBKPTS
970
`define OR1200_DU_DMR2          11'd17
971
`define OR1200_DU_DWCR0         11'd18
972
`define OR1200_DU_DWCR1         11'd19
973
`endif
974
`define OR1200_DU_DSR           11'd20
975
`define OR1200_DU_DRR           11'd21
976
`ifdef OR1200_DU_TB_IMPLEMENTED
977
`define OR1200_DU_TBADR         11'h0ff
978
`define OR1200_DU_TBIA          11'h1??
979
`define OR1200_DU_TBIM          11'h2??
980
`define OR1200_DU_TBAR          11'h3??
981
`define OR1200_DU_TBTS          11'h4??
982
`endif
983
 
984
// Position of offset bits inside SPR address
985
`define OR1200_DUOFS_BITS       10:0
986
 
987
// DCR bits
988
`define OR1200_DU_DCR_DP        0
989
`define OR1200_DU_DCR_CC        3:1
990
`define OR1200_DU_DCR_SC        4
991
`define OR1200_DU_DCR_CT        7:5
992
 
993
// DMR1 bits
994
`define OR1200_DU_DMR1_CW0      1:0
995
`define OR1200_DU_DMR1_CW1      3:2
996
`define OR1200_DU_DMR1_CW2      5:4
997
`define OR1200_DU_DMR1_CW3      7:6
998
`define OR1200_DU_DMR1_CW4      9:8
999
`define OR1200_DU_DMR1_CW5      11:10
1000
`define OR1200_DU_DMR1_CW6      13:12
1001
`define OR1200_DU_DMR1_CW7      15:14
1002
`define OR1200_DU_DMR1_CW8      17:16
1003
`define OR1200_DU_DMR1_CW9      19:18
1004
`define OR1200_DU_DMR1_CW10     21:20
1005
`define OR1200_DU_DMR1_ST       22
1006
`define OR1200_DU_DMR1_BT       23
1007
`define OR1200_DU_DMR1_DXFW     24
1008
`define OR1200_DU_DMR1_ETE      25
1009
 
1010
// DMR2 bits
1011
`define OR1200_DU_DMR2_WCE0     0
1012
`define OR1200_DU_DMR2_WCE1     1
1013
`define OR1200_DU_DMR2_AWTC     12:2
1014
`define OR1200_DU_DMR2_WGB      23:13
1015
 
1016
// DWCR bits
1017
`define OR1200_DU_DWCR_COUNT    15:0
1018
`define OR1200_DU_DWCR_MATCH    31:16
1019
 
1020
// DSR bits
1021
`define OR1200_DU_DSR_WIDTH     14
1022
`define OR1200_DU_DSR_RSTE      0
1023
`define OR1200_DU_DSR_BUSEE     1
1024
`define OR1200_DU_DSR_DPFE      2
1025
`define OR1200_DU_DSR_IPFE      3
1026
`define OR1200_DU_DSR_TTE       4
1027
`define OR1200_DU_DSR_AE        5
1028
`define OR1200_DU_DSR_IIE       6
1029
`define OR1200_DU_DSR_IE        7
1030
`define OR1200_DU_DSR_DME       8
1031
`define OR1200_DU_DSR_IME       9
1032
`define OR1200_DU_DSR_RE        10
1033
`define OR1200_DU_DSR_SCE       11
1034
`define OR1200_DU_DSR_FPE       12
1035
`define OR1200_DU_DSR_TE        13
1036
 
1037
// DRR bits
1038
`define OR1200_DU_DRR_RSTE      0
1039
`define OR1200_DU_DRR_BUSEE     1
1040
`define OR1200_DU_DRR_DPFE      2
1041
`define OR1200_DU_DRR_IPFE      3
1042
`define OR1200_DU_DRR_TTE       4
1043
`define OR1200_DU_DRR_AE        5
1044
`define OR1200_DU_DRR_IIE       6
1045
`define OR1200_DU_DRR_IE        7
1046
`define OR1200_DU_DRR_DME       8
1047
`define OR1200_DU_DRR_IME       9
1048
`define OR1200_DU_DRR_RE        10
1049
`define OR1200_DU_DRR_SCE       11
1050
`define OR1200_DU_DRR_FPE       12
1051
`define OR1200_DU_DRR_TE        13
1052
 
1053
// Define if reading DU regs is allowed
1054
`define OR1200_DU_READREGS
1055
 
1056
// Define if unused DU registers bits should be zero
1057
`define OR1200_DU_UNUSED_ZERO
1058
 
1059
// Define if IF/LSU status is not needed by devel i/f
1060
`define OR1200_DU_STATUS_UNIMPLEMENTED
1061
 
1062
/////////////////////////////////////////////////////
1063
//
1064
// Programmable Interrupt Controller (PIC)
1065
//
1066
 
1067
// Define it if you want PIC implemented
1068
`define OR1200_PIC_IMPLEMENTED
1069
 
1070
// Define number of interrupt inputs (2-31)
1071
`define OR1200_PIC_INTS 20
1072
 
1073
// Address offsets of PIC registers inside PIC group
1074
`define OR1200_PIC_OFS_PICMR 2'd0
1075
`define OR1200_PIC_OFS_PICSR 2'd2
1076
 
1077
// Position of offset bits inside SPR address
1078
`define OR1200_PICOFS_BITS 1:0
1079
 
1080
// Define if you want these PIC registers to be implemented
1081
`define OR1200_PIC_PICMR
1082
`define OR1200_PIC_PICSR
1083
 
1084
// Define if reading PIC registers is allowed
1085
`define OR1200_PIC_READREGS
1086
 
1087
// Define if unused PIC register bits should be zero
1088
`define OR1200_PIC_UNUSED_ZERO
1089
 
1090
 
1091
/////////////////////////////////////////////////////
1092
//
1093
// Tick Timer (TT)
1094
//
1095
 
1096
// Define it if you want TT implemented
1097
`define OR1200_TT_IMPLEMENTED
1098
 
1099
// Address offsets of TT registers inside TT group
1100
`define OR1200_TT_OFS_TTMR 1'd0
1101
`define OR1200_TT_OFS_TTCR 1'd1
1102
 
1103
// Position of offset bits inside SPR group
1104
`define OR1200_TTOFS_BITS 0
1105
 
1106
// Define if you want these TT registers to be implemented
1107
`define OR1200_TT_TTMR
1108
`define OR1200_TT_TTCR
1109
 
1110
// TTMR bits
1111
`define OR1200_TT_TTMR_TP 27:0
1112
`define OR1200_TT_TTMR_IP 28
1113
`define OR1200_TT_TTMR_IE 29
1114
`define OR1200_TT_TTMR_M 31:30
1115
 
1116
// Define if reading TT registers is allowed
1117
`define OR1200_TT_READREGS
1118
 
1119
 
1120
//////////////////////////////////////////////
1121
//
1122
// MAC
1123
//
1124
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1125
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1126
 
1127
//
1128
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1129
//
1130
// According to architecture manual there is no shift, so default value is 0.
1131
// However the implementation has deviated in this from the arch manual and had
1132
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
1133
// (if using libmad fixed point library). Shifts are no longer default setup, 
1134
// but if you need to remain backward compatible, define your shift bits, which
1135
// were normally
1136
// dest_GPR = {MACHI,MACLO}[59:28]
1137
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1138
 
1139
 
1140
//////////////////////////////////////////////
1141
//
1142
// Data MMU (DMMU)
1143
//
1144
 
1145
//
1146
// Address that selects between TLB TR and MR
1147
//
1148
`define OR1200_DTLB_TM_ADDR     7
1149
 
1150
//
1151
// DTLBMR fields
1152
//
1153
`define OR1200_DTLBMR_V_BITS    0
1154
`define OR1200_DTLBMR_CID_BITS  4:1
1155
`define OR1200_DTLBMR_RES_BITS  11:5
1156
`define OR1200_DTLBMR_VPN_BITS  31:13
1157
 
1158
//
1159
// DTLBTR fields
1160
//
1161
`define OR1200_DTLBTR_CC_BITS   0
1162
`define OR1200_DTLBTR_CI_BITS   1
1163
`define OR1200_DTLBTR_WBC_BITS  2
1164
`define OR1200_DTLBTR_WOM_BITS  3
1165
`define OR1200_DTLBTR_A_BITS    4
1166
`define OR1200_DTLBTR_D_BITS    5
1167
`define OR1200_DTLBTR_URE_BITS  6
1168
`define OR1200_DTLBTR_UWE_BITS  7
1169
`define OR1200_DTLBTR_SRE_BITS  8
1170
`define OR1200_DTLBTR_SWE_BITS  9
1171
`define OR1200_DTLBTR_RES_BITS  11:10
1172
`define OR1200_DTLBTR_PPN_BITS  31:13
1173
 
1174
//
1175
// DTLB configuration
1176
//
1177
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1178
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1179
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1180
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1181
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1182
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1183
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1184
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1185
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1186
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1187
 
1188
//
1189
// Cache inhibit while DMMU is not enabled/implemented
1190
//
1191
// cache inhibited 0GB-4GB              1'b1
1192
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1193
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1194
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1195
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1196
// cached 0GB-4GB                       1'b0
1197
//
1198
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1199
 
1200
 
1201
//////////////////////////////////////////////
1202
//
1203
// Insn MMU (IMMU)
1204
//
1205
 
1206
//
1207
// Address that selects between TLB TR and MR
1208
//
1209
`define OR1200_ITLB_TM_ADDR     7
1210
 
1211
//
1212
// ITLBMR fields
1213
//
1214
`define OR1200_ITLBMR_V_BITS    0
1215
`define OR1200_ITLBMR_CID_BITS  4:1
1216
`define OR1200_ITLBMR_RES_BITS  11:5
1217
`define OR1200_ITLBMR_VPN_BITS  31:13
1218
 
1219
//
1220
// ITLBTR fields
1221
//
1222
`define OR1200_ITLBTR_CC_BITS   0
1223
`define OR1200_ITLBTR_CI_BITS   1
1224
`define OR1200_ITLBTR_WBC_BITS  2
1225
`define OR1200_ITLBTR_WOM_BITS  3
1226
`define OR1200_ITLBTR_A_BITS    4
1227
`define OR1200_ITLBTR_D_BITS    5
1228
`define OR1200_ITLBTR_SXE_BITS  6
1229
`define OR1200_ITLBTR_UXE_BITS  7
1230
`define OR1200_ITLBTR_RES_BITS  11:8
1231
`define OR1200_ITLBTR_PPN_BITS  31:13
1232
 
1233
//
1234
// ITLB configuration
1235
//
1236
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1237
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1238
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1239
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1240
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1241
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1242
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1243
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1244
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1245
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1246
 
1247
//
1248
// Cache inhibit while IMMU is not enabled/implemented
1249
// Note: all combinations that use icpu_adr_i cause async loop
1250
//
1251
// cache inhibited 0GB-4GB              1'b1
1252
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1253
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1254
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1255
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1256
// cached 0GB-4GB                       1'b0
1257
//
1258
`define OR1200_IMMU_CI                  1'b0
1259
 
1260
 
1261
/////////////////////////////////////////////////
1262
//
1263
// Insn cache (IC)
1264
//
1265
 
1266
// 4 for 16 byte line, 5 for 32 byte lines.
1267
`ifdef OR1200_IC_1W_32KB
1268
 `define OR1200_ICLS            5
1269
`else
1270
 `define OR1200_ICLS            4
1271
`endif
1272
 
1273
//
1274
// IC configurations
1275
//
1276
`ifdef OR1200_IC_1W_512B
1277
`define OR1200_ICSIZE                   9                       // 512
1278
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 7
1279
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 8
1280
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 9
1281
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS // 5
1282
`define OR1200_ICTAG_W                  24
1283
`endif
1284
`ifdef OR1200_IC_1W_4KB
1285
`define OR1200_ICSIZE                   12                      // 4096
1286
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1287
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1288
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1289
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1290
`define OR1200_ICTAG_W                  21
1291
`endif
1292
`ifdef OR1200_IC_1W_8KB
1293
`define OR1200_ICSIZE                   13                      // 8192
1294
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1295
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1296
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1297
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1298
`define OR1200_ICTAG_W                  20
1299
`endif
1300
`ifdef OR1200_IC_1W_16KB
1301
`define OR1200_ICSIZE                   14                      // 16384
1302
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 12
1303
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 13
1304
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 14
1305
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 10
1306
`define OR1200_ICTAG_W                  19
1307
`endif
1308
`ifdef OR1200_IC_1W_32KB
1309
`define OR1200_ICSIZE                   15                      // 32768
1310
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 13
1311
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 14
1312
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 14
1313
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 10
1314
`define OR1200_ICTAG_W                  18
1315
`endif
1316
 
1317
 
1318
/////////////////////////////////////////////////
1319
//
1320
// Data cache (DC)
1321
//
1322
 
1323
// 4 for 16 bytes, 5 for 32 bytes
1324
`ifdef OR1200_DC_1W_32KB
1325
 `define OR1200_DCLS            5
1326
`else
1327
 `define OR1200_DCLS            4
1328
`endif
1329
 
1330
// Define to enable default behavior of cache as write through
1331
// Turning this off enabled write back statergy
1332
//
1333
`define OR1200_DC_WRITETHROUGH
1334
 
1335
// Define to enable stores from the stack not doing writethrough.
1336
// EXPERIMENTAL
1337
//`define OR1200_DC_NOSTACKWRITETHROUGH
1338
 
1339
// Data cache SPR definitions
1340
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
1341
// Data cache group SPR addresses
1342
`define OR1200_SPRGRP_DC_DCCR           3'd0 // Not implemented
1343
`define OR1200_SPRGRP_DC_DCBPR          3'd1 // Not implemented
1344
`define OR1200_SPRGRP_DC_DCBFR          3'd2
1345
`define OR1200_SPRGRP_DC_DCBIR          3'd3
1346
`define OR1200_SPRGRP_DC_DCBWR          3'd4 // Not implemented
1347
`define OR1200_SPRGRP_DC_DCBLR          3'd5 // Not implemented
1348
 
1349
//
1350
// DC configurations
1351
//
1352
`ifdef OR1200_DC_1W_4KB
1353
`define OR1200_DCSIZE                   12                      // 4096
1354
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1355
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1356
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1357
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1358
`define OR1200_DCTAG_W                  21
1359
`endif
1360
`ifdef OR1200_DC_1W_8KB
1361
`define OR1200_DCSIZE                   13                      // 8192
1362
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1363
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1364
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1365
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1366
`define OR1200_DCTAG_W                  20
1367
`endif
1368
`ifdef OR1200_DC_1W_16KB
1369
`define OR1200_DCSIZE                   14                      // 16384
1370
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 12
1371
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 13
1372
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 14
1373
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 10
1374
`define OR1200_DCTAG_W                  19
1375
`endif
1376
`ifdef OR1200_DC_1W_32KB
1377
`define OR1200_DCSIZE                   15                      // 32768
1378
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 13
1379
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 14
1380
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 15
1381
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 10
1382
`define OR1200_DCTAG_W                  18
1383
`endif
1384
 
1385
 
1386
/////////////////////////////////////////////////
1387
//
1388
// Store buffer (SB)
1389
//
1390
 
1391
//
1392
// Store buffer
1393
//
1394
// It will improve performance by "caching" CPU stores
1395
// using store buffer. This is most important for function
1396
// prologues because DC can only work in write though mode
1397
// and all stores would have to complete external WB writes
1398
// to memory.
1399
// Store buffer is between DC and data BIU.
1400
// All stores will be stored into store buffer and immediately
1401
// completed by the CPU, even though actual external writes
1402
// will be performed later. As a consequence store buffer masks
1403
// all data bus errors related to stores (data bus errors
1404
// related to loads are delivered normally).
1405
// All pending CPU loads will wait until store buffer is empty to
1406
// ensure strict memory model. Right now this is necessary because
1407
// we don't make destinction between cached and cache inhibited
1408
// address space, so we simply empty store buffer until loads
1409
// can begin.
1410
//
1411
// It makes design a bit bigger, depending what is the number of
1412
// entries in SB FIFO. Number of entries can be changed further
1413
// down.
1414
//
1415
//`define OR1200_SB_IMPLEMENTED
1416
 
1417
//
1418
// Number of store buffer entries
1419
//
1420
// Verified number of entries are 4 and 8 entries
1421
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1422
// always match 2**OR1200_SB_LOG.
1423
// To disable store buffer, undefine
1424
// OR1200_SB_IMPLEMENTED.
1425
//
1426
`define OR1200_SB_LOG           2       // 2 or 3
1427
`define OR1200_SB_ENTRIES       4       // 4 or 8
1428
 
1429
 
1430
/////////////////////////////////////////////////
1431
//
1432
// Quick Embedded Memory (QMEM)
1433
//
1434
 
1435
//
1436
// Quick Embedded Memory
1437
//
1438
// Instantiation of dedicated insn/data memory (RAM or ROM).
1439
// Insn fetch has effective throughput 1insn / clock cycle.
1440
// Data load takes two clock cycles / access, data store
1441
// takes 1 clock cycle / access (if there is no insn fetch)).
1442
// Memory instantiation is shared between insn and data,
1443
// meaning if insn fetch are performed, data load/store
1444
// performance will be lower.
1445
//
1446
// Main reason for QMEM is to put some time critical functions
1447
// into this memory and to have predictable and fast access
1448
// to these functions. (soft fpu, context switch, exception
1449
// handlers, stack, etc)
1450
//
1451
// It makes design a bit bigger and slower. QMEM sits behind
1452
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1453
// used with QMEM and QMEM is seen by the CPU just like any other
1454
// memory in the system). IC/DC are sitting behind QMEM so the
1455
// whole design timing might be worse with QMEM implemented.
1456
//
1457
//`define OR1200_QMEM_IMPLEMENTED
1458
 
1459
//
1460
// Base address and mask of QMEM
1461
//
1462
// Base address defines first address of QMEM. Mask defines
1463
// QMEM range in address space. Actual size of QMEM is however
1464
// determined with instantiated RAM/ROM. However bigger
1465
// mask will reserve more address space for QMEM, but also
1466
// make design faster, while more tight mask will take
1467
// less address space but also make design slower. If
1468
// instantiated RAM/ROM is smaller than space reserved with
1469
// the mask, instatiated RAM/ROM will also be shadowed
1470
// at higher addresses in reserved space.
1471
//
1472
`define OR1200_QMEM_IADDR       32'h0080_0000
1473
`define OR1200_QMEM_IMASK       32'hfff0_0000 // Max QMEM size 1MB
1474
`define OR1200_QMEM_DADDR       32'h0080_0000
1475
`define OR1200_QMEM_DMASK       32'hfff0_0000 // Max QMEM size 1MB
1476
 
1477
//
1478
// QMEM interface byte-select capability
1479
//
1480
// To enable qmem_sel* ports, define this macro.
1481
//
1482
//`define OR1200_QMEM_BSEL
1483
 
1484
//
1485
// QMEM interface acknowledge
1486
//
1487
// To enable qmem_ack port, define this macro.
1488
//
1489
//`define OR1200_QMEM_ACK
1490
 
1491
/////////////////////////////////////////////////////
1492
//
1493
// VR, UPR and Configuration Registers
1494
//
1495
//
1496
// VR, UPR and configuration registers are optional. If 
1497
// implemented, operating system can automatically figure
1498
// out how to use the processor because it knows 
1499
// what units are available in the processor and how they
1500
// are configured.
1501
//
1502
// This section must be last in or1200_defines.v file so
1503
// that all units are already configured and thus
1504
// configuration registers are properly set.
1505
// 
1506
 
1507
// Define if you want configuration registers implemented
1508
`define OR1200_CFGR_IMPLEMENTED
1509
 
1510
// Define if you want full address decode inside SYS group
1511
`define OR1200_SYS_FULL_DECODE
1512
 
1513
// Offsets of VR, UPR and CFGR registers
1514
`define OR1200_SPRGRP_SYS_VR            4'h0
1515
`define OR1200_SPRGRP_SYS_UPR           4'h1
1516
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1517
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1518
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1519
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1520
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1521
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1522
 
1523
// VR fields
1524
`define OR1200_VR_REV_BITS              5:0
1525
`define OR1200_VR_RES1_BITS             15:6
1526
`define OR1200_VR_CFG_BITS              23:16
1527
`define OR1200_VR_VER_BITS              31:24
1528
 
1529
// VR values
1530
`define OR1200_VR_REV                   6'h08
1531
`define OR1200_VR_RES1                  10'h000
1532
`define OR1200_VR_CFG                   8'h00
1533
`define OR1200_VR_VER                   8'h12
1534
 
1535
// UPR fields
1536
`define OR1200_UPR_UP_BITS              0
1537
`define OR1200_UPR_DCP_BITS             1
1538
`define OR1200_UPR_ICP_BITS             2
1539
`define OR1200_UPR_DMP_BITS             3
1540
`define OR1200_UPR_IMP_BITS             4
1541
`define OR1200_UPR_MP_BITS              5
1542
`define OR1200_UPR_DUP_BITS             6
1543
`define OR1200_UPR_PCUP_BITS            7
1544
`define OR1200_UPR_PMP_BITS             8
1545
`define OR1200_UPR_PICP_BITS            9
1546
`define OR1200_UPR_TTP_BITS             10
1547
`define OR1200_UPR_FPP_BITS             11
1548
`define OR1200_UPR_RES1_BITS            23:12
1549
`define OR1200_UPR_CUP_BITS             31:24
1550
 
1551
// UPR values
1552
`define OR1200_UPR_UP                   1'b1
1553
`ifdef OR1200_NO_DC
1554
`define OR1200_UPR_DCP                  1'b0
1555
`else
1556
`define OR1200_UPR_DCP                  1'b1
1557
`endif
1558
`ifdef OR1200_NO_IC
1559
`define OR1200_UPR_ICP                  1'b0
1560
`else
1561
`define OR1200_UPR_ICP                  1'b1
1562
`endif
1563
`ifdef OR1200_NO_DMMU
1564
`define OR1200_UPR_DMP                  1'b0
1565
`else
1566
`define OR1200_UPR_DMP                  1'b1
1567
`endif
1568
`ifdef OR1200_NO_IMMU
1569
`define OR1200_UPR_IMP                  1'b0
1570
`else
1571
`define OR1200_UPR_IMP                  1'b1
1572
`endif
1573
`ifdef OR1200_MAC_IMPLEMENTED
1574
`define OR1200_UPR_MP                   1'b1
1575
`else
1576
`define OR1200_UPR_MP                   1'b0
1577
`endif
1578
`ifdef OR1200_DU_IMPLEMENTED
1579
`define OR1200_UPR_DUP                  1'b1
1580
`else
1581
`define OR1200_UPR_DUP                  1'b0
1582
`endif
1583
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1584
`ifdef OR1200_PM_IMPLEMENTED
1585
`define OR1200_UPR_PMP                  1'b1
1586
`else
1587
`define OR1200_UPR_PMP                  1'b0
1588
`endif
1589
`ifdef OR1200_PIC_IMPLEMENTED
1590
`define OR1200_UPR_PICP                 1'b1
1591
`else
1592
`define OR1200_UPR_PICP                 1'b0
1593
`endif
1594
`ifdef OR1200_TT_IMPLEMENTED
1595
`define OR1200_UPR_TTP                  1'b1
1596
`else
1597
`define OR1200_UPR_TTP                  1'b0
1598
`endif
1599
`ifdef OR1200_FPU_IMPLEMENTED
1600
`define OR1200_UPR_FPP                  1'b1
1601
`else
1602
`define OR1200_UPR_FPP                  1'b0
1603
`endif
1604
`define OR1200_UPR_RES1                 12'h000
1605
`define OR1200_UPR_CUP                  8'h00
1606
 
1607
// CPUCFGR fields
1608
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1609
`define OR1200_CPUCFGR_HGF_BITS     4
1610
`define OR1200_CPUCFGR_OB32S_BITS       5
1611
`define OR1200_CPUCFGR_OB64S_BITS       6
1612
`define OR1200_CPUCFGR_OF32S_BITS       7
1613
`define OR1200_CPUCFGR_OF64S_BITS       8
1614
`define OR1200_CPUCFGR_OV64S_BITS       9
1615
`define OR1200_CPUCFGR_RES1_BITS        31:10
1616
 
1617
// CPUCFGR values
1618
`define OR1200_CPUCFGR_NSGF                 4'h0
1619
`ifdef OR1200_RFRAM_16REG
1620
    `define OR1200_CPUCFGR_HGF                  1'b1
1621
`else
1622
    `define OR1200_CPUCFGR_HGF                  1'b0
1623
`endif
1624
`define OR1200_CPUCFGR_OB32S            1'b1
1625
`define OR1200_CPUCFGR_OB64S            1'b0
1626
`ifdef OR1200_FPU_IMPLEMENTED
1627
 `define OR1200_CPUCFGR_OF32S           1'b1
1628
`else
1629
 `define OR1200_CPUCFGR_OF32S           1'b0
1630
`endif
1631
 
1632
`define OR1200_CPUCFGR_OF64S            1'b0
1633
`define OR1200_CPUCFGR_OV64S            1'b0
1634
`define OR1200_CPUCFGR_RES1             22'h000000
1635
 
1636
// DMMUCFGR fields
1637
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1638
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1639
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1640
`define OR1200_DMMUCFGR_CRI_BITS        8
1641
`define OR1200_DMMUCFGR_PRI_BITS        9
1642
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1643
`define OR1200_DMMUCFGR_HTR_BITS        11
1644
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1645
 
1646
// DMMUCFGR values
1647
`ifdef OR1200_NO_DMMU
1648
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1649
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1650
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1651
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1652
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1653
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1654
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1655
`define OR1200_DMMUCFGR_RES1            20'h00000
1656
`else
1657
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1658
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1659
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1660
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1661
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1662 92 rfajardo
`define OR1200_DMMUCFGR_TEIRI           1'b0    // TLB entry inv reg NOT impl.
1663 66 rfajardo
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1664
`define OR1200_DMMUCFGR_RES1            20'h00000
1665
`endif
1666
 
1667
// IMMUCFGR fields
1668
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1669
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1670
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1671
`define OR1200_IMMUCFGR_CRI_BITS        8
1672
`define OR1200_IMMUCFGR_PRI_BITS        9
1673
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1674
`define OR1200_IMMUCFGR_HTR_BITS        11
1675
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1676
 
1677
// IMMUCFGR values
1678
`ifdef OR1200_NO_IMMU
1679
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1680
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1681
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1682
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1683
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1684
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1685
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1686
`define OR1200_IMMUCFGR_RES1            20'h00000
1687
`else
1688
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1689
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1690
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1691
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1692
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1693 92 rfajardo
`define OR1200_IMMUCFGR_TEIRI           1'b0    // TLB entry inv reg NOT impl
1694 66 rfajardo
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1695
`define OR1200_IMMUCFGR_RES1            20'h00000
1696
`endif
1697
 
1698
// DCCFGR fields
1699
`define OR1200_DCCFGR_NCW_BITS          2:0
1700
`define OR1200_DCCFGR_NCS_BITS          6:3
1701
`define OR1200_DCCFGR_CBS_BITS          7
1702
`define OR1200_DCCFGR_CWS_BITS          8
1703
`define OR1200_DCCFGR_CCRI_BITS         9
1704
`define OR1200_DCCFGR_CBIRI_BITS        10
1705
`define OR1200_DCCFGR_CBPRI_BITS        11
1706
`define OR1200_DCCFGR_CBLRI_BITS        12
1707
`define OR1200_DCCFGR_CBFRI_BITS        13
1708
`define OR1200_DCCFGR_CBWBRI_BITS       14
1709
`define OR1200_DCCFGR_RES1_BITS 31:15
1710
 
1711
// DCCFGR values
1712
`ifdef OR1200_NO_DC
1713
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1714
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1715
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1716
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1717
`define OR1200_DCCFGR_CCRI              1'b0    // Irrelevant
1718
`define OR1200_DCCFGR_CBIRI             1'b0    // Irrelevant
1719
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1720
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1721
`define OR1200_DCCFGR_CBFRI             1'b0    // Irrelevant
1722
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1723
`define OR1200_DCCFGR_RES1              17'h00000
1724
`else
1725
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1726
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1727
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
1728
`ifdef OR1200_DC_WRITETHROUGH
1729
 `define OR1200_DCCFGR_CWS              1'b0    // Write-through strategy
1730
`else
1731
 `define OR1200_DCCFGR_CWS              1'b1    // Write-back strategy
1732
`endif
1733
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1734
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1735
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1736
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1737
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1738
`ifdef OR1200_DC_WRITETHROUGH
1739
 `define OR1200_DCCFGR_CBWBRI           1'b0    // Cache block WB reg not impl.
1740
`else
1741
 `define OR1200_DCCFGR_CBWBRI           1'b1    // Cache block WB reg impl.
1742
`endif
1743
`define OR1200_DCCFGR_RES1              17'h00000
1744
`endif
1745
 
1746
// ICCFGR fields
1747
`define OR1200_ICCFGR_NCW_BITS          2:0
1748
`define OR1200_ICCFGR_NCS_BITS          6:3
1749
`define OR1200_ICCFGR_CBS_BITS          7
1750
`define OR1200_ICCFGR_CWS_BITS          8
1751
`define OR1200_ICCFGR_CCRI_BITS         9
1752
`define OR1200_ICCFGR_CBIRI_BITS        10
1753
`define OR1200_ICCFGR_CBPRI_BITS        11
1754
`define OR1200_ICCFGR_CBLRI_BITS        12
1755
`define OR1200_ICCFGR_CBFRI_BITS        13
1756
`define OR1200_ICCFGR_CBWBRI_BITS       14
1757
`define OR1200_ICCFGR_RES1_BITS 31:15
1758
 
1759
// ICCFGR values
1760
`ifdef OR1200_NO_IC
1761
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1762
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1763
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1764
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1765
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1766
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1767
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1768
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1769
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1770
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1771
`define OR1200_ICCFGR_RES1              17'h00000
1772
`else
1773
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1774
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1775
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1  // 16 byte cache block
1776
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1777
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1778
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1779
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1780
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1781
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1782
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1783
`define OR1200_ICCFGR_RES1              17'h00000
1784
`endif
1785
 
1786
// DCFGR fields
1787
`define OR1200_DCFGR_NDP_BITS           3:0
1788
`define OR1200_DCFGR_WPCI_BITS          4
1789
`define OR1200_DCFGR_RES1_BITS          31:5
1790
 
1791
// DCFGR values
1792
`ifdef OR1200_DU_HWBKPTS
1793
`define OR1200_DCFGR_NDP                4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1794
`ifdef OR1200_DU_DWCR0
1795
`define OR1200_DCFGR_WPCI               1'b1
1796
`else
1797
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1798
`endif
1799
`else
1800
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
1801
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1802
`endif
1803
`define OR1200_DCFGR_RES1               27'd0
1804
 
1805
///////////////////////////////////////////////////////////////////////////////
1806
// Boot Address Selection                                                    //
1807
//                                                                           //
1808
// Allows a definable boot address, potentially different to the usual reset //
1809
// vector to allow for power-on code to be run, if desired.                  //
1810
//                                                                           //
1811
// OR1200_BOOT_ADR should be the 32-bit address of the boot location         //
1812
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2)              //
1813
//                                                                           //
1814
// For default reset behavior uncomment the settings under the "Boot 0x100"  //
1815
// comment below.                                                            //
1816
//                                                                           //
1817
///////////////////////////////////////////////////////////////////////////////
1818
// Boot from 0xf0000100
1819
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
1820
//`define OR1200_BOOT_ADR 32'hf0000100
1821
// Boot from 0x100
1822
 `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
1823
 `define OR1200_BOOT_ADR 32'h00000100

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.