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[/] [minsoc/] [trunk/] [backend/] [spartan3e_starter_kit_eth/] [minsoc_bench_defines.v] - Blame information for rev 69

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Line No. Rev Author Line
1 69 rfajardo
 
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`timescale 1ns/100ps
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//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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`define GENERIC_FPGA
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`define MEMORY_MODEL        //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
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`define NO_CLOCK_DIVISION   //if commented out, generic clock division is implemented (odd divisors are rounded down)
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//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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`define FREQ_NUM_FOR_NS 1000000000
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`define FREQ 10000000
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`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
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`define ETH_PHY_FREQ  25000000
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`define ETH_PHY_PERIOD  (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ)    //40ns
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`define UART_BAUDRATE 19200
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`define VPI_DEBUG
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//`define VCD_OUTPUT
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//`define START_UP                                              //pass firmware over spi to or1k_startup
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`define INITIALIZE_MEMORY_MODEL                 //instantaneously initialize memory model with firmware
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                                                                                //only use with the memory model. 
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                                        //If you use the original memory (`define MEMORY_MODEL 
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                                        //commented out), comment this too.

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