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1 69 rfajardo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's definitions                                        ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://opencores.org/project,or1k                           ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Defines for the OR1200 core                                 ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add parameters that are missing                          ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// $Log: or1200_defines.v,v $
45
// Revision 2.0  2010/06/30 11:00:00  ORSoC
46
// Minor update: 
47
// Defines added, bugs fixed. 
48
 
49
//
50
// Dump VCD
51
//
52
//`define OR1200_VCD_DUMP
53
 
54
//
55
// Generate debug messages during simulation
56
//
57
//`define OR1200_VERBOSE
58
 
59
//  `define OR1200_ASIC
60
////////////////////////////////////////////////////////
61
//
62
// Typical configuration for an ASIC
63
//
64
`ifdef OR1200_ASIC
65
 
66
//
67
// Target ASIC memories
68
//
69
//`define OR1200_ARTISAN_SSP
70
//`define OR1200_ARTISAN_SDP
71
//`define OR1200_ARTISAN_STP
72
`define OR1200_VIRTUALSILICON_SSP
73
//`define OR1200_VIRTUALSILICON_STP_T1
74
//`define OR1200_VIRTUALSILICON_STP_T2
75
 
76
//
77
// Do not implement Data cache
78
//
79
//`define OR1200_NO_DC
80
 
81
//
82
// Do not implement Insn cache
83
//
84
//`define OR1200_NO_IC
85
 
86
//
87
// Do not implement Data MMU
88
//
89
//`define OR1200_NO_DMMU
90
 
91
//
92
// Do not implement Insn MMU
93
//
94
//`define OR1200_NO_IMMU
95
 
96
//
97
// Select between ASIC optimized and generic multiplier
98
//
99
//`define OR1200_ASIC_MULTP2_32X32
100
`define OR1200_GENERIC_MULTP2_32X32
101
 
102
//
103
// Size/type of insn/data cache if implemented
104
//
105
// `define OR1200_IC_1W_512B
106
// `define OR1200_IC_1W_4KB
107
`define OR1200_IC_1W_8KB
108
// `define OR1200_DC_1W_4KB
109
`define OR1200_DC_1W_8KB
110
 
111
`else
112
 
113
 
114
/////////////////////////////////////////////////////////
115
//
116
// Typical configuration for an FPGA
117
//
118
 
119
//
120
// Target FPGA memories
121
//
122
//`define OR1200_ALTERA_LPM
123
//`define OR1200_XILINX_RAMB16
124
//`define OR1200_XILINX_RAMB4
125
//`define OR1200_XILINX_RAM32X1D
126
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
127
// Generic models should infer RAM blocks at synthesis time (not only effects 
128
// single port ram.)
129
`define OR1200_GENERIC
130
 
131
//
132
// Do not implement Data cache
133
//
134
`define OR1200_NO_DC
135
 
136
//
137
// Do not implement Insn cache
138
//
139
`define OR1200_NO_IC
140
 
141
//
142
// Do not implement Data MMU
143
//
144
`define OR1200_NO_DMMU
145
 
146
//
147
// Do not implement Insn MMU
148
//
149
`define OR1200_NO_IMMU
150
 
151
//
152
// Select between ASIC and generic multiplier
153
//
154
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
155
//
156
//`define OR1200_ASIC_MULTP2_32X32
157
`define OR1200_GENERIC_MULTP2_32X32
158
 
159
//
160
// Size/type of insn/data cache if implemented
161
// (consider available FPGA memory resources)
162
//
163
//`define OR1200_IC_1W_512B
164
//`define OR1200_IC_1W_4KB
165
`define OR1200_IC_1W_8KB
166
//`define OR1200_IC_1W_16KB
167
//`define OR1200_IC_1W_32KB
168
//`define OR1200_DC_1W_4KB
169
`define OR1200_DC_1W_8KB
170
//`define OR1200_DC_1W_16KB
171
//`define OR1200_DC_1W_32KB
172
 
173
`endif
174
 
175
 
176
//////////////////////////////////////////////////////////
177
//
178
// Do not change below unless you know what you are doing
179
//
180
 
181
//
182
// Reset active low
183
//
184
//`define OR1200_RST_ACT_LOW
185
 
186
//
187
// Enable RAM BIST
188
//
189
// At the moment this only works for Virtual Silicon
190
// single port RAMs. For other RAMs it has not effect.
191
// Special wrapper for VS RAMs needs to be provided
192
// with scan flops to facilitate bist scan.
193
//
194
//`define OR1200_BIST
195
 
196
//
197
// Register OR1200 WISHBONE outputs
198
// (must be defined/enabled)
199
//
200
`define OR1200_REGISTERED_OUTPUTS
201
 
202
//
203
// Register OR1200 WISHBONE inputs
204
//
205
// (must be undefined/disabled)
206
//
207
//`define OR1200_REGISTERED_INPUTS
208
 
209
//
210
// Disable bursts if they are not supported by the
211
// memory subsystem (only affect cache line fill)
212
//
213
//`define OR1200_NO_BURSTS
214
//
215
 
216
//
217
// WISHBONE retry counter range
218
//
219
// 2^value range for retry counter. Retry counter
220
// is activated whenever *wb_rty_i is asserted and
221
// until retry counter expires, corresponding
222
// WISHBONE interface is deactivated.
223
//
224
// To disable retry counters and *wb_rty_i all together,
225
// undefine this macro.
226
//
227
//`define OR1200_WB_RETRY 7
228
 
229
//
230
// WISHBONE Consecutive Address Burst
231
//
232
// This was used prior to WISHBONE B3 specification
233
// to identify bursts. It is no longer needed but
234
// remains enabled for compatibility with old designs.
235
//
236
// To remove *wb_cab_o ports undefine this macro.
237
//
238
//`define OR1200_WB_CAB
239
 
240
//
241
// WISHBONE B3 compatible interface
242
//
243
// This follows the WISHBONE B3 specification.
244
// It is not enabled by default because most
245
// designs still don't use WB b3.
246
//
247
// To enable *wb_cti_o/*wb_bte_o ports,
248
// define this macro.
249
//
250
`define OR1200_WB_B3
251
 
252
//
253
// LOG all WISHBONE accesses
254
//
255
`define OR1200_LOG_WB_ACCESS
256
 
257
//
258
// Enable additional synthesis directives if using
259
// _Synopsys_ synthesis tool
260
//
261
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
262
 
263
//
264
// Enables default statement in some case blocks
265
// and disables Synopsys synthesis directive full_case
266
//
267
// By default it is enabled. When disabled it
268
// can increase clock frequency.
269
//
270
`define OR1200_CASE_DEFAULT
271
 
272
//
273
// Operand width / register file address width
274
//
275
// (DO NOT CHANGE)
276
//
277
`define OR1200_OPERAND_WIDTH            32
278
`define OR1200_REGFILE_ADDR_WIDTH       5
279
 
280
//
281
// l.add/l.addi/l.and and optional l.addc/l.addic
282
// also set (compare) flag when result of their
283
// operation equals zero
284
//
285
// At the time of writing this, default or32
286
// C/C++ compiler doesn't generate code that
287
// would benefit from this optimization.
288
//
289
// By default this optimization is disabled to
290
// save area.
291
//
292
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
293
 
294
//
295
// Implement l.addc/l.addic instructions
296
//
297
// By default implementation of l.addc/l.addic
298
// instructions is enabled in case you need them.
299
// If you don't use them, then disable implementation
300
// to save area.
301
//
302
//`define OR1200_IMPL_ADDC
303
 
304
//
305
// Implement l.sub instruction
306
//
307
// By default implementation of l.sub instructions
308
// is enabled to be compliant with the simulator.
309
// If you don't use carry bit, then disable
310
// implementation to save area.
311
//
312
`define OR1200_IMPL_SUB
313
 
314
//
315
// Implement carry bit SR[CY]
316
//
317
//
318
// By default implementation of SR[CY] is enabled
319
// to be compliant with the simulator. However SR[CY]
320
// is explicitly only used by l.addc/l.addic/l.sub
321
// instructions and if these three insns are not
322
// implemented there is not much point having SR[CY].
323
//
324
//`define OR1200_IMPL_CY
325
 
326
//
327
// Implement rotate in the ALU
328
//
329
// At the time of writing this, or32
330
// C/C++ compiler doesn't generate rotate
331
// instructions. However or32 assembler
332
// can assemble code that uses rotate insn.
333
// This means that rotate instructions
334
// must be used manually inserted.
335
//
336
// By default implementation of rotate
337
// is disabled to save area and increase
338
// clock frequency.
339
//
340
//`define OR1200_IMPL_ALU_ROTATE
341
 
342
//
343
// Type of ALU compare to implement
344
//
345
// Try either one to find what yields
346
// higher clock frequencyin your case.
347
//
348
//`define OR1200_IMPL_ALU_COMP1
349
`define OR1200_IMPL_ALU_COMP2
350
 
351
//
352
// Implement Find First/Last '1'
353
//
354
`define OR1200_IMPL_ALU_FFL1
355
 
356
//
357
// Implement multiplier
358
//
359
// By default multiplier is implemented
360
//
361
`define OR1200_MULT_IMPLEMENTED
362
 
363
//
364
// Implement multiply-and-accumulate
365
//
366
// By default MAC is implemented. To
367
// implement MAC, multiplier (non-serial) needs to be
368
// implemented.
369
//
370
//`define OR1200_MAC_IMPLEMENTED
371
 
372
//
373
// Implement optional l.div/l.divu instructions
374
//
375
// By default divide instructions are not implemented
376
// to save area.
377
//
378
//
379
//`define OR1200_DIV_IMPLEMENTED
380
 
381
//
382
// Serial multiplier.
383
//
384
//`define OR1200_MULT_SERIAL
385
 
386
//
387
// Serial divider.
388
// Uncomment to use a serial divider, otherwise will
389
// be a generic parallel implementation.
390
//
391
`define OR1200_DIV_SERIAL
392
 
393
//
394
// Implement HW Single Precision FPU
395
//
396
//`define OR1200_FPU_IMPLEMENTED
397
 
398
 
399
//
400
// Clock ratio RISC clock versus WB clock
401
//
402
// If you plan to run WB:RISC clock fixed to 1:1, disable
403
// both defines
404
//
405
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
406
// and use clmode to set ratio
407
//
408
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
409
// clmode to set ratio
410
//
411
//`define OR1200_CLKDIV_2_SUPPORTED
412
//`define OR1200_CLKDIV_4_SUPPORTED
413
 
414
//
415
// Type of register file RAM
416
//
417
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
418
//`define OR1200_RFRAM_TWOPORT
419
//
420
// Memory macro dual port (see or1200_dpram.v)
421
`define OR1200_RFRAM_DUALPORT
422
 
423
//
424
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
425
//`define OR1200_RFRAM_GENERIC
426
//  Generic register file supports - 16 registers 
427
`ifdef OR1200_RFRAM_GENERIC
428
//    `define OR1200_RFRAM_16REG
429
`endif
430
 
431
//
432
// Type of mem2reg aligner to implement.
433
//
434
// Once OR1200_IMPL_MEM2REG2 yielded faster
435
// circuit, however with today tools it will
436
// most probably give you slower circuit.
437
//
438
`define OR1200_IMPL_MEM2REG1
439
//`define OR1200_IMPL_MEM2REG2
440
 
441
//
442
// Reset value and event
443
//
444
`ifdef OR1200_RST_ACT_LOW
445
  `define OR1200_RST_VALUE      (1'b0)
446
  `define OR1200_RST_EVENT      negedge
447
`else
448
  `define OR1200_RST_VALUE      (1'b1)
449
  `define OR1200_RST_EVENT      posedge
450
`endif
451
 
452
//
453
// ALUOPs
454
//
455
`define OR1200_ALUOP_WIDTH      4
456
`define OR1200_ALUOP_NOP        4'd4
457
/* Order defined by arith insns that have two source operands both in regs
458
   (see binutils/include/opcode/or32.h) */
459
`define OR1200_ALUOP_ADD        4'd0
460
`define OR1200_ALUOP_ADDC       4'd1
461
`define OR1200_ALUOP_SUB        4'd2
462
`define OR1200_ALUOP_AND        4'd3
463
`define OR1200_ALUOP_OR         4'd4
464
`define OR1200_ALUOP_XOR        4'd5
465
`define OR1200_ALUOP_MUL        4'd6
466
`define OR1200_ALUOP_CUST5      4'd7
467
`define OR1200_ALUOP_SHROT      4'd8
468
`define OR1200_ALUOP_DIV        4'd9
469
`define OR1200_ALUOP_DIVU       4'd10
470
`define OR1200_ALUOP_MULU       4'd11
471
/* Values sent to ALU from decode unit - not strictly defined by ISA */
472
`define OR1200_ALUOP_MOVHI      4'd12
473
`define OR1200_ALUOP_COMP       4'd13
474
`define OR1200_ALUOP_MTSR       4'd14
475
`define OR1200_ALUOP_MFSR       4'd15
476
`define OR1200_ALUOP_CMOV       4'd14
477
`define OR1200_ALUOP_FFL1       4'd15
478
 
479
 
480
// ALU instructions second opcode field (previously multicycle field in 
481
// machine word)
482
`define OR1200_ALUOP2_POS               9:8
483
`define OR1200_ALUOP2_WIDTH     2
484
 
485
 
486
//
487
// MACOPs
488
//
489
`define OR1200_MACOP_WIDTH      3
490
`define OR1200_MACOP_NOP        3'b000
491
`define OR1200_MACOP_MAC        3'b001
492
`define OR1200_MACOP_MSB        3'b010
493
 
494
//
495
// Shift/rotate ops
496
//
497
`define OR1200_SHROTOP_WIDTH    2
498
`define OR1200_SHROTOP_NOP      2'd0
499
`define OR1200_SHROTOP_SLL      2'd0
500
`define OR1200_SHROTOP_SRL      2'd1
501
`define OR1200_SHROTOP_SRA      2'd2
502
`define OR1200_SHROTOP_ROR      2'd3
503
 
504
// Execution cycles per instruction
505
`define OR1200_MULTICYCLE_WIDTH 3
506
`define OR1200_ONE_CYCLE                3'd0
507
`define OR1200_TWO_CYCLES               3'd1
508
 
509
// Execution control which will "wait on" a module to finish
510
`define OR1200_WAIT_ON_WIDTH 2
511
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd1
512
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd2
513
 
514
// Operand MUX selects
515
`define OR1200_SEL_WIDTH                2
516
`define OR1200_SEL_RF                   2'd0
517
`define OR1200_SEL_IMM                  2'd1
518
`define OR1200_SEL_EX_FORW              2'd2
519
`define OR1200_SEL_WB_FORW              2'd3
520
 
521
//
522
// BRANCHOPs
523
//
524
`define OR1200_BRANCHOP_WIDTH           3
525
`define OR1200_BRANCHOP_NOP             3'd0
526
`define OR1200_BRANCHOP_J               3'd1
527
`define OR1200_BRANCHOP_JR              3'd2
528
`define OR1200_BRANCHOP_BAL             3'd3
529
`define OR1200_BRANCHOP_BF              3'd4
530
`define OR1200_BRANCHOP_BNF             3'd5
531
`define OR1200_BRANCHOP_RFE             3'd6
532
 
533
//
534
// LSUOPs
535
//
536
// Bit 0: sign extend
537
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
538
// Bit 3: 0 load, 1 store
539
`define OR1200_LSUOP_WIDTH              4
540
`define OR1200_LSUOP_NOP                4'b0000
541
`define OR1200_LSUOP_LBZ                4'b0010
542
`define OR1200_LSUOP_LBS                4'b0011
543
`define OR1200_LSUOP_LHZ                4'b0100
544
`define OR1200_LSUOP_LHS                4'b0101
545
`define OR1200_LSUOP_LWZ                4'b0110
546
`define OR1200_LSUOP_LWS                4'b0111
547
`define OR1200_LSUOP_LD                 4'b0001
548
`define OR1200_LSUOP_SD                 4'b1000
549
`define OR1200_LSUOP_SB                 4'b1010
550
`define OR1200_LSUOP_SH                 4'b1100
551
`define OR1200_LSUOP_SW                 4'b1110
552
 
553
// Number of bits of load/store EA precalculated in ID stage
554
// for balancing ID and EX stages.
555
//
556
// Valid range: 2,3,...,30,31
557
`define OR1200_LSUEA_PRECALC            2
558
 
559
// FETCHOPs
560
`define OR1200_FETCHOP_WIDTH            1
561
`define OR1200_FETCHOP_NOP              1'b0
562
`define OR1200_FETCHOP_LW               1'b1
563
 
564
//
565
// Register File Write-Back OPs
566
//
567
// Bit 0: register file write enable
568
// Bits 3-1: write-back mux selects
569
//
570
`define OR1200_RFWBOP_WIDTH             4
571
`define OR1200_RFWBOP_NOP               4'b0000
572
`define OR1200_RFWBOP_ALU               3'b000
573
`define OR1200_RFWBOP_LSU               3'b001
574
`define OR1200_RFWBOP_SPRS              3'b010
575
`define OR1200_RFWBOP_LR                3'b011
576
`define OR1200_RFWBOP_FPU               3'b100
577
 
578
// Compare instructions
579
`define OR1200_COP_SFEQ       3'b000
580
`define OR1200_COP_SFNE       3'b001
581
`define OR1200_COP_SFGT       3'b010
582
`define OR1200_COP_SFGE       3'b011
583
`define OR1200_COP_SFLT       3'b100
584
`define OR1200_COP_SFLE       3'b101
585
`define OR1200_COP_X          3'b111
586
`define OR1200_SIGNED_COMPARE 'd3
587
`define OR1200_COMPOP_WIDTH     4
588
 
589
//
590
// FP OPs
591
//
592
// MSbit indicates FPU operation valid
593
//
594
`define OR1200_FPUOP_WIDTH      8
595
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
596
`define OR1200_FPUOP_CYCLES 3'd4
597
// FP instruction is double precision if bit 4 is set. We're a 32-bit 
598
// implementation thus do not support double precision FP 
599
`define OR1200_FPUOP_DOUBLE_BIT 4
600
`define OR1200_FPUOP_ADD  8'b0000_0000
601
`define OR1200_FPUOP_SUB  8'b0000_0001
602
`define OR1200_FPUOP_MUL  8'b0000_0010
603
`define OR1200_FPUOP_DIV  8'b0000_0011
604
`define OR1200_FPUOP_ITOF 8'b0000_0100
605
`define OR1200_FPUOP_FTOI 8'b0000_0101
606
`define OR1200_FPUOP_REM  8'b0000_0110
607
`define OR1200_FPUOP_RESERVED  8'b0000_0111
608
// FP Compare instructions
609
`define OR1200_FPCOP_SFEQ 8'b0000_1000
610
`define OR1200_FPCOP_SFNE 8'b0000_1001
611
`define OR1200_FPCOP_SFGT 8'b0000_1010
612
`define OR1200_FPCOP_SFGE 8'b0000_1011
613
`define OR1200_FPCOP_SFLT 8'b0000_1100
614
`define OR1200_FPCOP_SFLE 8'b0000_1101
615
 
616
//
617
// TAGs for instruction bus
618
//
619
`define OR1200_ITAG_IDLE        4'h0    // idle bus
620
`define OR1200_ITAG_NI          4'h1    // normal insn
621
`define OR1200_ITAG_BE          4'hb    // Bus error exception
622
`define OR1200_ITAG_PE          4'hc    // Page fault exception
623
`define OR1200_ITAG_TE          4'hd    // TLB miss exception
624
 
625
//
626
// TAGs for data bus
627
//
628
`define OR1200_DTAG_IDLE        4'h0    // idle bus
629
`define OR1200_DTAG_ND          4'h1    // normal data
630
`define OR1200_DTAG_AE          4'ha    // Alignment exception
631
`define OR1200_DTAG_BE          4'hb    // Bus error exception
632
`define OR1200_DTAG_PE          4'hc    // Page fault exception
633
`define OR1200_DTAG_TE          4'hd    // TLB miss exception
634
 
635
 
636
//////////////////////////////////////////////
637
//
638
// ORBIS32 ISA specifics
639
//
640
 
641
// SHROT_OP position in machine word
642
`define OR1200_SHROTOP_POS              7:6
643
 
644
//
645
// Instruction opcode groups (basic)
646
//
647
`define OR1200_OR32_J                 6'b000000
648
`define OR1200_OR32_JAL               6'b000001
649
`define OR1200_OR32_BNF               6'b000011
650
`define OR1200_OR32_BF                6'b000100
651
`define OR1200_OR32_NOP               6'b000101
652
`define OR1200_OR32_MOVHI             6'b000110
653
`define OR1200_OR32_XSYNC             6'b001000
654
`define OR1200_OR32_RFE               6'b001001
655
/* */
656
`define OR1200_OR32_JR                6'b010001
657
`define OR1200_OR32_JALR              6'b010010
658
`define OR1200_OR32_MACI              6'b010011
659
/* */
660
`define OR1200_OR32_LWZ               6'b100001
661
`define OR1200_OR32_LBZ               6'b100011
662
`define OR1200_OR32_LBS               6'b100100
663
`define OR1200_OR32_LHZ               6'b100101
664
`define OR1200_OR32_LHS               6'b100110
665
`define OR1200_OR32_ADDI              6'b100111
666
`define OR1200_OR32_ADDIC             6'b101000
667
`define OR1200_OR32_ANDI              6'b101001
668
`define OR1200_OR32_ORI               6'b101010
669
`define OR1200_OR32_XORI              6'b101011
670
`define OR1200_OR32_MULI              6'b101100
671
`define OR1200_OR32_MFSPR             6'b101101
672
`define OR1200_OR32_SH_ROTI           6'b101110
673
`define OR1200_OR32_SFXXI             6'b101111
674
/* */
675
`define OR1200_OR32_MTSPR             6'b110000
676
`define OR1200_OR32_MACMSB            6'b110001
677
`define OR1200_OR32_FLOAT             6'b110010
678
/* */
679
`define OR1200_OR32_SW                6'b110101
680
`define OR1200_OR32_SB                6'b110110
681
`define OR1200_OR32_SH                6'b110111
682
`define OR1200_OR32_ALU               6'b111000
683
`define OR1200_OR32_SFXX              6'b111001
684
//`define OR1200_OR32_CUST5             6'b111100
685
 
686
 
687
/////////////////////////////////////////////////////
688
//
689
// Exceptions
690
//
691
 
692
//
693
// Exception vectors per OR1K architecture:
694
// 0xPPPPP100 - reset
695
// 0xPPPPP200 - bus error
696
// ... etc
697
// where P represents exception prefix.
698
//
699
// Exception vectors can be customized as per
700
// the following formula:
701
// 0xPPPPPNVV - exception N
702
//
703
// P represents exception prefix
704
// N represents exception N
705
// VV represents length of the individual vector space,
706
//   usually it is 8 bits wide and starts with all bits zero
707
//
708
 
709
//
710
// PPPPP and VV parts
711
//
712
// Sum of these two defines needs to be 28
713
//
714
`define OR1200_EXCEPT_EPH0_P    20'h00000
715
`define OR1200_EXCEPT_EPH1_P    20'hF0000
716
`define OR1200_EXCEPT_V             8'h00
717
 
718
//
719
// N part width
720
//
721
`define OR1200_EXCEPT_WIDTH 4
722
 
723
//
724
// Definition of exception vectors
725
//
726
// To avoid implementation of a certain exception,
727
// simply comment out corresponding line
728
//
729
`define OR1200_EXCEPT_UNUSED            `OR1200_EXCEPT_WIDTH'hf
730
`define OR1200_EXCEPT_TRAP              `OR1200_EXCEPT_WIDTH'he
731
`define OR1200_EXCEPT_FLOAT             `OR1200_EXCEPT_WIDTH'hd
732
`define OR1200_EXCEPT_SYSCALL           `OR1200_EXCEPT_WIDTH'hc
733
`define OR1200_EXCEPT_RANGE             `OR1200_EXCEPT_WIDTH'hb
734
`define OR1200_EXCEPT_ITLBMISS          `OR1200_EXCEPT_WIDTH'ha
735
`define OR1200_EXCEPT_DTLBMISS          `OR1200_EXCEPT_WIDTH'h9
736
`define OR1200_EXCEPT_INT               `OR1200_EXCEPT_WIDTH'h8
737
`define OR1200_EXCEPT_ILLEGAL           `OR1200_EXCEPT_WIDTH'h7
738
`define OR1200_EXCEPT_ALIGN             `OR1200_EXCEPT_WIDTH'h6
739
`define OR1200_EXCEPT_TICK              `OR1200_EXCEPT_WIDTH'h5
740
`define OR1200_EXCEPT_IPF               `OR1200_EXCEPT_WIDTH'h4
741
`define OR1200_EXCEPT_DPF               `OR1200_EXCEPT_WIDTH'h3
742
`define OR1200_EXCEPT_BUSERR            `OR1200_EXCEPT_WIDTH'h2
743
`define OR1200_EXCEPT_RESET             `OR1200_EXCEPT_WIDTH'h1
744
`define OR1200_EXCEPT_NONE              `OR1200_EXCEPT_WIDTH'h0
745
 
746
 
747
/////////////////////////////////////////////////////
748
//
749
// SPR groups
750
//
751
 
752
// Bits that define the group
753
`define OR1200_SPR_GROUP_BITS   15:11
754
 
755
// Width of the group bits
756
`define OR1200_SPR_GROUP_WIDTH  5
757
 
758
// Bits that define offset inside the group
759
`define OR1200_SPR_OFS_BITS 10:0
760
 
761
// List of groups
762
`define OR1200_SPR_GROUP_SYS    5'd00
763
`define OR1200_SPR_GROUP_DMMU   5'd01
764
`define OR1200_SPR_GROUP_IMMU   5'd02
765
`define OR1200_SPR_GROUP_DC     5'd03
766
`define OR1200_SPR_GROUP_IC     5'd04
767
`define OR1200_SPR_GROUP_MAC    5'd05
768
`define OR1200_SPR_GROUP_DU     5'd06
769
`define OR1200_SPR_GROUP_PM     5'd08
770
`define OR1200_SPR_GROUP_PIC    5'd09
771
`define OR1200_SPR_GROUP_TT     5'd10
772
`define OR1200_SPR_GROUP_FPU    5'd11
773
 
774
/////////////////////////////////////////////////////
775
//
776
// System group
777
//
778
 
779
//
780
// System registers
781
//
782
`define OR1200_SPR_CFGR         7'd0
783
`define OR1200_SPR_RF           6'd32   // 1024 >> 5
784
`define OR1200_SPR_NPC          11'd16
785
`define OR1200_SPR_SR           11'd17
786
`define OR1200_SPR_PPC          11'd18
787
`define OR1200_SPR_FPCSR        11'd20
788
`define OR1200_SPR_EPCR         11'd32
789
`define OR1200_SPR_EEAR         11'd48
790
`define OR1200_SPR_ESR          11'd64
791
 
792
//
793
// SR bits
794
//
795
`define OR1200_SR_WIDTH 17
796
`define OR1200_SR_SM   0
797
`define OR1200_SR_TEE  1
798
`define OR1200_SR_IEE  2
799
`define OR1200_SR_DCE  3
800
`define OR1200_SR_ICE  4
801
`define OR1200_SR_DME  5
802
`define OR1200_SR_IME  6
803
`define OR1200_SR_LEE  7
804
`define OR1200_SR_CE   8
805
`define OR1200_SR_F    9
806
`define OR1200_SR_CY   10       // Unused
807
`define OR1200_SR_OV   11       // Unused
808
`define OR1200_SR_OVE  12       // Unused
809
`define OR1200_SR_DSX  13       // Unused
810
`define OR1200_SR_EPH  14
811
`define OR1200_SR_FO   15
812
`define OR1200_SR_TED  16
813
`define OR1200_SR_CID  31:28    // Unimplemented
814
 
815
//
816
// Bits that define offset inside the group
817
//
818
`define OR1200_SPROFS_BITS 10:0
819
 
820
//
821
// Default Exception Prefix
822
//
823
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
824
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
825
//
826
`define OR1200_SR_EPH_DEF       1'b0
827
 
828
 
829
//
830
// FPCSR bits
831
//
832
`define OR1200_FPCSR_WIDTH 12
833
`define OR1200_FPCSR_FPEE  0
834
`define OR1200_FPCSR_RM    2:1
835
`define OR1200_FPCSR_OVF   3
836
`define OR1200_FPCSR_UNF   4
837
`define OR1200_FPCSR_SNF   5
838
`define OR1200_FPCSR_QNF   6
839
`define OR1200_FPCSR_ZF    7
840
`define OR1200_FPCSR_IXF   8
841
`define OR1200_FPCSR_IVF   9
842
`define OR1200_FPCSR_INF   10
843
`define OR1200_FPCSR_DZF   11
844
`define OR1200_FPCSR_RES   31:12
845
 
846
/////////////////////////////////////////////////////
847
//
848
// Power Management (PM)
849
//
850
 
851
// Define it if you want PM implemented
852
//`define OR1200_PM_IMPLEMENTED
853
 
854
// Bit positions inside PMR (don't change)
855
`define OR1200_PM_PMR_SDF 3:0
856
`define OR1200_PM_PMR_DME 4
857
`define OR1200_PM_PMR_SME 5
858
`define OR1200_PM_PMR_DCGE 6
859
`define OR1200_PM_PMR_UNUSED 31:7
860
 
861
// PMR offset inside PM group of registers
862
`define OR1200_PM_OFS_PMR 11'b0
863
 
864
// PM group
865
`define OR1200_SPRGRP_PM 5'd8
866
 
867
// Define if PMR can be read/written at any address inside PM group
868
`define OR1200_PM_PARTIAL_DECODING
869
 
870
// Define if reading PMR is allowed
871
`define OR1200_PM_READREGS
872
 
873
// Define if unused PMR bits should be zero
874
`define OR1200_PM_UNUSED_ZERO
875
 
876
 
877
/////////////////////////////////////////////////////
878
//
879
// Debug Unit (DU)
880
//
881
 
882
// Define it if you want DU implemented
883
`define OR1200_DU_IMPLEMENTED
884
 
885
//
886
// Define if you want HW Breakpoints
887
// (if HW breakpoints are not implemented
888
// only default software trapping is
889
// possible with l.trap insn - this is
890
// however already enough for use
891
// with or32 gdb)
892
//
893
//`define OR1200_DU_HWBKPTS
894
 
895
// Number of DVR/DCR pairs if HW breakpoints enabled
896
//      Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number ! 
897
//      DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS 
898
`define OR1200_DU_DVRDCR_PAIRS 8
899
 
900
// Define if you want trace buffer
901
//      (for now only available for Xilinx Virtex FPGAs)
902
//`define OR1200_DU_TB_IMPLEMENTED
903
 
904
 
905
//
906
// Address offsets of DU registers inside DU group
907
//
908
// To not implement a register, doq not define its address
909
//
910
`ifdef OR1200_DU_HWBKPTS
911
`define OR1200_DU_DVR0          11'd0
912
`define OR1200_DU_DVR1          11'd1
913
`define OR1200_DU_DVR2          11'd2
914
`define OR1200_DU_DVR3          11'd3
915
`define OR1200_DU_DVR4          11'd4
916
`define OR1200_DU_DVR5          11'd5
917
`define OR1200_DU_DVR6          11'd6
918
`define OR1200_DU_DVR7          11'd7
919
`define OR1200_DU_DCR0          11'd8
920
`define OR1200_DU_DCR1          11'd9
921
`define OR1200_DU_DCR2          11'd10
922
`define OR1200_DU_DCR3          11'd11
923
`define OR1200_DU_DCR4          11'd12
924
`define OR1200_DU_DCR5          11'd13
925
`define OR1200_DU_DCR6          11'd14
926
`define OR1200_DU_DCR7          11'd15
927
`endif
928
`define OR1200_DU_DMR1          11'd16
929
`ifdef OR1200_DU_HWBKPTS
930
`define OR1200_DU_DMR2          11'd17
931
`define OR1200_DU_DWCR0         11'd18
932
`define OR1200_DU_DWCR1         11'd19
933
`endif
934
`define OR1200_DU_DSR           11'd20
935
`define OR1200_DU_DRR           11'd21
936
`ifdef OR1200_DU_TB_IMPLEMENTED
937
`define OR1200_DU_TBADR         11'h0ff
938
`define OR1200_DU_TBIA          11'h1??
939
`define OR1200_DU_TBIM          11'h2??
940
`define OR1200_DU_TBAR          11'h3??
941
`define OR1200_DU_TBTS          11'h4??
942
`endif
943
 
944
// Position of offset bits inside SPR address
945
`define OR1200_DUOFS_BITS       10:0
946
 
947
// DCR bits
948
`define OR1200_DU_DCR_DP        0
949
`define OR1200_DU_DCR_CC        3:1
950
`define OR1200_DU_DCR_SC        4
951
`define OR1200_DU_DCR_CT        7:5
952
 
953
// DMR1 bits
954
`define OR1200_DU_DMR1_CW0      1:0
955
`define OR1200_DU_DMR1_CW1      3:2
956
`define OR1200_DU_DMR1_CW2      5:4
957
`define OR1200_DU_DMR1_CW3      7:6
958
`define OR1200_DU_DMR1_CW4      9:8
959
`define OR1200_DU_DMR1_CW5      11:10
960
`define OR1200_DU_DMR1_CW6      13:12
961
`define OR1200_DU_DMR1_CW7      15:14
962
`define OR1200_DU_DMR1_CW8      17:16
963
`define OR1200_DU_DMR1_CW9      19:18
964
`define OR1200_DU_DMR1_CW10     21:20
965
`define OR1200_DU_DMR1_ST       22
966
`define OR1200_DU_DMR1_BT       23
967
`define OR1200_DU_DMR1_DXFW     24
968
`define OR1200_DU_DMR1_ETE      25
969
 
970
// DMR2 bits
971
`define OR1200_DU_DMR2_WCE0     0
972
`define OR1200_DU_DMR2_WCE1     1
973
`define OR1200_DU_DMR2_AWTC     12:2
974
`define OR1200_DU_DMR2_WGB      23:13
975
 
976
// DWCR bits
977
`define OR1200_DU_DWCR_COUNT    15:0
978
`define OR1200_DU_DWCR_MATCH    31:16
979
 
980
// DSR bits
981
`define OR1200_DU_DSR_WIDTH     14
982
`define OR1200_DU_DSR_RSTE      0
983
`define OR1200_DU_DSR_BUSEE     1
984
`define OR1200_DU_DSR_DPFE      2
985
`define OR1200_DU_DSR_IPFE      3
986
`define OR1200_DU_DSR_TTE       4
987
`define OR1200_DU_DSR_AE        5
988
`define OR1200_DU_DSR_IIE       6
989
`define OR1200_DU_DSR_IE        7
990
`define OR1200_DU_DSR_DME       8
991
`define OR1200_DU_DSR_IME       9
992
`define OR1200_DU_DSR_RE        10
993
`define OR1200_DU_DSR_SCE       11
994
`define OR1200_DU_DSR_FPE       12
995
`define OR1200_DU_DSR_TE        13
996
 
997
// DRR bits
998
`define OR1200_DU_DRR_RSTE      0
999
`define OR1200_DU_DRR_BUSEE     1
1000
`define OR1200_DU_DRR_DPFE      2
1001
`define OR1200_DU_DRR_IPFE      3
1002
`define OR1200_DU_DRR_TTE       4
1003
`define OR1200_DU_DRR_AE        5
1004
`define OR1200_DU_DRR_IIE       6
1005
`define OR1200_DU_DRR_IE        7
1006
`define OR1200_DU_DRR_DME       8
1007
`define OR1200_DU_DRR_IME       9
1008
`define OR1200_DU_DRR_RE        10
1009
`define OR1200_DU_DRR_SCE       11
1010
`define OR1200_DU_DRR_FPE       12
1011
`define OR1200_DU_DRR_TE        13
1012
 
1013
// Define if reading DU regs is allowed
1014
`define OR1200_DU_READREGS
1015
 
1016
// Define if unused DU registers bits should be zero
1017
`define OR1200_DU_UNUSED_ZERO
1018
 
1019
// Define if IF/LSU status is not needed by devel i/f
1020
`define OR1200_DU_STATUS_UNIMPLEMENTED
1021
 
1022
/////////////////////////////////////////////////////
1023
//
1024
// Programmable Interrupt Controller (PIC)
1025
//
1026
 
1027
// Define it if you want PIC implemented
1028
`define OR1200_PIC_IMPLEMENTED
1029
 
1030
// Define number of interrupt inputs (2-31)
1031
`define OR1200_PIC_INTS 20
1032
 
1033
// Address offsets of PIC registers inside PIC group
1034
`define OR1200_PIC_OFS_PICMR 2'd0
1035
`define OR1200_PIC_OFS_PICSR 2'd2
1036
 
1037
// Position of offset bits inside SPR address
1038
`define OR1200_PICOFS_BITS 1:0
1039
 
1040
// Define if you want these PIC registers to be implemented
1041
`define OR1200_PIC_PICMR
1042
`define OR1200_PIC_PICSR
1043
 
1044
// Define if reading PIC registers is allowed
1045
`define OR1200_PIC_READREGS
1046
 
1047
// Define if unused PIC register bits should be zero
1048
`define OR1200_PIC_UNUSED_ZERO
1049
 
1050
 
1051
/////////////////////////////////////////////////////
1052
//
1053
// Tick Timer (TT)
1054
//
1055
 
1056
// Define it if you want TT implemented
1057
`define OR1200_TT_IMPLEMENTED
1058
 
1059
// Address offsets of TT registers inside TT group
1060
`define OR1200_TT_OFS_TTMR 1'd0
1061
`define OR1200_TT_OFS_TTCR 1'd1
1062
 
1063
// Position of offset bits inside SPR group
1064
`define OR1200_TTOFS_BITS 0
1065
 
1066
// Define if you want these TT registers to be implemented
1067
`define OR1200_TT_TTMR
1068
`define OR1200_TT_TTCR
1069
 
1070
// TTMR bits
1071
`define OR1200_TT_TTMR_TP 27:0
1072
`define OR1200_TT_TTMR_IP 28
1073
`define OR1200_TT_TTMR_IE 29
1074
`define OR1200_TT_TTMR_M 31:30
1075
 
1076
// Define if reading TT registers is allowed
1077
`define OR1200_TT_READREGS
1078
 
1079
 
1080
//////////////////////////////////////////////
1081
//
1082
// MAC
1083
//
1084
`define OR1200_MAC_ADDR         0        // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
1085
`define OR1200_MAC_SPR_WE               // Define if MACLO/MACHI are SPR writable
1086
 
1087
//
1088
// Shift {MACHI,MACLO} into destination register when executing l.macrc
1089
//
1090
// According to architecture manual there is no shift, so default value is 0.
1091
// However the implementation has deviated in this from the arch manual and had
1092
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding 
1093
// (if using libmad fixed point library). Shifts are no longer default setup, 
1094
// but if you need to remain backward compatible, define your shift bits, which
1095
// were normally
1096
// dest_GPR = {MACHI,MACLO}[59:28]
1097
`define OR1200_MAC_SHIFTBY      0        // 0 = According to arch manual, 28 = obsolete backward compatibility
1098
 
1099
 
1100
//////////////////////////////////////////////
1101
//
1102
// Data MMU (DMMU)
1103
//
1104
 
1105
//
1106
// Address that selects between TLB TR and MR
1107
//
1108
`define OR1200_DTLB_TM_ADDR     7
1109
 
1110
//
1111
// DTLBMR fields
1112
//
1113
`define OR1200_DTLBMR_V_BITS    0
1114
`define OR1200_DTLBMR_CID_BITS  4:1
1115
`define OR1200_DTLBMR_RES_BITS  11:5
1116
`define OR1200_DTLBMR_VPN_BITS  31:13
1117
 
1118
//
1119
// DTLBTR fields
1120
//
1121
`define OR1200_DTLBTR_CC_BITS   0
1122
`define OR1200_DTLBTR_CI_BITS   1
1123
`define OR1200_DTLBTR_WBC_BITS  2
1124
`define OR1200_DTLBTR_WOM_BITS  3
1125
`define OR1200_DTLBTR_A_BITS    4
1126
`define OR1200_DTLBTR_D_BITS    5
1127
`define OR1200_DTLBTR_URE_BITS  6
1128
`define OR1200_DTLBTR_UWE_BITS  7
1129
`define OR1200_DTLBTR_SRE_BITS  8
1130
`define OR1200_DTLBTR_SWE_BITS  9
1131
`define OR1200_DTLBTR_RES_BITS  11:10
1132
`define OR1200_DTLBTR_PPN_BITS  31:13
1133
 
1134
//
1135
// DTLB configuration
1136
//
1137
`define OR1200_DMMU_PS          13                                      // 13 for 8KB page size
1138
`define OR1200_DTLB_INDXW       6                                       // 6 for 64 entry DTLB  7 for 128 entries
1139
`define OR1200_DTLB_INDXL       `OR1200_DMMU_PS                         // 13                   13
1140
`define OR1200_DTLB_INDXH       `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1    // 18                   19
1141
`define OR1200_DTLB_INDX        `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL   // 18:13                19:13
1142
`define OR1200_DTLB_TAGW        32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS   // 13                   12
1143
`define OR1200_DTLB_TAGL        `OR1200_DTLB_INDXH+1                    // 19                   20
1144
`define OR1200_DTLB_TAG         31:`OR1200_DTLB_TAGL                    // 31:19                31:20
1145
`define OR1200_DTLBMRW          `OR1200_DTLB_TAGW+1                     // +1 because of V bit
1146
`define OR1200_DTLBTRW          32-`OR1200_DMMU_PS+5                    // +5 because of protection bits and CI
1147
 
1148
//
1149
// Cache inhibit while DMMU is not enabled/implemented
1150
//
1151
// cache inhibited 0GB-4GB              1'b1
1152
// cache inhibited 0GB-2GB              !dcpu_adr_i[31]
1153
// cache inhibited 0GB-1GB 2GB-3GB      !dcpu_adr_i[30]
1154
// cache inhibited 1GB-2GB 3GB-4GB      dcpu_adr_i[30]
1155
// cache inhibited 2GB-4GB (default)    dcpu_adr_i[31]
1156
// cached 0GB-4GB                       1'b0
1157
//
1158
`define OR1200_DMMU_CI                  dcpu_adr_i[31]
1159
 
1160
 
1161
//////////////////////////////////////////////
1162
//
1163
// Insn MMU (IMMU)
1164
//
1165
 
1166
//
1167
// Address that selects between TLB TR and MR
1168
//
1169
`define OR1200_ITLB_TM_ADDR     7
1170
 
1171
//
1172
// ITLBMR fields
1173
//
1174
`define OR1200_ITLBMR_V_BITS    0
1175
`define OR1200_ITLBMR_CID_BITS  4:1
1176
`define OR1200_ITLBMR_RES_BITS  11:5
1177
`define OR1200_ITLBMR_VPN_BITS  31:13
1178
 
1179
//
1180
// ITLBTR fields
1181
//
1182
`define OR1200_ITLBTR_CC_BITS   0
1183
`define OR1200_ITLBTR_CI_BITS   1
1184
`define OR1200_ITLBTR_WBC_BITS  2
1185
`define OR1200_ITLBTR_WOM_BITS  3
1186
`define OR1200_ITLBTR_A_BITS    4
1187
`define OR1200_ITLBTR_D_BITS    5
1188
`define OR1200_ITLBTR_SXE_BITS  6
1189
`define OR1200_ITLBTR_UXE_BITS  7
1190
`define OR1200_ITLBTR_RES_BITS  11:8
1191
`define OR1200_ITLBTR_PPN_BITS  31:13
1192
 
1193
//
1194
// ITLB configuration
1195
//
1196
`define OR1200_IMMU_PS          13                                      // 13 for 8KB page size
1197
`define OR1200_ITLB_INDXW       6                                       // 6 for 64 entry ITLB  7 for 128 entries
1198
`define OR1200_ITLB_INDXL       `OR1200_IMMU_PS                         // 13                   13
1199
`define OR1200_ITLB_INDXH       `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1    // 18                   19
1200
`define OR1200_ITLB_INDX        `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL   // 18:13                19:13
1201
`define OR1200_ITLB_TAGW        32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS   // 13                   12
1202
`define OR1200_ITLB_TAGL        `OR1200_ITLB_INDXH+1                    // 19                   20
1203
`define OR1200_ITLB_TAG         31:`OR1200_ITLB_TAGL                    // 31:19                31:20
1204
`define OR1200_ITLBMRW          `OR1200_ITLB_TAGW+1                     // +1 because of V bit
1205
`define OR1200_ITLBTRW          32-`OR1200_IMMU_PS+3                    // +3 because of protection bits and CI
1206
 
1207
//
1208
// Cache inhibit while IMMU is not enabled/implemented
1209
// Note: all combinations that use icpu_adr_i cause async loop
1210
//
1211
// cache inhibited 0GB-4GB              1'b1
1212
// cache inhibited 0GB-2GB              !icpu_adr_i[31]
1213
// cache inhibited 0GB-1GB 2GB-3GB      !icpu_adr_i[30]
1214
// cache inhibited 1GB-2GB 3GB-4GB      icpu_adr_i[30]
1215
// cache inhibited 2GB-4GB (default)    icpu_adr_i[31]
1216
// cached 0GB-4GB                       1'b0
1217
//
1218
`define OR1200_IMMU_CI                  1'b0
1219
 
1220
 
1221
/////////////////////////////////////////////////
1222
//
1223
// Insn cache (IC)
1224
//
1225
 
1226
// 4 for 16 byte line, 5 for 32 byte lines.
1227
`ifdef OR1200_IC_1W_32KB
1228
 `define OR1200_ICLS            5
1229
`else
1230
 `define OR1200_ICLS            4
1231
`endif
1232
 
1233
//
1234
// IC configurations
1235
//
1236
`ifdef OR1200_IC_1W_512B
1237
`define OR1200_ICSIZE                   9                       // 512
1238
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 7
1239
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 8
1240
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 9
1241
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS // 5
1242
`define OR1200_ICTAG_W                  24
1243
`endif
1244
`ifdef OR1200_IC_1W_4KB
1245
`define OR1200_ICSIZE                   12                      // 4096
1246
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 10
1247
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 11
1248
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 12
1249
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 8
1250
`define OR1200_ICTAG_W                  21
1251
`endif
1252
`ifdef OR1200_IC_1W_8KB
1253
`define OR1200_ICSIZE                   13                      // 8192
1254
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 11
1255
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 12
1256
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 13
1257
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 9
1258
`define OR1200_ICTAG_W                  20
1259
`endif
1260
`ifdef OR1200_IC_1W_16KB
1261
`define OR1200_ICSIZE                   14                      // 16384
1262
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 12
1263
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 13
1264
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 14
1265
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 10
1266
`define OR1200_ICTAG_W                  19
1267
`endif
1268
`ifdef OR1200_IC_1W_32KB
1269
`define OR1200_ICSIZE                   15                      // 32768
1270
`define OR1200_ICINDX                   `OR1200_ICSIZE-2        // 13
1271
`define OR1200_ICINDXH                  `OR1200_ICSIZE-1        // 14
1272
`define OR1200_ICTAGL                   `OR1200_ICINDXH+1       // 14
1273
`define OR1200_ICTAG                    `OR1200_ICSIZE-`OR1200_ICLS     // 10
1274
`define OR1200_ICTAG_W                  18
1275
`endif
1276
 
1277
 
1278
/////////////////////////////////////////////////
1279
//
1280
// Data cache (DC)
1281
//
1282
 
1283
// 4 for 16 bytes, 5 for 32 bytes
1284
`ifdef OR1200_DC_1W_32KB
1285
 `define OR1200_DCLS            5
1286
`else
1287
 `define OR1200_DCLS            4
1288
`endif
1289
 
1290
// Define to enable default behavior of cache as write through
1291
// Turning this off enabled write back statergy
1292
//
1293
`define OR1200_DC_WRITETHROUGH
1294
 
1295
// Define to enable stores from the stack not doing writethrough.
1296
// EXPERIMENTAL
1297
//`define OR1200_DC_NOSTACKWRITETHROUGH
1298
 
1299
// Data cache SPR definitions
1300
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
1301
// Data cache group SPR addresses
1302
`define OR1200_SPRGRP_DC_DCCR           3'd0 // Not implemented
1303
`define OR1200_SPRGRP_DC_DCBPR          3'd1 // Not implemented
1304
`define OR1200_SPRGRP_DC_DCBFR          3'd2
1305
`define OR1200_SPRGRP_DC_DCBIR          3'd3
1306
`define OR1200_SPRGRP_DC_DCBWR          3'd4 // Not implemented
1307
`define OR1200_SPRGRP_DC_DCBLR          3'd5 // Not implemented
1308
 
1309
//
1310
// DC configurations
1311
//
1312
`ifdef OR1200_DC_1W_4KB
1313
`define OR1200_DCSIZE                   12                      // 4096
1314
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 10
1315
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 11
1316
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 12
1317
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 8
1318
`define OR1200_DCTAG_W                  21
1319
`endif
1320
`ifdef OR1200_DC_1W_8KB
1321
`define OR1200_DCSIZE                   13                      // 8192
1322
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 11
1323
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 12
1324
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 13
1325
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 9
1326
`define OR1200_DCTAG_W                  20
1327
`endif
1328
`ifdef OR1200_DC_1W_16KB
1329
`define OR1200_DCSIZE                   14                      // 16384
1330
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 12
1331
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 13
1332
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 14
1333
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 10
1334
`define OR1200_DCTAG_W                  19
1335
`endif
1336
`ifdef OR1200_DC_1W_32KB
1337
`define OR1200_DCSIZE                   15                      // 32768
1338
`define OR1200_DCINDX                   `OR1200_DCSIZE-2        // 13
1339
`define OR1200_DCINDXH                  `OR1200_DCSIZE-1        // 14
1340
`define OR1200_DCTAGL                   `OR1200_DCINDXH+1       // 15
1341
`define OR1200_DCTAG                    `OR1200_DCSIZE-`OR1200_DCLS     // 10
1342
`define OR1200_DCTAG_W                  18
1343
`endif
1344
 
1345
 
1346
/////////////////////////////////////////////////
1347
//
1348
// Store buffer (SB)
1349
//
1350
 
1351
//
1352
// Store buffer
1353
//
1354
// It will improve performance by "caching" CPU stores
1355
// using store buffer. This is most important for function
1356
// prologues because DC can only work in write though mode
1357
// and all stores would have to complete external WB writes
1358
// to memory.
1359
// Store buffer is between DC and data BIU.
1360
// All stores will be stored into store buffer and immediately
1361
// completed by the CPU, even though actual external writes
1362
// will be performed later. As a consequence store buffer masks
1363
// all data bus errors related to stores (data bus errors
1364
// related to loads are delivered normally).
1365
// All pending CPU loads will wait until store buffer is empty to
1366
// ensure strict memory model. Right now this is necessary because
1367
// we don't make destinction between cached and cache inhibited
1368
// address space, so we simply empty store buffer until loads
1369
// can begin.
1370
//
1371
// It makes design a bit bigger, depending what is the number of
1372
// entries in SB FIFO. Number of entries can be changed further
1373
// down.
1374
//
1375
//`define OR1200_SB_IMPLEMENTED
1376
 
1377
//
1378
// Number of store buffer entries
1379
//
1380
// Verified number of entries are 4 and 8 entries
1381
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
1382
// always match 2**OR1200_SB_LOG.
1383
// To disable store buffer, undefine
1384
// OR1200_SB_IMPLEMENTED.
1385
//
1386
`define OR1200_SB_LOG           2       // 2 or 3
1387
`define OR1200_SB_ENTRIES       4       // 4 or 8
1388
 
1389
 
1390
/////////////////////////////////////////////////
1391
//
1392
// Quick Embedded Memory (QMEM)
1393
//
1394
 
1395
//
1396
// Quick Embedded Memory
1397
//
1398
// Instantiation of dedicated insn/data memory (RAM or ROM).
1399
// Insn fetch has effective throughput 1insn / clock cycle.
1400
// Data load takes two clock cycles / access, data store
1401
// takes 1 clock cycle / access (if there is no insn fetch)).
1402
// Memory instantiation is shared between insn and data,
1403
// meaning if insn fetch are performed, data load/store
1404
// performance will be lower.
1405
//
1406
// Main reason for QMEM is to put some time critical functions
1407
// into this memory and to have predictable and fast access
1408
// to these functions. (soft fpu, context switch, exception
1409
// handlers, stack, etc)
1410
//
1411
// It makes design a bit bigger and slower. QMEM sits behind
1412
// IMMU/DMMU so all addresses are physical (so the MMUs can be
1413
// used with QMEM and QMEM is seen by the CPU just like any other
1414
// memory in the system). IC/DC are sitting behind QMEM so the
1415
// whole design timing might be worse with QMEM implemented.
1416
//
1417
//`define OR1200_QMEM_IMPLEMENTED
1418
 
1419
//
1420
// Base address and mask of QMEM
1421
//
1422
// Base address defines first address of QMEM. Mask defines
1423
// QMEM range in address space. Actual size of QMEM is however
1424
// determined with instantiated RAM/ROM. However bigger
1425
// mask will reserve more address space for QMEM, but also
1426
// make design faster, while more tight mask will take
1427
// less address space but also make design slower. If
1428
// instantiated RAM/ROM is smaller than space reserved with
1429
// the mask, instatiated RAM/ROM will also be shadowed
1430
// at higher addresses in reserved space.
1431
//
1432
`define OR1200_QMEM_IADDR       32'h0080_0000
1433
`define OR1200_QMEM_IMASK       32'hfff0_0000 // Max QMEM size 1MB
1434
`define OR1200_QMEM_DADDR       32'h0080_0000
1435
`define OR1200_QMEM_DMASK       32'hfff0_0000 // Max QMEM size 1MB
1436
 
1437
//
1438
// QMEM interface byte-select capability
1439
//
1440
// To enable qmem_sel* ports, define this macro.
1441
//
1442
//`define OR1200_QMEM_BSEL
1443
 
1444
//
1445
// QMEM interface acknowledge
1446
//
1447
// To enable qmem_ack port, define this macro.
1448
//
1449
//`define OR1200_QMEM_ACK
1450
 
1451
/////////////////////////////////////////////////////
1452
//
1453
// VR, UPR and Configuration Registers
1454
//
1455
//
1456
// VR, UPR and configuration registers are optional. If 
1457
// implemented, operating system can automatically figure
1458
// out how to use the processor because it knows 
1459
// what units are available in the processor and how they
1460
// are configured.
1461
//
1462
// This section must be last in or1200_defines.v file so
1463
// that all units are already configured and thus
1464
// configuration registers are properly set.
1465
// 
1466
 
1467
// Define if you want configuration registers implemented
1468
//`define OR1200_CFGR_IMPLEMENTED
1469
 
1470
// Define if you want full address decode inside SYS group
1471
`define OR1200_SYS_FULL_DECODE
1472
 
1473
// Offsets of VR, UPR and CFGR registers
1474
`define OR1200_SPRGRP_SYS_VR            4'h0
1475
`define OR1200_SPRGRP_SYS_UPR           4'h1
1476
`define OR1200_SPRGRP_SYS_CPUCFGR       4'h2
1477
`define OR1200_SPRGRP_SYS_DMMUCFGR      4'h3
1478
`define OR1200_SPRGRP_SYS_IMMUCFGR      4'h4
1479
`define OR1200_SPRGRP_SYS_DCCFGR        4'h5
1480
`define OR1200_SPRGRP_SYS_ICCFGR        4'h6
1481
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
1482
 
1483
// VR fields
1484
`define OR1200_VR_REV_BITS              5:0
1485
`define OR1200_VR_RES1_BITS             15:6
1486
`define OR1200_VR_CFG_BITS              23:16
1487
`define OR1200_VR_VER_BITS              31:24
1488
 
1489
// VR values
1490
`define OR1200_VR_REV                   6'h08
1491
`define OR1200_VR_RES1                  10'h000
1492
`define OR1200_VR_CFG                   8'h00
1493
`define OR1200_VR_VER                   8'h12
1494
 
1495
// UPR fields
1496
`define OR1200_UPR_UP_BITS              0
1497
`define OR1200_UPR_DCP_BITS             1
1498
`define OR1200_UPR_ICP_BITS             2
1499
`define OR1200_UPR_DMP_BITS             3
1500
`define OR1200_UPR_IMP_BITS             4
1501
`define OR1200_UPR_MP_BITS              5
1502
`define OR1200_UPR_DUP_BITS             6
1503
`define OR1200_UPR_PCUP_BITS            7
1504
`define OR1200_UPR_PMP_BITS             8
1505
`define OR1200_UPR_PICP_BITS            9
1506
`define OR1200_UPR_TTP_BITS             10
1507
`define OR1200_UPR_FPP_BITS             11
1508
`define OR1200_UPR_RES1_BITS            23:12
1509
`define OR1200_UPR_CUP_BITS             31:24
1510
 
1511
// UPR values
1512
`define OR1200_UPR_UP                   1'b1
1513
`ifdef OR1200_NO_DC
1514
`define OR1200_UPR_DCP                  1'b0
1515
`else
1516
`define OR1200_UPR_DCP                  1'b1
1517
`endif
1518
`ifdef OR1200_NO_IC
1519
`define OR1200_UPR_ICP                  1'b0
1520
`else
1521
`define OR1200_UPR_ICP                  1'b1
1522
`endif
1523
`ifdef OR1200_NO_DMMU
1524
`define OR1200_UPR_DMP                  1'b0
1525
`else
1526
`define OR1200_UPR_DMP                  1'b1
1527
`endif
1528
`ifdef OR1200_NO_IMMU
1529
`define OR1200_UPR_IMP                  1'b0
1530
`else
1531
`define OR1200_UPR_IMP                  1'b1
1532
`endif
1533
`ifdef OR1200_MAC_IMPLEMENTED
1534
`define OR1200_UPR_MP                   1'b1
1535
`else
1536
`define OR1200_UPR_MP                   1'b0
1537
`endif
1538
`ifdef OR1200_DU_IMPLEMENTED
1539
`define OR1200_UPR_DUP                  1'b1
1540
`else
1541
`define OR1200_UPR_DUP                  1'b0
1542
`endif
1543
`define OR1200_UPR_PCUP                 1'b0    // Performance counters not present
1544
`ifdef OR1200_PM_IMPLEMENTED
1545
`define OR1200_UPR_PMP                  1'b1
1546
`else
1547
`define OR1200_UPR_PMP                  1'b0
1548
`endif
1549
`ifdef OR1200_PIC_IMPLEMENTED
1550
`define OR1200_UPR_PICP                 1'b1
1551
`else
1552
`define OR1200_UPR_PICP                 1'b0
1553
`endif
1554
`ifdef OR1200_TT_IMPLEMENTED
1555
`define OR1200_UPR_TTP                  1'b1
1556
`else
1557
`define OR1200_UPR_TTP                  1'b0
1558
`endif
1559
`ifdef OR1200_FPU_IMPLEMENTED
1560
`define OR1200_UPR_FPP                  1'b1
1561
`else
1562
`define OR1200_UPR_FPP                  1'b0
1563
`endif
1564
`define OR1200_UPR_RES1                 12'h000
1565
`define OR1200_UPR_CUP                  8'h00
1566
 
1567
// CPUCFGR fields
1568
`define OR1200_CPUCFGR_NSGF_BITS        3:0
1569
`define OR1200_CPUCFGR_HGF_BITS     4
1570
`define OR1200_CPUCFGR_OB32S_BITS       5
1571
`define OR1200_CPUCFGR_OB64S_BITS       6
1572
`define OR1200_CPUCFGR_OF32S_BITS       7
1573
`define OR1200_CPUCFGR_OF64S_BITS       8
1574
`define OR1200_CPUCFGR_OV64S_BITS       9
1575
`define OR1200_CPUCFGR_RES1_BITS        31:10
1576
 
1577
// CPUCFGR values
1578
`define OR1200_CPUCFGR_NSGF                 4'h0
1579
`ifdef OR1200_RFRAM_16REG
1580
    `define OR1200_CPUCFGR_HGF                  1'b1
1581
`else
1582
    `define OR1200_CPUCFGR_HGF                  1'b0
1583
`endif
1584
`define OR1200_CPUCFGR_OB32S            1'b1
1585
`define OR1200_CPUCFGR_OB64S            1'b0
1586
`ifdef OR1200_FPU_IMPLEMENTED
1587
 `define OR1200_CPUCFGR_OF32S           1'b1
1588
`else
1589
 `define OR1200_CPUCFGR_OF32S           1'b0
1590
`endif
1591
 
1592
`define OR1200_CPUCFGR_OF64S            1'b0
1593
`define OR1200_CPUCFGR_OV64S            1'b0
1594
`define OR1200_CPUCFGR_RES1             22'h000000
1595
 
1596
// DMMUCFGR fields
1597
`define OR1200_DMMUCFGR_NTW_BITS        1:0
1598
`define OR1200_DMMUCFGR_NTS_BITS        4:2
1599
`define OR1200_DMMUCFGR_NAE_BITS        7:5
1600
`define OR1200_DMMUCFGR_CRI_BITS        8
1601
`define OR1200_DMMUCFGR_PRI_BITS        9
1602
`define OR1200_DMMUCFGR_TEIRI_BITS      10
1603
`define OR1200_DMMUCFGR_HTR_BITS        11
1604
`define OR1200_DMMUCFGR_RES1_BITS       31:12
1605
 
1606
// DMMUCFGR values
1607
`ifdef OR1200_NO_DMMU
1608
`define OR1200_DMMUCFGR_NTW             2'h0    // Irrelevant
1609
`define OR1200_DMMUCFGR_NTS             3'h0    // Irrelevant
1610
`define OR1200_DMMUCFGR_NAE             3'h0    // Irrelevant
1611
`define OR1200_DMMUCFGR_CRI             1'b0    // Irrelevant
1612
`define OR1200_DMMUCFGR_PRI             1'b0    // Irrelevant
1613
`define OR1200_DMMUCFGR_TEIRI           1'b0    // Irrelevant
1614
`define OR1200_DMMUCFGR_HTR             1'b0    // Irrelevant
1615
`define OR1200_DMMUCFGR_RES1            20'h00000
1616
`else
1617
`define OR1200_DMMUCFGR_NTW             2'h0    // 1 TLB way
1618
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW       // Num TLB sets
1619
`define OR1200_DMMUCFGR_NAE             3'h0    // No ATB entries
1620
`define OR1200_DMMUCFGR_CRI             1'b0    // No control register
1621
`define OR1200_DMMUCFGR_PRI             1'b0    // No protection reg
1622
`define OR1200_DMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl.
1623
`define OR1200_DMMUCFGR_HTR             1'b0    // No HW TLB reload
1624
`define OR1200_DMMUCFGR_RES1            20'h00000
1625
`endif
1626
 
1627
// IMMUCFGR fields
1628
`define OR1200_IMMUCFGR_NTW_BITS        1:0
1629
`define OR1200_IMMUCFGR_NTS_BITS        4:2
1630
`define OR1200_IMMUCFGR_NAE_BITS        7:5
1631
`define OR1200_IMMUCFGR_CRI_BITS        8
1632
`define OR1200_IMMUCFGR_PRI_BITS        9
1633
`define OR1200_IMMUCFGR_TEIRI_BITS      10
1634
`define OR1200_IMMUCFGR_HTR_BITS        11
1635
`define OR1200_IMMUCFGR_RES1_BITS       31:12
1636
 
1637
// IMMUCFGR values
1638
`ifdef OR1200_NO_IMMU
1639
`define OR1200_IMMUCFGR_NTW             2'h0    // Irrelevant
1640
`define OR1200_IMMUCFGR_NTS             3'h0    // Irrelevant
1641
`define OR1200_IMMUCFGR_NAE             3'h0    // Irrelevant
1642
`define OR1200_IMMUCFGR_CRI             1'b0    // Irrelevant
1643
`define OR1200_IMMUCFGR_PRI             1'b0    // Irrelevant
1644
`define OR1200_IMMUCFGR_TEIRI           1'b0    // Irrelevant
1645
`define OR1200_IMMUCFGR_HTR             1'b0    // Irrelevant
1646
`define OR1200_IMMUCFGR_RES1            20'h00000
1647
`else
1648
`define OR1200_IMMUCFGR_NTW             2'h0    // 1 TLB way
1649
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW       // Num TLB sets
1650
`define OR1200_IMMUCFGR_NAE             3'h0    // No ATB entry
1651
`define OR1200_IMMUCFGR_CRI             1'b0    // No control reg
1652
`define OR1200_IMMUCFGR_PRI             1'b0    // No protection reg
1653
`define OR1200_IMMUCFGR_TEIRI           1'b1    // TLB entry inv reg impl
1654
`define OR1200_IMMUCFGR_HTR             1'b0    // No HW TLB reload
1655
`define OR1200_IMMUCFGR_RES1            20'h00000
1656
`endif
1657
 
1658
// DCCFGR fields
1659
`define OR1200_DCCFGR_NCW_BITS          2:0
1660
`define OR1200_DCCFGR_NCS_BITS          6:3
1661
`define OR1200_DCCFGR_CBS_BITS          7
1662
`define OR1200_DCCFGR_CWS_BITS          8
1663
`define OR1200_DCCFGR_CCRI_BITS         9
1664
`define OR1200_DCCFGR_CBIRI_BITS        10
1665
`define OR1200_DCCFGR_CBPRI_BITS        11
1666
`define OR1200_DCCFGR_CBLRI_BITS        12
1667
`define OR1200_DCCFGR_CBFRI_BITS        13
1668
`define OR1200_DCCFGR_CBWBRI_BITS       14
1669
`define OR1200_DCCFGR_RES1_BITS 31:15
1670
 
1671
// DCCFGR values
1672
`ifdef OR1200_NO_DC
1673
`define OR1200_DCCFGR_NCW               3'h0    // Irrelevant
1674
`define OR1200_DCCFGR_NCS               4'h0    // Irrelevant
1675
`define OR1200_DCCFGR_CBS               1'b0    // Irrelevant
1676
`define OR1200_DCCFGR_CWS               1'b0    // Irrelevant
1677
`define OR1200_DCCFGR_CCRI              1'b0    // Irrelevant
1678
`define OR1200_DCCFGR_CBIRI             1'b0    // Irrelevant
1679
`define OR1200_DCCFGR_CBPRI             1'b0    // Irrelevant
1680
`define OR1200_DCCFGR_CBLRI             1'b0    // Irrelevant
1681
`define OR1200_DCCFGR_CBFRI             1'b0    // Irrelevant
1682
`define OR1200_DCCFGR_CBWBRI            1'b0    // Irrelevant
1683
`define OR1200_DCCFGR_RES1              17'h00000
1684
`else
1685
`define OR1200_DCCFGR_NCW               3'h0    // 1 cache way
1686
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG)       // Num cache sets
1687
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
1688
`ifdef OR1200_DC_WRITETHROUGH
1689
 `define OR1200_DCCFGR_CWS              1'b0    // Write-through strategy
1690
`else
1691
 `define OR1200_DCCFGR_CWS              1'b1    // Write-back strategy
1692
`endif
1693
`define OR1200_DCCFGR_CCRI              1'b1    // Cache control reg impl.
1694
`define OR1200_DCCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1695
`define OR1200_DCCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1696
`define OR1200_DCCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1697
`define OR1200_DCCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1698
`ifdef OR1200_DC_WRITETHROUGH
1699
 `define OR1200_DCCFGR_CBWBRI           1'b0    // Cache block WB reg not impl.
1700
`else
1701
 `define OR1200_DCCFGR_CBWBRI           1'b1    // Cache block WB reg impl.
1702
`endif
1703
`define OR1200_DCCFGR_RES1              17'h00000
1704
`endif
1705
 
1706
// ICCFGR fields
1707
`define OR1200_ICCFGR_NCW_BITS          2:0
1708
`define OR1200_ICCFGR_NCS_BITS          6:3
1709
`define OR1200_ICCFGR_CBS_BITS          7
1710
`define OR1200_ICCFGR_CWS_BITS          8
1711
`define OR1200_ICCFGR_CCRI_BITS         9
1712
`define OR1200_ICCFGR_CBIRI_BITS        10
1713
`define OR1200_ICCFGR_CBPRI_BITS        11
1714
`define OR1200_ICCFGR_CBLRI_BITS        12
1715
`define OR1200_ICCFGR_CBFRI_BITS        13
1716
`define OR1200_ICCFGR_CBWBRI_BITS       14
1717
`define OR1200_ICCFGR_RES1_BITS 31:15
1718
 
1719
// ICCFGR values
1720
`ifdef OR1200_NO_IC
1721
`define OR1200_ICCFGR_NCW               3'h0    // Irrelevant
1722
`define OR1200_ICCFGR_NCS               4'h0    // Irrelevant
1723
`define OR1200_ICCFGR_CBS               1'b0    // Irrelevant
1724
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1725
`define OR1200_ICCFGR_CCRI              1'b0    // Irrelevant
1726
`define OR1200_ICCFGR_CBIRI             1'b0    // Irrelevant
1727
`define OR1200_ICCFGR_CBPRI             1'b0    // Irrelevant
1728
`define OR1200_ICCFGR_CBLRI             1'b0    // Irrelevant
1729
`define OR1200_ICCFGR_CBFRI             1'b0    // Irrelevant
1730
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1731
`define OR1200_ICCFGR_RES1              17'h00000
1732
`else
1733
`define OR1200_ICCFGR_NCW               3'h0    // 1 cache way
1734
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG)       // Num cache sets
1735
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1  // 16 byte cache block
1736
`define OR1200_ICCFGR_CWS               1'b0    // Irrelevant
1737
`define OR1200_ICCFGR_CCRI              1'b1    // Cache control reg impl.
1738
`define OR1200_ICCFGR_CBIRI             1'b1    // Cache block inv reg impl.
1739
`define OR1200_ICCFGR_CBPRI             1'b0    // Cache block prefetch reg not impl.
1740
`define OR1200_ICCFGR_CBLRI             1'b0    // Cache block lock reg not impl.
1741
`define OR1200_ICCFGR_CBFRI             1'b1    // Cache block flush reg impl.
1742
`define OR1200_ICCFGR_CBWBRI            1'b0    // Irrelevant
1743
`define OR1200_ICCFGR_RES1              17'h00000
1744
`endif
1745
 
1746
// DCFGR fields
1747
`define OR1200_DCFGR_NDP_BITS           3:0
1748
`define OR1200_DCFGR_WPCI_BITS          4
1749
`define OR1200_DCFGR_RES1_BITS          31:5
1750
 
1751
// DCFGR values
1752
`ifdef OR1200_DU_HWBKPTS
1753
`define OR1200_DCFGR_NDP                4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
1754
`ifdef OR1200_DU_DWCR0
1755
`define OR1200_DCFGR_WPCI               1'b1
1756
`else
1757
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1758
`endif
1759
`else
1760
`define OR1200_DCFGR_NDP                4'h0    // Zero DVR/DCR pairs
1761
`define OR1200_DCFGR_WPCI               1'b0    // WP counters not impl.
1762
`endif
1763
`define OR1200_DCFGR_RES1               27'd0
1764
 
1765
///////////////////////////////////////////////////////////////////////////////
1766
// Boot Address Selection                                                    //
1767
//                                                                           //
1768
// Allows a definable boot address, potentially different to the usual reset //
1769
// vector to allow for power-on code to be run, if desired.                  //
1770
//                                                                           //
1771
// OR1200_BOOT_ADR should be the 32-bit address of the boot location         //
1772
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2)              //
1773
//                                                                           //
1774
// For default reset behavior uncomment the settings under the "Boot 0x100"  //
1775
// comment below.                                                            //
1776
//                                                                           //
1777
///////////////////////////////////////////////////////////////////////////////
1778
// Boot from 0xf0000100
1779
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
1780
//`define OR1200_BOOT_ADR 32'hf0000100
1781
// Boot from 0x100
1782
 `define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
1783
 `define OR1200_BOOT_ADR 32'h00000100

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