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[/] [minsoc/] [trunk/] [backend/] [std/] [minsoc_bench_defines.v] - Blame information for rev 141

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Line No. Rev Author Line
1 2 rfajardo
//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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`define GENERIC_FPGA
3 60 rfajardo
`define MEMORY_MODEL        //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
4 28 rfajardo
`define NO_CLOCK_DIVISION   //if commented out, generic clock division is implemented (odd divisors are rounded down)
5 2 rfajardo
//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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7 141 rfajardo
`define FREQ_NUM_FOR_NS 100000000
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9 2 rfajardo
`define FREQ 25000000
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`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
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12 17 rfajardo
`define ETH_PHY_FREQ  25000000
13 28 rfajardo
`define ETH_PHY_PERIOD  (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ)    //40ns
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15 69 rfajardo
`define UART_BAUDRATE 115200
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17 17 rfajardo
`define VPI_DEBUG
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19 2 rfajardo
//`define VCD_OUTPUT
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//`define START_UP                                              //pass firmware over spi to or1k_startup
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`define INITIALIZE_MEMORY_MODEL                 //instantaneously initialize memory model with firmware
24 64 rfajardo
                                                                                //only use with the memory model. 
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                                        //If you use the original memory (`define MEMORY_MODEL 
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                                        //commented out), comment this too.
27 141 rfajardo
 
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`define TEST_UART
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//`define TEST_ETHERNET

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