OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_bench.v] - Blame information for rev 141

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 133 rfajardo
`include "minsoc_bench_defines.v"
2
`include "minsoc_defines.v"
3
`include "or1200_defines.v"
4
 
5
`include "timescale.v"
6
 
7
module minsoc_bench();
8
 
9
`ifdef POSITIVE_RESET
10
    localparam RESET_LEVEL = 1'b1;
11
`elsif NEGATIVE_RESET
12
    localparam RESET_LEVEL = 1'b0;
13
`else
14
    localparam RESET_LEVEL = 1'b1;
15
`endif
16
 
17
reg clock, reset;
18
 
19
//Debug interface
20
wire dbg_tms_i;
21
wire dbg_tck_i;
22
wire dbg_tdi_i;
23
wire dbg_tdo_o;
24
wire jtag_vref;
25
wire jtag_gnd;
26
 
27
//SPI wires
28
wire spi_mosi;
29
reg spi_miso;
30
wire spi_sclk;
31
wire [1:0] spi_ss;
32
 
33
//UART wires
34
wire uart_stx;
35
reg uart_srx;
36
 
37
//ETH wires
38
reg eth_col;
39
reg eth_crs;
40
wire eth_trst;
41
reg eth_tx_clk;
42
wire eth_tx_en;
43
wire eth_tx_er;
44
wire [3:0] eth_txd;
45
reg eth_rx_clk;
46
reg eth_rx_dv;
47
reg eth_rx_er;
48
reg [3:0] eth_rxd;
49
reg eth_fds_mdint;
50
wire eth_mdc;
51
wire eth_mdio;
52
 
53
//
54
//      TASKS registers to communicate with interfaces
55
//
56
reg design_ready;
57
reg uart_echo;
58
`ifdef UART
59
reg [40*8-1:0] line;
60
reg [12*8-1:0] hello;
61
reg new_line;
62
reg new_char;
63
`endif
64
`ifdef ETHERNET
65
reg [7:0] eth_rx_data [0:1535];            //receive buffer ETH (max packet 1536)
66
reg [7:0] eth_tx_data [0:1535];     //send buffer ETH (max packet 1536)
67
localparam ETH_HDR = 14;
68
localparam ETH_PAYLOAD_MAX_LENGTH = 1518;//only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
69
`endif
70
 
71
 
72
//
73
// Testbench mechanics
74
//
75
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
76
integer initialize, ptr;
77
reg [8*64:0] file_name;
78
integer      firmware_size;  // Note that the .hex file size is greater than this, as each byte in the file needs 2 hex characters.
79
integer      firmware_size_in_header;
80
reg load_file;
81
 
82
initial begin
83
    reset = ~RESET_LEVEL;
84
    clock = 1'b0;
85
        eth_tx_clk = 1'b0;
86
        eth_rx_clk = 1'b0;
87
 
88
    design_ready = 1'b0;
89
    uart_echo = 1'b1;
90
 
91
`ifndef NO_CLOCK_DIVISION
92
    minsoc_top_0.clk_adjust.clk_int = 1'b0;
93
    minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;
94
`endif
95
 
96
    uart_srx = 1'b1;
97
 
98
        eth_col = 1'b0;
99
        eth_crs = 1'b0;
100
        eth_fds_mdint = 1'b1;
101
        eth_rx_er = 1'b0;
102
        eth_rxd = 4'h0;
103
        eth_rx_dv = 1'b0;
104
 
105
 
106
//dual and two port rams from FPGA memory instances have to be initialized to 0
107
    init_fpga_memory();
108
 
109
        load_file = 1'b0;
110
`ifdef INITIALIZE_MEMORY_MODEL
111
        load_file = 1'b1;
112
`endif
113
`ifdef START_UP
114
        load_file = 1'b1;
115
`endif
116
 
117
        //get firmware hex file from command line input
118
        if ( load_file ) begin
119
                if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
120
                        $display("ERROR: Please specify the name of the firmware file to load on start-up.");
121
                        $finish;
122
                end
123
 
124
        // We are passing the firmware size separately as a command-line argument in order
125
        // to avoid this kind of Icarus Verilog warnings:
126
        //   WARNING: minsoc_bench_core.v:111: $readmemh: Standard inconsistency, following 1364-2005.
127
        //   WARNING: minsoc_bench_core.v:111: $readmemh(../../sw/uart/uart.hex): Not enough words in the file for the requested range [0:32767].
128
        // Apparently, some of the $readmemh() warnigns are even required by the standard. The trouble is,
129
        // Verilog's $fread() is not widely implemented in the simulators, so from Verilog alone
130
        // it's not easy to read the firmware file header without getting such warnings.
131
                if ( ! $value$plusargs("firmware_size=%d", firmware_size) ) begin
132
                        $display("ERROR: Please specify the size of the firmware (in bytes) contained in the hex firmware file.");
133
                        $finish;
134
                end
135
 
136
                $readmemh(file_name, program_mem, 0, firmware_size - 1);
137
 
138
                firmware_size_in_header = { program_mem[0] , program_mem[1] , program_mem[2] , program_mem[3] };
139
 
140
        if ( firmware_size != firmware_size_in_header ) begin
141
                        $display("ERROR: The firmware size in the file header does not match the firmware size given as command-line argument. Did you forget bin2hex's -size_word flag when generating the firmware file?");
142
                        $finish;
143
        end
144
 
145
        end
146
 
147
`ifdef INITIALIZE_MEMORY_MODEL
148
        // Initialize memory with firmware
149
        initialize = 0;
150
        while ( initialize < firmware_size ) begin
151
                minsoc_top_0.onchip_ram_top.block_ram_3.mem[initialize/4] = program_mem[initialize];
152
                minsoc_top_0.onchip_ram_top.block_ram_2.mem[initialize/4] = program_mem[initialize+1];
153
                minsoc_top_0.onchip_ram_top.block_ram_1.mem[initialize/4] = program_mem[initialize+2];
154
                minsoc_top_0.onchip_ram_top.block_ram_0.mem[initialize/4] = program_mem[initialize+3];
155
        initialize = initialize + 4;
156
        end
157
        $display("Memory model initialized with firmware:");
158
        $display("%s", file_name);
159
        $display("%d Bytes loaded from %d ...", initialize , firmware_size);
160
`endif
161
 
162
    // Reset controller
163
    repeat (2) @ (negedge clock);
164
    reset = RESET_LEVEL;
165
    repeat (16) @ (negedge clock);
166
    reset = ~RESET_LEVEL;
167
 
168
`ifdef START_UP
169
        // Pass firmware over spi to or1k_startup
170
        ptr = 0;
171
        //read dummy
172
        send_spi(program_mem[ptr]);
173
        send_spi(program_mem[ptr]);
174
        send_spi(program_mem[ptr]);
175
        send_spi(program_mem[ptr]);
176
        //~read dummy
177
        while ( ptr < firmware_size ) begin
178
                send_spi(program_mem[ptr]);
179
                ptr = ptr + 1;
180
        end
181
        $display("Memory start-up completed...");
182
        $display("Loaded firmware:");
183
        $display("%s", file_name);
184
`endif
185
 
186
 
187
        //
188
    // Testbench START
189
        //
190
    design_ready = 1'b1;
191
    $display("Running simulation: if you want to stop it, type ctrl+c and type in finish afterwards.");
192
    fork
193
        begin
194
`ifdef UART
195
 
196
`ifdef ETHERNET
197
`ifdef TEST_ETHERNET
198
            $display("Testing Ethernet firmware, this takes long (~15 min. @ 2.53 GHz dual-core)...");
199
            $display("Ethernet firmware encloses UART firmware, testing UART firmware first...");
200
            test_uart();
201
            test_eth();
202
            $display("Stopping simulation.");
203
            $finish;
204
`endif
205
`endif
206
 
207
`ifdef TEST_UART
208
            $display("Testing UART firmware, this takes a while (~1 min. @ 2.53 GHz dual-core)...");
209
            test_uart();
210
            $display("Stopping simulation.");
211
            $finish;
212
`endif
213
 
214
`endif
215
        end
216
        begin
217
`ifdef ETHERNET
218
`ifdef TEST_ETHERNET
219
            get_mac();
220
            if ( { eth_rx_data[ETH_HDR] , eth_rx_data[ETH_HDR+1] , eth_rx_data[ETH_HDR+2] , eth_rx_data[ETH_HDR+3] } == 32'hFF2B4050 )
221
                $display("Ethernet firmware started correctly.");
222
`endif
223
`endif
224
        end
225
    join
226
 
227
end
228
 
229
 
230
//
231
// Modules instantiations
232
//
233
minsoc_top minsoc_top_0(
234
   .clk(clock),
235
   .reset(reset)
236
 
237
   //JTAG ports
238
`ifdef GENERIC_TAP
239
   , .jtag_tdi(dbg_tdi_i),
240
   .jtag_tms(dbg_tms_i),
241
   .jtag_tck(dbg_tck_i),
242
   .jtag_tdo(dbg_tdo_o),
243
   .jtag_vref(jtag_vref),
244
   .jtag_gnd(jtag_gnd)
245
`endif
246
 
247
   //SPI ports
248
`ifdef START_UP
249
   , .spi_flash_mosi(spi_mosi),
250
   .spi_flash_miso(spi_miso),
251
   .spi_flash_sclk(spi_sclk),
252
   .spi_flash_ss(spi_ss)
253
`endif
254
 
255
   //UART ports
256
`ifdef UART
257
   , .uart_stx(uart_stx),
258
   .uart_srx(uart_srx)
259
`endif // !UART
260
 
261
        // Ethernet ports
262
`ifdef ETHERNET
263
        , .eth_col(eth_col),
264
    .eth_crs(eth_crs),
265
    .eth_trste(eth_trst),
266
    .eth_tx_clk(eth_tx_clk),
267
        .eth_tx_en(eth_tx_en),
268
    .eth_tx_er(eth_tx_er),
269
    .eth_txd(eth_txd),
270
    .eth_rx_clk(eth_rx_clk),
271
        .eth_rx_dv(eth_rx_dv),
272
    .eth_rx_er(eth_rx_er),
273
    .eth_rxd(eth_rxd),
274
    .eth_fds_mdint(eth_fds_mdint),
275
        .eth_mdc(eth_mdc),
276
    .eth_mdio(eth_mdio)
277
`endif // !ETHERNET
278
);
279
 
280
`ifdef VPI_DEBUG
281
        dbg_comm_vpi dbg_if(
282
                .SYS_CLK(clock),
283
                .P_TMS(dbg_tms_i),
284
                .P_TCK(dbg_tck_i),
285
                .P_TRST(),
286
                .P_TDI(dbg_tdi_i),
287
                .P_TDO(dbg_tdo_o)
288
        );
289
`else
290
   assign dbg_tdi_i = 1;
291
   assign dbg_tck_i = 0;
292
   assign dbg_tms_i = 1;
293
`endif
294
 
295
 
296
//
297
// Firmware testers
298
//
299
`ifdef UART
300
task test_uart();
301
    begin
302
            @ (posedge new_line);
303
            $display("UART data received.");
304
            hello = line[12*8-1:0];
305
            //sending character A to UART, B expected
306
            $display("Testing UART interrupt...");
307
            uart_echo = 1'b0;
308
            uart_send(8'h41);       //Character A
309
            @ (posedge new_char);
310
            if ( line[7:0] == "B" )
311
                $display("UART interrupt working.");
312
            else
313
                $display("UART interrupt failed.");
314
            uart_echo = 1'b1;
315
 
316
            if ( hello == "Hello World." )
317
                $display("UART firmware test completed, behaving correctly.");
318
            else
319
                $display("UART firmware test completed, failed.");
320
    end
321
endtask
322
`endif
323
 
324
`ifdef ETHERNET
325
task test_eth();
326
    begin
327
                eth_tx_data[ETH_HDR+0] = 8'hBA;
328
                eth_tx_data[ETH_HDR+1] = 8'h87;
329
                eth_tx_data[ETH_HDR+2] = 8'hAA;
330
                eth_tx_data[ETH_HDR+3] = 8'hBB;
331
                eth_tx_data[ETH_HDR+4] = 8'hCC;
332
                eth_tx_data[ETH_HDR+5] = 8'hDD;
333
 
334
            $display("Sending an Ethernet package to the system and waiting for the data to be output through UART...");
335
                send_mac(6);
336
            repeat(3+40) @ (posedge new_line);
337
            $display("Ethernet test completed.");
338
    end
339
endtask
340
`endif
341
 
342
 
343
//
344
//      Regular clocking and output
345
//
346
always begin
347
    #((`CLK_PERIOD)/2) clock <= ~clock;
348
end
349
 
350
`ifdef VCD_OUTPUT
351
initial begin
352
        $dumpfile("../results/minsoc_wave.vcd");
353
        $dumpvars();
354
end
355
`endif
356
 
357
 
358
//
359
//      Functionalities tasks: SPI Startup and UART Monitor
360
//
361
//SPI START_UP
362
`ifdef START_UP
363
task send_spi;
364
    input [7:0] data_in;
365
    integer i;
366
    begin
367
        i = 7;
368
        for ( i = 7 ; i >= 0; i = i - 1 ) begin
369
                spi_miso = data_in[i];
370
                        @ (posedge spi_sclk);
371
            end
372
    end
373
endtask
374
`endif
375
//~SPI START_UP
376
 
377
//UART
378
`ifdef UART
379
localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE);
380
 
381
task uart_send;
382
    input [7:0] data;
383
    integer i;
384
    begin
385
        uart_srx = 1'b0;
386
        #UART_TX_WAIT;
387
        for ( i = 0; i < 8 ; i = i + 1 ) begin
388
                    uart_srx = data[i];
389
            #UART_TX_WAIT;
390
            end
391
        uart_srx = 1'b0;
392
        #UART_TX_WAIT;
393
            uart_srx = 1'b1;
394
    end
395
endtask
396
 
397
//UART Monitor (prints uart output on the terminal)
398
// Something to trigger the task
399
initial
400
begin
401
    new_line = 1'b0;
402
    new_char = 1'b0;
403
end
404
 
405
always @ (posedge clock)
406
    if ( design_ready )
407
        uart_decoder;
408
 
409
task uart_decoder;
410
        integer i;
411
        reg [7:0] tx_byte;
412
        begin
413
        new_char = 1'b0;
414
        // Wait for start bit
415
        while (uart_stx == 1'b1)
416
        @(uart_stx);
417
 
418
        #(UART_TX_WAIT + (UART_TX_WAIT/2));
419
 
420
        for ( i = 0; i < 8 ; i = i + 1 ) begin
421
            tx_byte[i] = uart_stx;
422
            #UART_TX_WAIT;
423
        end
424
 
425
        //Check for stop bit
426
        if (uart_stx == 1'b0) begin
427
            //$display("* WARNING: user stop bit not received when expected at time %d__", $time);
428
            // Wait for return to idle
429
            while (uart_stx == 1'b0)
430
            @(uart_stx);
431
            //$display("* USER UART returned to idle at time %d",$time);
432
        end
433
        // display the char
434
        new_char = 1'b1;
435
        if ( uart_echo )
436
            $write("%c", tx_byte);
437
        if ( new_line )
438
            line = "";
439
        if ( tx_byte == "\n" )
440
            new_line = 1'b1;
441
        else begin
442
            line = { line[39*8-1:0], tx_byte};
443
            new_line = 1'b0;
444
        end
445
    end
446
endtask
447
//~UART Monitor
448
`endif // !UART
449
//~UART
450
 
451
 
452
//
453
//      TASKS to communicate with interfaces
454
//
455
//MAC_DATA
456
//
457
`ifdef ETHERNET
458
reg [31:0] crc32_result;
459
 
460
task get_mac;
461
    integer conta;
462
    reg LSB;
463
    begin
464
        conta = 0;
465
        LSB = 1;
466
        @ ( posedge eth_tx_en);
467
 
468
        repeat (16) @ (negedge eth_tx_clk);  //8 bytes, preamble (7 bytes) + start of frame (1 byte)
469
 
470
        while ( eth_tx_en == 1'b1 ) begin
471
            @ (negedge eth_tx_clk) begin
472
                if ( LSB == 1'b1 )
473
                    eth_rx_data[conta][3:0] = eth_txd;
474
                else begin
475
                    eth_rx_data[conta][7:4] = eth_txd;
476
                    conta = conta + 1;
477
                end
478
                LSB = ~LSB;
479
            end
480
        end
481
    end
482
endtask
483
 
484
task send_mac;              //only able to send up to 1536 bytes with header (14 bytes) and CRC (4 bytes)
485
    input [31:0] length;    //ETH_PAYLOAD_MAX_LENGTH 1518
486
    integer conta;
487
    begin
488
        if ( length <= ETH_PAYLOAD_MAX_LENGTH ) begin
489
            //DEST MAC
490
            eth_tx_data[0] = 8'h55;
491
            eth_tx_data[1] = 8'h47;
492
            eth_tx_data[2] = 8'h34;
493
            eth_tx_data[3] = 8'h22;
494
            eth_tx_data[4] = 8'h88;
495
            eth_tx_data[5] = 8'h92;
496
 
497
            //SOURCE MAC
498
            eth_tx_data[6] = 8'h3D;
499
            eth_tx_data[7] = 8'h4F;
500
            eth_tx_data[8] = 8'h1A;
501
            eth_tx_data[9] = 8'hBE;
502
            eth_tx_data[10] = 8'h68;
503
            eth_tx_data[11] = 8'h72;
504
 
505
            //LEN
506
            eth_tx_data[12] = length[7:4];
507
            eth_tx_data[13] = length[3:0];
508
 
509
            //DATA input by task caller
510
 
511
            //PAD
512
            for ( conta = length+14; conta < 60; conta = conta + 1 ) begin
513
                eth_tx_data[conta] = 8'h00;
514
            end
515
 
516
            gencrc32(conta);
517
 
518
            eth_tx_data[conta] = crc32_result[31:24];
519
            eth_tx_data[conta+1] = crc32_result[23:16];
520
            eth_tx_data[conta+2] = crc32_result[15:8];
521
            eth_tx_data[conta+3] = crc32_result[7:0];
522
 
523
            send_rx_packet( 64'h0055_5555_5555_5555, 4'h7, 8'hD5, 32'h0000_0000, conta+4, 1'b0 );
524
        end
525
        else
526
            $display("Warning: Ethernet packet is to big to be sent.");
527
    end
528
 
529
endtask
530
 
531
task send_rx_packet;
532
  input  [(8*8)-1:0] preamble_data; // preamble data to be sent - correct is 64'h0055_5555_5555_5555
533
  input   [3:0] preamble_len; // length of preamble in bytes - max is 4'h8, correct is 4'h7 
534
  input   [7:0] sfd_data; // SFD data to be sent - correct is 8'hD5
535
  input  [31:0] start_addr; // start address
536
  input  [31:0] len; // length of frame in Bytes (without preamble and SFD)
537
  input         plus_drible_nibble; // if length is longer for one nibble
538
  integer       rx_cnt;
539
  reg    [31:0] eth_tx_data_addr_in; // address for reading from RX memory       
540
  reg     [7:0] eth_tx_data_data_out; // data for reading from RX memory
541
begin
542
      @(posedge eth_rx_clk);
543
       eth_rx_dv = 1;
544
 
545
      // set initial rx memory address
546
      eth_tx_data_addr_in = start_addr;
547
 
548
      // send preamble
549
      for (rx_cnt = 0; (rx_cnt < (preamble_len << 1)) && (rx_cnt < 16); rx_cnt = rx_cnt + 1)
550
      begin
551
         eth_rxd = preamble_data[3:0];
552
         preamble_data = preamble_data >> 4;
553
        @(posedge eth_rx_clk);
554
      end
555
 
556
      // send SFD
557
      for (rx_cnt = 0; rx_cnt < 2; rx_cnt = rx_cnt + 1)
558
      begin
559
         eth_rxd = sfd_data[3:0];
560
         sfd_data = sfd_data >> 4;
561
        @(posedge eth_rx_clk);
562
      end
563
 
564
      // send packet's addresses, type/length, data and FCS
565
      for (rx_cnt = 0; rx_cnt < len; rx_cnt = rx_cnt + 1)
566
      begin
567
        eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
568
        eth_rxd = eth_tx_data_data_out[3:0];
569
        @(posedge eth_rx_clk);
570
        eth_rxd = eth_tx_data_data_out[7:4];
571
        eth_tx_data_addr_in = eth_tx_data_addr_in + 1;
572
        @(posedge eth_rx_clk);
573
      end
574
      if (plus_drible_nibble)
575
      begin
576
        eth_tx_data_data_out = eth_tx_data[eth_tx_data_addr_in[21:0]];
577
        eth_rxd = eth_tx_data_data_out[3:0];
578
        @(posedge eth_rx_clk);
579
      end
580
 
581
       eth_rx_dv = 0;
582
      @(posedge eth_rx_clk);
583
 
584
end
585
endtask // send_rx_packet
586
 
587
//CRC32
588
localparam [31:0] CRC32_POLY = 32'h04C11DB7;
589
 
590
task gencrc32;
591
    input [31:0] crc32_length;
592
 
593
    integer     byte, bit;
594
    reg         msb;
595
    reg [7:0]    current_byte;
596
    reg [31:0]   temp;
597
 
598
    begin
599
        crc32_result = 32'hffffffff;
600
        for (byte = 0; byte < crc32_length; byte = byte + 1) begin
601
            current_byte = eth_tx_data[byte];
602
            for (bit = 0; bit < 8; bit = bit + 1) begin
603
                msb = crc32_result[31];
604
                crc32_result = crc32_result << 1;
605
                if (msb != current_byte[bit]) begin
606
                    crc32_result = crc32_result ^ CRC32_POLY;
607
                    crc32_result[0] = 1;
608
                end
609
            end
610
        end
611
 
612
        // Last step is to "mirror" every bit, swap the 4 bytes, and then complement each bit.
613
        //
614
        // Mirror:
615
        for (bit = 0; bit < 32; bit = bit + 1)
616
            temp[31-bit] = crc32_result[bit];
617
 
618
        // Swap and Complement:
619
        crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
620
    end
621
endtask
622
//~CRC32
623
 
624
`endif // !ETHERNET
625
//~MAC_DATA
626
 
627
//Generate tx and rx clocks
628
always begin
629
        #((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
630
end
631
always begin
632
        #((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
633
end
634
//~Generate tx and rx clocks
635
 
636
 
637
 
638
//
639
// TASK to initialize instantiated FPGA dual and two port memory to 0
640
//
641
task init_fpga_memory;
642
    integer i;
643
    begin
644
`ifdef OR1200_RFRAM_TWOPORT
645
`ifdef OR1200_XILINX_RAMB4
646
    for ( i = 0; i < (1<<8); i = i + 1 ) begin
647
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_0.mem[i] = 16'h0000;
648
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_s16_1.mem[i] = 16'h0000;
649
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_0.mem[i] = 16'h0000;
650
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_s16_1.mem[i] = 16'h0000;
651
    end
652
`elsif OR1200_XILINX_RAMB16
653
    for ( i = 0; i < (1<<9); i = i + 1 ) begin
654
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
655
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
656
    end
657
`elsif OR1200_ALTERA_LPM
658
`ifndef OR1200_ALTERA_LPM_XXX
659
    $display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
660
    $display("It uses GENERIC memory instead.");
661
    $display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
662
`endif
663
`ifdef OR1200_ALTERA_LPM_XXX
664
    $display("...Using ALTERA memory for TWOPORT RFRAM!");
665
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
666
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
667
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
668
    end
669
`else
670
    $display("...Using GENERIC memory!");
671
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
672
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
673
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
674
    end
675
`endif
676
`elsif OR1200_XILINX_RAM32X1D
677
    $display("Definition OR1200_XILINX_RAM32X1D in or1200_defines.v does not enable FPGA memory for TWO port RFRAM");
678
    $display("It uses GENERIC memory instead.");
679
    $display("FPGA memory can be used if you choose OR1200_RFRAM_DUALPORT");
680
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
681
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
682
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
683
    end
684
`else
685
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
686
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
687
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
688
    end
689
`endif
690
`elsif OR1200_RFRAM_DUALPORT
691
`ifdef OR1200_XILINX_RAMB4
692
    for ( i = 0; i < (1<<8); i = i + 1 ) begin
693
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[i] = 16'h0000;
694
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[i] = 16'h0000;
695
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_0.mem[i] = 16'h0000;
696
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb4_s16_1.mem[i] = 16'h0000;
697
    end
698
`elsif OR1200_XILINX_RAMB16
699
    for ( i = 0; i < (1<<9); i = i + 1 ) begin
700
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.ramb16_s36_s36.mem[i] = 32'h0000_0000;
701
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.ramb16_s36_s36.mem[i] = 32'h0000_0000;
702
    end
703
`elsif OR1200_ALTERA_LPM
704
`ifndef OR1200_ALTERA_LPM_XXX
705
    $display("Definition OR1200_ALTERA_LPM in or1200_defines.v does not enable ALTERA memory for neither DUAL nor TWO port RFRAM");
706
    $display("It uses GENERIC memory instead.");
707
    $display("Add '`define OR1200_ALTERA_LPM_XXX' under '`define OR1200_ALTERA_LPM' on or1200_defines.v to use ALTERA memory.");
708
`endif
709
`ifdef OR1200_ALTERA_LPM_XXX
710
    $display("...Using ALTERA memory for DUALPORT RFRAM!");
711
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
712
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.altqpram_component.mem[i] = 32'h0000_0000;
713
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.altqpram_component.mem[i] = 32'h0000_0000;
714
    end
715
`else
716
    $display("...Using GENERIC memory!");
717
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
718
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
719
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
720
    end
721
`endif
722
`elsif OR1200_XILINX_RAM32X1D
723
`ifdef OR1200_USE_RAM16X1D_FOR_RAM32X1D
724
    for ( i = 0; i < (1<<4); i = i + 1 ) begin
725
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
726
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
727
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
728
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
729
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
730
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
731
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
732
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
733
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
734
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
735
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
736
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
737
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
738
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
739
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
740
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
741
 
742
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
743
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
744
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
745
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
746
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
747
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
748
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
749
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
750
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
751
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
752
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
753
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
754
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
755
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
756
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
757
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
758
 
759
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
760
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
761
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
762
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
763
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
764
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
765
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
766
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
767
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
768
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
769
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
770
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
771
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
772
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
773
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
774
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
775
 
776
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
777
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
778
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
779
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
780
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
781
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
782
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
783
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
784
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
785
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
786
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
787
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
788
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
789
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
790
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
791
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
792
 
793
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_0.mem[i] = 1'b0;
794
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_1.mem[i] = 1'b0;
795
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_2.mem[i] = 1'b0;
796
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_3.mem[i] = 1'b0;
797
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_4.mem[i] = 1'b0;
798
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_5.mem[i] = 1'b0;
799
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_6.mem[i] = 1'b0;
800
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0_7.mem[i] = 1'b0;
801
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_0.mem[i] = 1'b0;
802
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_1.mem[i] = 1'b0;
803
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_2.mem[i] = 1'b0;
804
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_3.mem[i] = 1'b0;
805
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_4.mem[i] = 1'b0;
806
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_5.mem[i] = 1'b0;
807
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_6.mem[i] = 1'b0;
808
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1_7.mem[i] = 1'b0;
809
 
810
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_0.mem[i] = 1'b0;
811
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_1.mem[i] = 1'b0;
812
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_2.mem[i] = 1'b0;
813
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_3.mem[i] = 1'b0;
814
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_4.mem[i] = 1'b0;
815
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_5.mem[i] = 1'b0;
816
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_6.mem[i] = 1'b0;
817
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0_7.mem[i] = 1'b0;
818
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_0.mem[i] = 1'b0;
819
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_1.mem[i] = 1'b0;
820
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_2.mem[i] = 1'b0;
821
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_3.mem[i] = 1'b0;
822
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_4.mem[i] = 1'b0;
823
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_5.mem[i] = 1'b0;
824
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_6.mem[i] = 1'b0;
825
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1_7.mem[i] = 1'b0;
826
 
827
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_0.mem[i] = 1'b0;
828
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_1.mem[i] = 1'b0;
829
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_2.mem[i] = 1'b0;
830
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_3.mem[i] = 1'b0;
831
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_4.mem[i] = 1'b0;
832
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_5.mem[i] = 1'b0;
833
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_6.mem[i] = 1'b0;
834
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0_7.mem[i] = 1'b0;
835
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_0.mem[i] = 1'b0;
836
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_1.mem[i] = 1'b0;
837
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_2.mem[i] = 1'b0;
838
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_3.mem[i] = 1'b0;
839
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_4.mem[i] = 1'b0;
840
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_5.mem[i] = 1'b0;
841
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_6.mem[i] = 1'b0;
842
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1_7.mem[i] = 1'b0;
843
 
844
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_0.mem[i] = 1'b0;
845
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_1.mem[i] = 1'b0;
846
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_2.mem[i] = 1'b0;
847
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_3.mem[i] = 1'b0;
848
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_4.mem[i] = 1'b0;
849
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_5.mem[i] = 1'b0;
850
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_6.mem[i] = 1'b0;
851
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0_7.mem[i] = 1'b0;
852
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_0.mem[i] = 1'b0;
853
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_1.mem[i] = 1'b0;
854
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_2.mem[i] = 1'b0;
855
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_3.mem[i] = 1'b0;
856
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_4.mem[i] = 1'b0;
857
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_5.mem[i] = 1'b0;
858
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_6.mem[i] = 1'b0;
859
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1_7.mem[i] = 1'b0;
860
    end
861
`else
862
    for ( i = 0; i < (1<<4); i = i + 1 ) begin
863
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
864
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
865
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
866
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
867
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
868
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
869
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
870
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
871
 
872
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
873
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
874
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
875
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
876
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
877
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
878
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
879
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
880
 
881
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
882
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
883
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
884
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
885
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
886
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
887
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
888
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
889
 
890
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
891
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
892
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
893
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
894
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
895
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
896
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
897
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
898
 
899
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_0.mem[i] = 1'b0;
900
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_1.mem[i] = 1'b0;
901
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_2.mem[i] = 1'b0;
902
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_3.mem[i] = 1'b0;
903
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_4.mem[i] = 1'b0;
904
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_5.mem[i] = 1'b0;
905
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_6.mem[i] = 1'b0;
906
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_0.ram32x1d_7.mem[i] = 1'b0;
907
 
908
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_0.mem[i] = 1'b0;
909
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_1.mem[i] = 1'b0;
910
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_2.mem[i] = 1'b0;
911
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_3.mem[i] = 1'b0;
912
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_4.mem[i] = 1'b0;
913
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_5.mem[i] = 1'b0;
914
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_6.mem[i] = 1'b0;
915
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_1.ram32x1d_7.mem[i] = 1'b0;
916
 
917
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_0.mem[i] = 1'b0;
918
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_1.mem[i] = 1'b0;
919
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_2.mem[i] = 1'b0;
920
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_3.mem[i] = 1'b0;
921
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_4.mem[i] = 1'b0;
922
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_5.mem[i] = 1'b0;
923
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_6.mem[i] = 1'b0;
924
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_2.ram32x1d_7.mem[i] = 1'b0;
925
 
926
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_0.mem[i] = 1'b0;
927
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_1.mem[i] = 1'b0;
928
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_2.mem[i] = 1'b0;
929
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_3.mem[i] = 1'b0;
930
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_4.mem[i] = 1'b0;
931
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_5.mem[i] = 1'b0;
932
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_6.mem[i] = 1'b0;
933
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.xcv_ram32x8d_3.ram32x1d_7.mem[i] = 1'b0;
934
    end
935
`endif
936
`else
937
    for ( i = 0; i < (1<<5); i = i + 1 ) begin
938
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_a.mem[i] = 32'h0000_0000;
939
        minsoc_top_0.or1200_top.or1200_cpu.or1200_rf.rf_b.mem[i] = 32'h0000_0000;
940
    end
941
`endif
942
`endif
943
    end
944
endtask
945
 
946
endmodule
947
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.