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[/] [minsoc/] [trunk/] [bench/] [verilog/] [sim_lib/] [fpga_memory_primitives.v] - Blame information for rev 27

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1 10 rfajardo
 
2
//
3
//ALTERA_LPM
4
//
5
module lpm_ram_dq (
6
    address,
7
    inclock,
8
    outclock,
9
    data,
10
    we,
11
    q
12
);
13
 
14
parameter lpm_width = 8;
15
parameter lpm_widthad = 11;
16 27 rfajardo
parameter lpm_indata = "REGISTERED";            //This 4 parameters are included only to avoid warnings
17
parameter lpm_address_control = "REGISTERED";   //they are not accessed inside the module. OR1200 uses this 
18
parameter lpm_outdata = "UNREGISTERED";         //configuration set on all its instantiations, so this is fine.
19
parameter lpm_hint = "USE_EAB=ON";              //It may not be fine, if you are adding this library to your 
20
                                                //own system, which uses this module with another configuration.
21 10 rfajardo
localparam dw = lpm_width;
22
localparam aw = lpm_widthad;
23
 
24
input [aw-1:0] address;
25
input inclock;
26
input outclock;
27
input [dw-1:0] data;
28
input we;
29
output [dw-1:0] q;
30
 
31
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
32
reg     [aw-1:0] addr_reg;               // RAM address register
33
 
34
//
35
// Data output drivers
36
//
37 27 rfajardo
assign q = mem[addr_reg];
38 10 rfajardo
 
39
//
40
// RAM address register
41
//
42
always @(posedge inclock)
43
    addr_reg <= #1 address;
44
 
45
//
46
// RAM write
47
//
48
always @(posedge inclock)
49
        if (we)
50
                mem[address] <= #1 data;
51
 
52
endmodule
53
 
54
module altqpram (
55
        wraddress_a,
56
        inclocken_a,
57
        wraddress_b,
58
        wren_a,
59
        inclocken_b,
60
        wren_b,
61
        inaclr_a,
62
        inaclr_b,
63
        inclock_a,
64
        inclock_b,
65
        data_a,
66
        data_b,
67
        q_a,
68
        q_b
69
);
70
 
71
parameter width_write_a = 8;
72
parameter widthad_write_a = 11;
73
parameter width_write_b = 8;
74
parameter widthad_write_b = 11;
75
 
76
localparam dw = width_write_a;
77
localparam aw = widthad_write_a;
78
 
79
input inclock_a, inaclr_a, inclocken_a, wren_a, inclock_b, inaclr_b, inclocken_b, wren_b;
80
input [dw-1:0] data_a, data_b;
81
output [dw-1:0] q_a, q_b;
82
input [aw-1:0] wraddress_a, wraddress_b;
83
 
84
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
85
reg     [aw-1:0] addr_reg_a;             // RAM address register
86
reg     [aw-1:0] addr_reg_b;             // RAM address register
87
 
88
//
89
// Data output drivers
90
//
91
assign q_a = mem[addr_reg_a][dw-1:0];
92
assign q_b = mem[addr_reg_b][dw-1:0];
93
 
94
//
95
// RAM address register
96
//
97
always @(posedge inclock_a or posedge inaclr_a)
98
    if ( inaclr_a == 1'b1 )
99
        addr_reg_a <= #1 {aw{1'b0}};
100
    else if ( inclocken_a )
101
        addr_reg_a <= #1 wraddress_a;
102
 
103
always @(posedge inclock_b or posedge inaclr_b)
104
    if ( inaclr_b == 1'b1 )
105
        addr_reg_b <= #1 {aw{1'b0}};
106
    else if ( inclocken_b )
107
        addr_reg_b <= #1 wraddress_b;
108
 
109
//
110
// RAM write
111
//
112
always @(posedge inclock_a)
113
        if (inclocken_a && wren_a)
114
                mem[wraddress_a] <= #1 data_a;
115
 
116
always @(posedge inclock_b)
117
        if (inclocken_b && wren_b)
118
                mem[wraddress_b] <= #1 data_b;
119
 
120
endmodule
121
//
122
// ~ALTERA_LPM
123
//
124
 
125
 
126
//
127
//XILINX_RAMB16
128
//
129
module RAMB16_S36_S36 (
130
    CLKA,
131
    SSRA,
132
    ADDRA,
133
    DIA,
134
    DIPA,
135
    ENA,
136
    WEA,
137
    DOA,
138
    DOPA,
139
 
140
    CLKB,
141
    SSRB,
142
    ADDRB,
143
    DIB,
144
    DIPB,
145
    ENB,
146
    WEB,
147
    DOB,
148
    DOPB
149
);
150
 
151
parameter dw = 32;
152
parameter dwp = 4;
153
parameter aw = 9;
154
 
155
input CLKA, SSRA, ENA, WEA, CLKB, SSRB, ENB, WEB;
156
input [dw-1:0] DIA, DIB;
157
output [dw-1:0] DOA, DOB;
158
input [dwp-1:0] DIPA, DIPB;
159
output [dwp-1:0] DOPA, DOPB;
160
input [aw-1:0] ADDRA, ADDRB;
161
 
162
reg     [dw+dwp-1:0]     mem [(1<<aw)-1:0];       // RAM content
163
reg     [aw-1:0] addr_reg_a;             // RAM address register
164
reg     [aw-1:0] addr_reg_b;             // RAM address register
165
 
166
//
167
// Data output drivers
168
//
169
assign DOA = mem[addr_reg_a][dw-1:0];
170
assign DOPA = mem[addr_reg_a][dwp+dw-1:dw];
171
assign DOB = mem[addr_reg_b][dw-1:0];
172
assign DOPB = mem[addr_reg_b][dwp+dw-1:dw];
173
 
174
//
175
// RAM address register
176
//
177
always @(posedge CLKA or posedge SSRA)
178
    if ( SSRA == 1'b1 )
179
        addr_reg_a <= #1 {aw{1'b0}};
180
    else if ( ENA )
181
        addr_reg_a <= #1 ADDRA;
182
 
183
always @(posedge CLKB or posedge SSRB)
184
    if ( SSRB == 1'b1 )
185
        addr_reg_b <= #1 {aw{1'b0}};
186
    else if ( ENB )
187
        addr_reg_b <= #1 ADDRB;
188
 
189
//
190
// RAM write
191
//
192
always @(posedge CLKA)
193
        if (ENA && WEA)
194
                mem[ADDRA] <= #1 { DIPA , DIA };
195
 
196
always @(posedge CLKB)
197
        if (ENB && WEB)
198
                mem[ADDRB] <= #1 { DIPB , DIB };
199
 
200
endmodule
201
 
202
 
203
module RAMB16_S9 (
204
    CLK,
205
    SSR,
206
    ADDR,
207
    DI,
208
    DIP,
209
    EN,
210
    WE,
211
    DO,
212
    DOP
213
);
214
 
215
parameter dw = 8;
216
parameter dwp = 1;
217
parameter aw = 11;
218
 
219
input CLK, SSR, EN, WE;
220
input [dw-1:0] DI;
221
output [dw-1:0] DO;
222
input [dwp-1:0] DIP;
223
output [dwp-1:0] DOP;
224
input [aw-1:0] ADDR;
225
 
226
reg     [dw+dwp-1:0]     mem [(1<<aw)-1:0];       // RAM content
227
reg     [aw-1:0] addr_reg;               // RAM address register
228
 
229
//
230
// Data output drivers
231
//
232
assign DO = mem[addr_reg][dw-1:0];
233
assign DOP = mem[addr_reg][dwp+dw-1:dw];
234
 
235
//
236
// RAM address register
237
//
238
always @(posedge CLK or posedge SSR)
239
    if ( SSR == 1'b1 )
240
        addr_reg <= #1 {aw{1'b0}};
241
    else if ( EN )
242
        addr_reg <= #1 ADDR;
243
 
244
//
245
// RAM write
246
//
247
always @(posedge CLK)
248
        if (EN && WE)
249
                mem[ADDR] <= #1 { DIP , DI };
250
 
251
endmodule
252
 
253
 
254
module RAMB16_S36 (
255
    CLK,
256
    SSR,
257
    ADDR,
258
    DI,
259
    DIP,
260
    EN,
261
    WE,
262
    DO,
263
    DOP
264
);
265
 
266
parameter dw = 32;
267
parameter dwp = 4;
268
parameter aw = 9;
269
 
270
input CLK, SSR, EN, WE;
271
input [dw-1:0] DI;
272
output [dw-1:0] DO;
273
input [dwp-1:0] DIP;
274
output [dwp-1:0] DOP;
275
input [aw-1:0] ADDR;
276
 
277
reg     [dw+dwp-1:0]     mem [(1<<aw)-1:0];       // RAM content
278
reg     [aw-1:0] addr_reg;               // RAM address register
279
 
280
//
281
// Data output drivers
282
//
283
assign DO = mem[addr_reg][dw-1:0];
284
assign DOP = mem[addr_reg][dwp+dw-1:dw];
285
 
286
//
287
// RAM address register
288
//
289
always @(posedge CLK or posedge SSR)
290
    if ( SSR == 1'b1 )
291
        addr_reg <= #1 {aw{1'b0}};
292
    else if ( EN )
293
        addr_reg <= #1 ADDR;
294
 
295
//
296
// RAM write
297
//
298
always @(posedge CLK)
299
        if (EN && WE)
300
                mem[ADDR] <= #1 { DIP , DI };
301
 
302
endmodule
303
 
304
 
305
module RAMB16_S18 (
306
    CLK,
307
    SSR,
308
    ADDR,
309
    DI,
310
    DIP,
311
    EN,
312
    WE,
313
    DO,
314
    DOP
315
);
316
 
317
parameter dw = 16;
318
parameter dwp = 2;
319
parameter aw = 10;
320
 
321
input CLK, SSR, EN, WE;
322
input [dw-1:0] DI;
323
output [dw-1:0] DO;
324
input [dwp-1:0] DIP;
325
output [dwp-1:0] DOP;
326
input [aw-1:0] ADDR;
327
 
328
reg     [dw+dwp-1:0]     mem [(1<<aw)-1:0];       // RAM content
329
reg     [aw-1:0] addr_reg;               // RAM address register
330
 
331
//
332
// Data output drivers
333
//
334
assign DO = mem[addr_reg][dw-1:0];
335
assign DOP = mem[addr_reg][dwp+dw-1:dw];
336
 
337
//
338
// RAM address register
339
//
340
always @(posedge CLK or posedge SSR)
341
    if ( SSR == 1'b1 )
342
        addr_reg <= #1 {aw{1'b0}};
343
    else if ( EN )
344
        addr_reg <= #1 ADDR;
345
 
346
//
347
// RAM write
348
//
349
always @(posedge CLK)
350
        if (EN && WE)
351
                mem[ADDR] <= #1 { DIP , DI };
352
 
353
endmodule
354
//
355
//~XILINX_RAMB16
356
//
357
 
358
 
359
//
360
//XILINX_RAMB4
361
//
362
module RAMB4_S16_S16 (
363
    CLKA,
364
    RSTA,
365
    ADDRA,
366
    DIA,
367
    ENA,
368
    WEA,
369
    DOA,
370
 
371
    CLKB,
372
    RSTB,
373
    ADDRB,
374
    DIB,
375
    ENB,
376
    WEB,
377
    DOB
378
);
379
 
380
parameter dw = 16;
381
parameter aw = 8;
382
 
383
input CLKA, RSTA, ENA, WEA, CLKB, RSTB, ENB, WEB;
384
input [dw-1:0] DIA, DIB;
385
output [dw-1:0] DOA, DOB;
386
input [aw-1:0] ADDRA, ADDRB;
387
 
388
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
389
reg     [aw-1:0] addr_reg_a;             // RAM address register
390
reg     [aw-1:0] addr_reg_b;             // RAM address register
391
 
392
//
393
// Data output drivers
394
//
395
assign DOA = mem[addr_reg_a][dw-1:0];
396
assign DOB = mem[addr_reg_b][dw-1:0];
397
 
398
//
399
// RAM address register
400
//
401
always @(posedge CLKA or posedge RSTA)
402
    if ( RSTA == 1'b1 )
403
        addr_reg_a <= #1 {aw{1'b0}};
404
    else if ( ENA )
405
        addr_reg_a <= #1 ADDRA;
406
 
407
always @(posedge CLKB or posedge RSTB)
408
    if ( RSTB == 1'b1 )
409
        addr_reg_b <= #1 {aw{1'b0}};
410
    else if ( ENB )
411
        addr_reg_b <= #1 ADDRB;
412
 
413
//
414
// RAM write
415
//
416
always @(posedge CLKA)
417
        if (ENA && WEA)
418
                mem[ADDRA] <= #1 DIA;
419
 
420
always @(posedge CLKB)
421
        if (ENB && WEB)
422
                mem[ADDRB] <= #1 DIB;
423
 
424
endmodule
425
 
426
module RAMB4_S4 (
427
    CLK,
428
    RST,
429
    ADDR,
430
    DI,
431
    EN,
432
    WE,
433
    DO,
434
);
435
 
436
parameter dw = 4;
437
parameter aw = 10;
438
 
439
input CLK, RST, EN, WE;
440
input [dw-1:0] DI;
441
output [dw-1:0] DO;
442
input [aw-1:0] ADDR;
443
 
444
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
445
reg     [aw-1:0] addr_reg;               // RAM address register
446
 
447
//
448
// Data output drivers
449
//
450
assign DO = mem[addr_reg][dw-1:0];
451
 
452
//
453
// RAM address register
454
//
455
always @(posedge CLK or posedge RST)
456
    if ( RST == 1'b1 )
457
        addr_reg <= #1 {aw{1'b0}};
458
    else if ( EN )
459
        addr_reg <= #1 ADDR;
460
 
461
//
462
// RAM write
463
//
464
always @(posedge CLK)
465
        if (EN && WE)
466
                mem[ADDR] <= #1 DI;
467
 
468
endmodule
469
 
470
module RAMB4_S16 (
471
    CLK,
472
    RST,
473
    ADDR,
474
    DI,
475
    EN,
476
    WE,
477
    DO
478
);
479
 
480
parameter dw = 16;
481
parameter aw = 8;
482
 
483
input CLK, RST, EN, WE;
484
input [dw-1:0] DI;
485
output [dw-1:0] DO;
486
input [aw-1:0] ADDR;
487
 
488
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
489
reg     [aw-1:0] addr_reg;               // RAM address register
490
 
491
//
492
// Data output drivers
493
//
494
assign DO = mem[addr_reg][dw-1:0];
495
 
496
//
497
// RAM address register
498
//
499
always @(posedge CLK or posedge RST)
500
    if ( RST == 1'b1 )
501
        addr_reg <= #1 {aw{1'b0}};
502
    else if ( EN )
503
        addr_reg <= #1 ADDR;
504
 
505
//
506
// RAM write
507
//
508
always @(posedge CLK)
509
        if (EN && WE)
510
                mem[ADDR] <= #1 DI;
511
 
512
endmodule
513
 
514
module RAMB4_S2 (
515
    CLK,
516
    RST,
517
    ADDR,
518
    DI,
519
    EN,
520
    WE,
521
    DO,
522
);
523
 
524
parameter dw = 2;
525
parameter aw = 11;
526
 
527
input CLK, RST, EN, WE;
528
input [dw-1:0] DI;
529
output [dw-1:0] DO;
530
input [aw-1:0] ADDR;
531
 
532
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
533
reg     [aw-1:0] addr_reg;               // RAM address register
534
 
535
//
536
// Data output drivers
537
//
538
assign DO = mem[addr_reg][dw-1:0];
539
 
540
//
541
// RAM address register
542
//
543
always @(posedge CLK or posedge RST)
544
    if ( RST == 1'b1 )
545
        addr_reg <= #1 {aw{1'b0}};
546
    else if ( EN )
547
        addr_reg <= #1 ADDR;
548
 
549
//
550
// RAM write
551
//
552
always @(posedge CLK)
553
        if (EN && WE)
554
                mem[ADDR] <= #1 DI;
555
 
556
endmodule
557
 
558
module RAMB4_S8 (
559
    CLK,
560
    RST,
561
    ADDR,
562
    DI,
563
    EN,
564
    WE,
565
    DO,
566
);
567
 
568
parameter dw = 8;
569
parameter aw = 9;
570
 
571
input CLK, RST, EN, WE;
572
input [dw-1:0] DI;
573
output [dw-1:0] DO;
574
input [aw-1:0] ADDR;
575
 
576
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
577
reg     [aw-1:0] addr_reg;               // RAM address register
578
 
579
//
580
// Data output drivers
581
//
582
assign DO = mem[addr_reg][dw-1:0];
583
 
584
//
585
// RAM address register
586
//
587
always @(posedge CLK or posedge RST)
588
    if ( RST == 1'b1 )
589
        addr_reg <= #1 {aw{1'b0}};
590
    else if ( EN )
591
        addr_reg <= #1 ADDR;
592
 
593
//
594
// RAM write
595
//
596
always @(posedge CLK)
597
        if (EN && WE)
598
                mem[ADDR] <= #1 DI;
599
 
600
endmodule
601
//
602
// ~XILINX_RAMB4
603
//
604
 
605
 
606
//
607
// XILINX_RAM32X1D
608
//
609
module RAM32X1D (
610
    DPO,
611
    SPO,
612
    A0,
613
    A1,
614
    A2,
615
    A3,
616
    A4,
617
    D,
618
    DPRA0,
619
    DPRA1,
620
    DPRA2,
621
    DPRA3,
622
    DPRA4,
623
    WCLK,
624
    WE
625
);
626
 
627
parameter dw = 1;
628
parameter aw = 5;
629
 
630
output DPO, SPO;
631
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4;
632
input A0, A1, A2, A3, A4;
633
input D;
634
input WCLK;
635
input WE;
636
 
637
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
638
 
639
//
640
// Data output drivers
641
//
642
assign DPO = mem[{DPRA4 , DPRA3 , DPRA2 , DPRA1 , DPRA0}][dw-1:0];
643
assign SPO = mem[{A4 , A3 , A2 , A1 , A0}][dw-1:0];
644
 
645
//
646
// RAM write
647
//
648
always @(posedge WCLK)
649
        if (WE)
650
                mem[{A4 , A3 , A2 , A1 , A0}] <= #1 D;
651
 
652
endmodule
653
//
654 17 rfajardo
// ~XILINX_RAM32X1D
655 10 rfajardo
//
656
 
657
 
658
//
659
// USE_RAM16X1D_FOR_RAM32X1D
660
//
661
module RAM16X1D (
662
    DPO,
663
    SPO,
664
    A0,
665
    A1,
666
    A2,
667
    A3,
668
    D,
669
    DPRA0,
670
    DPRA1,
671
    DPRA2,
672
    DPRA3,
673
    WCLK,
674
    WE
675
);
676
 
677
parameter dw = 1;
678
parameter aw = 4;
679
 
680
output DPO, SPO;
681
input DPRA0, DPRA1, DPRA2, DPRA3;
682
input A0, A1, A2, A3;
683
input D;
684
input WCLK;
685
input WE;
686
 
687
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
688
 
689
//
690
// Data output drivers
691
//
692
assign DPO = mem[{DPRA3 , DPRA2 , DPRA1 , DPRA0}][dw-1:0];
693
assign SPO = mem[{A3 , A2 , A1 , A0}][dw-1:0];
694
 
695
//
696
// RAM write
697
//
698
always @(posedge WCLK)
699
        if (WE)
700
                mem[{A3 , A2 , A1 , A0}] <= #1 D;
701
 
702
endmodule
703
//
704 17 rfajardo
// ~USE_RAM16X1D_FOR_RAM32X1D
705 10 rfajardo
//

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