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1 10 rfajardo
 
2
//
3
//ALTERA_LPM
4
//
5
module lpm_ram_dq (
6
    address,
7
    inclock,
8
    outclock,
9
    data,
10
    we,
11
    q
12
);
13
 
14
parameter lpm_width = 8;
15
parameter lpm_widthad = 11;
16
 
17
localparam dw = lpm_width;
18
localparam aw = lpm_widthad;
19
 
20
input [aw-1:0] address;
21
input inclock;
22
input outclock;
23
input [dw-1:0] data;
24
input we;
25
output [dw-1:0] q;
26
 
27
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
28
reg     [aw-1:0] addr_reg;               // RAM address register
29
 
30
//
31
// Data output drivers
32
//
33
assign doq = mem[addr_reg];
34
 
35
//
36
// RAM address register
37
//
38
always @(posedge inclock)
39
    addr_reg <= #1 address;
40
 
41
//
42
// RAM write
43
//
44
always @(posedge inclock)
45
        if (we)
46
                mem[address] <= #1 data;
47
 
48
endmodule
49
 
50
module altqpram (
51
        wraddress_a,
52
        inclocken_a,
53
        wraddress_b,
54
        wren_a,
55
        inclocken_b,
56
        wren_b,
57
        inaclr_a,
58
        inaclr_b,
59
        inclock_a,
60
        inclock_b,
61
        data_a,
62
        data_b,
63
        q_a,
64
        q_b
65
);
66
 
67
parameter width_write_a = 8;
68
parameter widthad_write_a = 11;
69
parameter width_write_b = 8;
70
parameter widthad_write_b = 11;
71
 
72
localparam dw = width_write_a;
73
localparam aw = widthad_write_a;
74
 
75
input inclock_a, inaclr_a, inclocken_a, wren_a, inclock_b, inaclr_b, inclocken_b, wren_b;
76
input [dw-1:0] data_a, data_b;
77
output [dw-1:0] q_a, q_b;
78
input [aw-1:0] wraddress_a, wraddress_b;
79
 
80
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
81
reg     [aw-1:0] addr_reg_a;             // RAM address register
82
reg     [aw-1:0] addr_reg_b;             // RAM address register
83
 
84
//
85
// Data output drivers
86
//
87
assign q_a = mem[addr_reg_a][dw-1:0];
88
assign q_b = mem[addr_reg_b][dw-1:0];
89
 
90
//
91
// RAM address register
92
//
93
always @(posedge inclock_a or posedge inaclr_a)
94
    if ( inaclr_a == 1'b1 )
95
        addr_reg_a <= #1 {aw{1'b0}};
96
    else if ( inclocken_a )
97
        addr_reg_a <= #1 wraddress_a;
98
 
99
always @(posedge inclock_b or posedge inaclr_b)
100
    if ( inaclr_b == 1'b1 )
101
        addr_reg_b <= #1 {aw{1'b0}};
102
    else if ( inclocken_b )
103
        addr_reg_b <= #1 wraddress_b;
104
 
105
//
106
// RAM write
107
//
108
always @(posedge inclock_a)
109
        if (inclocken_a && wren_a)
110
                mem[wraddress_a] <= #1 data_a;
111
 
112
always @(posedge inclock_b)
113
        if (inclocken_b && wren_b)
114
                mem[wraddress_b] <= #1 data_b;
115
 
116
endmodule
117
//
118
// ~ALTERA_LPM
119
//
120
 
121
 
122
//
123
//XILINX_RAMB16
124
//
125
module RAMB16_S36_S36 (
126
    CLKA,
127
    SSRA,
128
    ADDRA,
129
    DIA,
130
    DIPA,
131
    ENA,
132
    WEA,
133
    DOA,
134
    DOPA,
135
 
136
    CLKB,
137
    SSRB,
138
    ADDRB,
139
    DIB,
140
    DIPB,
141
    ENB,
142
    WEB,
143
    DOB,
144
    DOPB
145
);
146
 
147
parameter dw = 32;
148
parameter dwp = 4;
149
parameter aw = 9;
150
 
151
input CLKA, SSRA, ENA, WEA, CLKB, SSRB, ENB, WEB;
152
input [dw-1:0] DIA, DIB;
153
output [dw-1:0] DOA, DOB;
154
input [dwp-1:0] DIPA, DIPB;
155
output [dwp-1:0] DOPA, DOPB;
156
input [aw-1:0] ADDRA, ADDRB;
157
 
158
reg     [dw+dwp-1:0]     mem [(1<<aw)-1:0];       // RAM content
159
reg     [aw-1:0] addr_reg_a;             // RAM address register
160
reg     [aw-1:0] addr_reg_b;             // RAM address register
161
 
162
//
163
// Data output drivers
164
//
165
assign DOA = mem[addr_reg_a][dw-1:0];
166
assign DOPA = mem[addr_reg_a][dwp+dw-1:dw];
167
assign DOB = mem[addr_reg_b][dw-1:0];
168
assign DOPB = mem[addr_reg_b][dwp+dw-1:dw];
169
 
170
//
171
// RAM address register
172
//
173
always @(posedge CLKA or posedge SSRA)
174
    if ( SSRA == 1'b1 )
175
        addr_reg_a <= #1 {aw{1'b0}};
176
    else if ( ENA )
177
        addr_reg_a <= #1 ADDRA;
178
 
179
always @(posedge CLKB or posedge SSRB)
180
    if ( SSRB == 1'b1 )
181
        addr_reg_b <= #1 {aw{1'b0}};
182
    else if ( ENB )
183
        addr_reg_b <= #1 ADDRB;
184
 
185
//
186
// RAM write
187
//
188
always @(posedge CLKA)
189
        if (ENA && WEA)
190
                mem[ADDRA] <= #1 { DIPA , DIA };
191
 
192
always @(posedge CLKB)
193
        if (ENB && WEB)
194
                mem[ADDRB] <= #1 { DIPB , DIB };
195
 
196
endmodule
197
 
198
 
199
module RAMB16_S9 (
200
    CLK,
201
    SSR,
202
    ADDR,
203
    DI,
204
    DIP,
205
    EN,
206
    WE,
207
    DO,
208
    DOP
209
);
210
 
211
parameter dw = 8;
212
parameter dwp = 1;
213
parameter aw = 11;
214
 
215
input CLK, SSR, EN, WE;
216
input [dw-1:0] DI;
217
output [dw-1:0] DO;
218
input [dwp-1:0] DIP;
219
output [dwp-1:0] DOP;
220
input [aw-1:0] ADDR;
221
 
222
reg     [dw+dwp-1:0]     mem [(1<<aw)-1:0];       // RAM content
223
reg     [aw-1:0] addr_reg;               // RAM address register
224
 
225
//
226
// Data output drivers
227
//
228
assign DO = mem[addr_reg][dw-1:0];
229
assign DOP = mem[addr_reg][dwp+dw-1:dw];
230
 
231
//
232
// RAM address register
233
//
234
always @(posedge CLK or posedge SSR)
235
    if ( SSR == 1'b1 )
236
        addr_reg <= #1 {aw{1'b0}};
237
    else if ( EN )
238
        addr_reg <= #1 ADDR;
239
 
240
//
241
// RAM write
242
//
243
always @(posedge CLK)
244
        if (EN && WE)
245
                mem[ADDR] <= #1 { DIP , DI };
246
 
247
endmodule
248
 
249
 
250
module RAMB16_S36 (
251
    CLK,
252
    SSR,
253
    ADDR,
254
    DI,
255
    DIP,
256
    EN,
257
    WE,
258
    DO,
259
    DOP
260
);
261
 
262
parameter dw = 32;
263
parameter dwp = 4;
264
parameter aw = 9;
265
 
266
input CLK, SSR, EN, WE;
267
input [dw-1:0] DI;
268
output [dw-1:0] DO;
269
input [dwp-1:0] DIP;
270
output [dwp-1:0] DOP;
271
input [aw-1:0] ADDR;
272
 
273
reg     [dw+dwp-1:0]     mem [(1<<aw)-1:0];       // RAM content
274
reg     [aw-1:0] addr_reg;               // RAM address register
275
 
276
//
277
// Data output drivers
278
//
279
assign DO = mem[addr_reg][dw-1:0];
280
assign DOP = mem[addr_reg][dwp+dw-1:dw];
281
 
282
//
283
// RAM address register
284
//
285
always @(posedge CLK or posedge SSR)
286
    if ( SSR == 1'b1 )
287
        addr_reg <= #1 {aw{1'b0}};
288
    else if ( EN )
289
        addr_reg <= #1 ADDR;
290
 
291
//
292
// RAM write
293
//
294
always @(posedge CLK)
295
        if (EN && WE)
296
                mem[ADDR] <= #1 { DIP , DI };
297
 
298
endmodule
299
 
300
 
301
module RAMB16_S18 (
302
    CLK,
303
    SSR,
304
    ADDR,
305
    DI,
306
    DIP,
307
    EN,
308
    WE,
309
    DO,
310
    DOP
311
);
312
 
313
parameter dw = 16;
314
parameter dwp = 2;
315
parameter aw = 10;
316
 
317
input CLK, SSR, EN, WE;
318
input [dw-1:0] DI;
319
output [dw-1:0] DO;
320
input [dwp-1:0] DIP;
321
output [dwp-1:0] DOP;
322
input [aw-1:0] ADDR;
323
 
324
reg     [dw+dwp-1:0]     mem [(1<<aw)-1:0];       // RAM content
325
reg     [aw-1:0] addr_reg;               // RAM address register
326
 
327
//
328
// Data output drivers
329
//
330
assign DO = mem[addr_reg][dw-1:0];
331
assign DOP = mem[addr_reg][dwp+dw-1:dw];
332
 
333
//
334
// RAM address register
335
//
336
always @(posedge CLK or posedge SSR)
337
    if ( SSR == 1'b1 )
338
        addr_reg <= #1 {aw{1'b0}};
339
    else if ( EN )
340
        addr_reg <= #1 ADDR;
341
 
342
//
343
// RAM write
344
//
345
always @(posedge CLK)
346
        if (EN && WE)
347
                mem[ADDR] <= #1 { DIP , DI };
348
 
349
endmodule
350
//
351
//~XILINX_RAMB16
352
//
353
 
354
 
355
//
356
//XILINX_RAMB4
357
//
358
module RAMB4_S16_S16 (
359
    CLKA,
360
    RSTA,
361
    ADDRA,
362
    DIA,
363
    ENA,
364
    WEA,
365
    DOA,
366
 
367
    CLKB,
368
    RSTB,
369
    ADDRB,
370
    DIB,
371
    ENB,
372
    WEB,
373
    DOB
374
);
375
 
376
parameter dw = 16;
377
parameter aw = 8;
378
 
379
input CLKA, RSTA, ENA, WEA, CLKB, RSTB, ENB, WEB;
380
input [dw-1:0] DIA, DIB;
381
output [dw-1:0] DOA, DOB;
382
input [aw-1:0] ADDRA, ADDRB;
383
 
384
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
385
reg     [aw-1:0] addr_reg_a;             // RAM address register
386
reg     [aw-1:0] addr_reg_b;             // RAM address register
387
 
388
//
389
// Data output drivers
390
//
391
assign DOA = mem[addr_reg_a][dw-1:0];
392
assign DOB = mem[addr_reg_b][dw-1:0];
393
 
394
//
395
// RAM address register
396
//
397
always @(posedge CLKA or posedge RSTA)
398
    if ( RSTA == 1'b1 )
399
        addr_reg_a <= #1 {aw{1'b0}};
400
    else if ( ENA )
401
        addr_reg_a <= #1 ADDRA;
402
 
403
always @(posedge CLKB or posedge RSTB)
404
    if ( RSTB == 1'b1 )
405
        addr_reg_b <= #1 {aw{1'b0}};
406
    else if ( ENB )
407
        addr_reg_b <= #1 ADDRB;
408
 
409
//
410
// RAM write
411
//
412
always @(posedge CLKA)
413
        if (ENA && WEA)
414
                mem[ADDRA] <= #1 DIA;
415
 
416
always @(posedge CLKB)
417
        if (ENB && WEB)
418
                mem[ADDRB] <= #1 DIB;
419
 
420
endmodule
421
 
422
module RAMB4_S4 (
423
    CLK,
424
    RST,
425
    ADDR,
426
    DI,
427
    EN,
428
    WE,
429
    DO,
430
);
431
 
432
parameter dw = 4;
433
parameter aw = 10;
434
 
435
input CLK, RST, EN, WE;
436
input [dw-1:0] DI;
437
output [dw-1:0] DO;
438
input [aw-1:0] ADDR;
439
 
440
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
441
reg     [aw-1:0] addr_reg;               // RAM address register
442
 
443
//
444
// Data output drivers
445
//
446
assign DO = mem[addr_reg][dw-1:0];
447
 
448
//
449
// RAM address register
450
//
451
always @(posedge CLK or posedge RST)
452
    if ( RST == 1'b1 )
453
        addr_reg <= #1 {aw{1'b0}};
454
    else if ( EN )
455
        addr_reg <= #1 ADDR;
456
 
457
//
458
// RAM write
459
//
460
always @(posedge CLK)
461
        if (EN && WE)
462
                mem[ADDR] <= #1 DI;
463
 
464
endmodule
465
 
466
module RAMB4_S16 (
467
    CLK,
468
    RST,
469
    ADDR,
470
    DI,
471
    EN,
472
    WE,
473
    DO
474
);
475
 
476
parameter dw = 16;
477
parameter aw = 8;
478
 
479
input CLK, RST, EN, WE;
480
input [dw-1:0] DI;
481
output [dw-1:0] DO;
482
input [aw-1:0] ADDR;
483
 
484
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
485
reg     [aw-1:0] addr_reg;               // RAM address register
486
 
487
//
488
// Data output drivers
489
//
490
assign DO = mem[addr_reg][dw-1:0];
491
 
492
//
493
// RAM address register
494
//
495
always @(posedge CLK or posedge RST)
496
    if ( RST == 1'b1 )
497
        addr_reg <= #1 {aw{1'b0}};
498
    else if ( EN )
499
        addr_reg <= #1 ADDR;
500
 
501
//
502
// RAM write
503
//
504
always @(posedge CLK)
505
        if (EN && WE)
506
                mem[ADDR] <= #1 DI;
507
 
508
endmodule
509
 
510
module RAMB4_S2 (
511
    CLK,
512
    RST,
513
    ADDR,
514
    DI,
515
    EN,
516
    WE,
517
    DO,
518
);
519
 
520
parameter dw = 2;
521
parameter aw = 11;
522
 
523
input CLK, RST, EN, WE;
524
input [dw-1:0] DI;
525
output [dw-1:0] DO;
526
input [aw-1:0] ADDR;
527
 
528
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
529
reg     [aw-1:0] addr_reg;               // RAM address register
530
 
531
//
532
// Data output drivers
533
//
534
assign DO = mem[addr_reg][dw-1:0];
535
 
536
//
537
// RAM address register
538
//
539
always @(posedge CLK or posedge RST)
540
    if ( RST == 1'b1 )
541
        addr_reg <= #1 {aw{1'b0}};
542
    else if ( EN )
543
        addr_reg <= #1 ADDR;
544
 
545
//
546
// RAM write
547
//
548
always @(posedge CLK)
549
        if (EN && WE)
550
                mem[ADDR] <= #1 DI;
551
 
552
endmodule
553
 
554
module RAMB4_S8 (
555
    CLK,
556
    RST,
557
    ADDR,
558
    DI,
559
    EN,
560
    WE,
561
    DO,
562
);
563
 
564
parameter dw = 8;
565
parameter aw = 9;
566
 
567
input CLK, RST, EN, WE;
568
input [dw-1:0] DI;
569
output [dw-1:0] DO;
570
input [aw-1:0] ADDR;
571
 
572
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
573
reg     [aw-1:0] addr_reg;               // RAM address register
574
 
575
//
576
// Data output drivers
577
//
578
assign DO = mem[addr_reg][dw-1:0];
579
 
580
//
581
// RAM address register
582
//
583
always @(posedge CLK or posedge RST)
584
    if ( RST == 1'b1 )
585
        addr_reg <= #1 {aw{1'b0}};
586
    else if ( EN )
587
        addr_reg <= #1 ADDR;
588
 
589
//
590
// RAM write
591
//
592
always @(posedge CLK)
593
        if (EN && WE)
594
                mem[ADDR] <= #1 DI;
595
 
596
endmodule
597
//
598
// ~XILINX_RAMB4
599
//
600
 
601
 
602
//
603
// XILINX_RAM32X1D
604
//
605
module RAM32X1D (
606
    DPO,
607
    SPO,
608
    A0,
609
    A1,
610
    A2,
611
    A3,
612
    A4,
613
    D,
614
    DPRA0,
615
    DPRA1,
616
    DPRA2,
617
    DPRA3,
618
    DPRA4,
619
    WCLK,
620
    WE
621
);
622
 
623
parameter dw = 1;
624
parameter aw = 5;
625
 
626
output DPO, SPO;
627
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4;
628
input A0, A1, A2, A3, A4;
629
input D;
630
input WCLK;
631
input WE;
632
 
633
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
634
 
635
//
636
// Data output drivers
637
//
638
assign DPO = mem[{DPRA4 , DPRA3 , DPRA2 , DPRA1 , DPRA0}][dw-1:0];
639
assign SPO = mem[{A4 , A3 , A2 , A1 , A0}][dw-1:0];
640
 
641
//
642
// RAM write
643
//
644
always @(posedge WCLK)
645
        if (WE)
646
                mem[{A4 , A3 , A2 , A1 , A0}] <= #1 D;
647
 
648
endmodule
649
//
650 17 rfajardo
// ~XILINX_RAM32X1D
651 10 rfajardo
//
652
 
653
 
654
//
655
// USE_RAM16X1D_FOR_RAM32X1D
656
//
657
module RAM16X1D (
658
    DPO,
659
    SPO,
660
    A0,
661
    A1,
662
    A2,
663
    A3,
664
    D,
665
    DPRA0,
666
    DPRA1,
667
    DPRA2,
668
    DPRA3,
669
    WCLK,
670
    WE
671
);
672
 
673
parameter dw = 1;
674
parameter aw = 4;
675
 
676
output DPO, SPO;
677
input DPRA0, DPRA1, DPRA2, DPRA3;
678
input A0, A1, A2, A3;
679
input D;
680
input WCLK;
681
input WE;
682
 
683
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
684
 
685
//
686
// Data output drivers
687
//
688
assign DPO = mem[{DPRA3 , DPRA2 , DPRA1 , DPRA0}][dw-1:0];
689
assign SPO = mem[{A3 , A2 , A1 , A0}][dw-1:0];
690
 
691
//
692
// RAM write
693
//
694
always @(posedge WCLK)
695
        if (WE)
696
                mem[{A3 , A2 , A1 , A0}] <= #1 D;
697
 
698
endmodule
699
//
700 17 rfajardo
// ~USE_RAM16X1D_FOR_RAM32X1D
701 10 rfajardo
//

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