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[/] [minsoc/] [trunk/] [prj/] [Makefile] - Blame information for rev 141

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Line No. Rev Author Line
1 104 rfajardo
VERILOG_PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
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VHDL_PROJECTS = altera_virtual_jtag.prj
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4 104 rfajardo
PROJECTS = $(VERILOG_PROJECTS) $(VHDL_PROJECTS)
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SRC_DIR = src
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SCRIPTS_DIR = scripts
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SIMULATION_DIR = sim
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XILINX_DIR = xilinx
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ALTERA_DIR = altera
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SIM_VERILOG_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .verilog, $(basename $(VERILOG_PROJECTS))))
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SIM_VHDL_FILES = $(addprefix $(SIMULATION_DIR)/, $(addsuffix .vhdl, $(basename $(VHDL_PROJECTS))))
14 141 rfajardo
 
15 85 rfajardo
XILINX_PRJ_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .prj, $(basename $(PROJECTS))))
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XILINX_XST_FILES = $(addprefix $(XILINX_DIR)/, $(addsuffix .xst, $(basename $(PROJECTS))))
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18 141 rfajardo
ALTERA_VERILOG_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vprj, $(basename $(VERILOG_PROJECTS))))
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ALTERA_VHDL_PRJ_FILES = $(addprefix $(ALTERA_DIR)/, $(addsuffix .vhdprj, $(basename $(VHDL_PROJECTS))))
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21 141 rfajardo
all: $(SIMULATION_DIR)/minsoc_verilog.src $(SIMULATION_DIR)/minsoc_vhdl.src $(XILINX_PRJ_FILES) $(XILINX_XST_FILES) $(ALTERA_VERILOG_PRJ_FILES) $(ALTERA_VHDL_PRJ_FILES)
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23 85 rfajardo
clean:
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        rm -rf $(SIMULATION_DIR)/*.verilog $(SIMULATION_DIR)/*.vhdl $(SIMULATION_DIR)/*.src $(XILINX_DIR)/*.prj $(XILINX_DIR)/*.xst $(ALTERA_DIR)/*.vprj $(ALTERA_DIR)/*.vhdprj
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26 141 rfajardo
 
27 85 rfajardo
$(XILINX_DIR)/minsoc_top.xst: $(SRC_DIR)/minsoc_top.prj
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        bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ minsoc_top.prj minsoc_top topmodule
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$(XILINX_DIR)/minsoc_top.prj: $(SRC_DIR)/minsoc_top.prj
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        bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@ topmodule
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$(XILINX_DIR)/%.xst: $(SRC_DIR)/%.prj
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        bash $(SCRIPTS_DIR)/xilinxxst.sh $^ $@ $*.prj $*
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$(XILINX_DIR)/%.prj: $(SRC_DIR)/%.prj
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        bash $(SCRIPTS_DIR)/xilinxprj.sh $^ $@
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40 141 rfajardo
$(ALTERA_DIR)/%.vprj: $(SRC_DIR)/%.prj
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        bash $(SCRIPTS_DIR)/altvprj.sh $^ $@
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$(ALTERA_DIR)/%.vhdprj: $(SRC_DIR)/%.prj
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        bash $(SCRIPTS_DIR)/altvhdprj.sh $^ $@
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$(SIMULATION_DIR)/minsoc_verilog.src: $(SIM_VERILOG_FILES)
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        cat $(SIM_VERILOG_FILES) > $(SIMULATION_DIR)/minsoc_verilog.src
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50 104 rfajardo
$(SIMULATION_DIR)/minsoc_vhdl.src: $(SIM_VHDL_FILES)
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        cat $(SIM_VHDL_FILES) > $(SIMULATION_DIR)/minsoc_vhdl.src
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53 104 rfajardo
$(SIMULATION_DIR)/%.verilog: $(SRC_DIR)/%.prj
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        bash $(SCRIPTS_DIR)/simverilog.sh $^ $@
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$(SIMULATION_DIR)/%.vhdl: $(SRC_DIR)/%.prj
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        bash $(SCRIPTS_DIR)/simvhdl.sh $^ $@
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