Subversion Repositories minsoc

PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog

PROJECT_SRC=(adbg_crc32.v

adbg_defines.v

adbg_jsp_biu.v

adbg_jsp_module.v

adbg_or1k_biu.v

adbg_or1k_defines.v

adbg_or1k_module.v

adbg_or1k_status_reg.v

adbg_top.v

adbg_wb_biu.v

adbg_wb_defines.v

adbg_wb_module.v

bytefifo.v

syncflop.v

syncreg.v)