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[/] [minsoc/] [trunk/] [prj/] [src/] [altera_virtual_jtag.prj] - Blame information for rev 96

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Line No. Rev Author Line
1 96 javieralso
PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/altera_virtual_jtag/rtl/vhdl/
2
PROJECT_SRC=altera_virtual_jtag.vhd

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