OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj/] [src/] [blackboxes/] [or1200_top.v] - Blame information for rev 105

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 63 rfajardo
 
2
 
3
`include "or1200_defines.v"
4
 
5
module or1200_top(
6
        // System
7
        clk_i, rst_i, pic_ints_i, clmode_i,
8
 
9
        // Instruction WISHBONE INTERFACE
10
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
11
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
12
`ifdef OR1200_WB_CAB
13
        iwb_cab_o,
14
`endif
15
`ifdef OR1200_WB_B3
16
        iwb_cti_o, iwb_bte_o,
17
`endif
18
        // Data WISHBONE INTERFACE
19
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
20
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
21
`ifdef OR1200_WB_CAB
22
        dwb_cab_o,
23
`endif
24
`ifdef OR1200_WB_B3
25
        dwb_cti_o, dwb_bte_o,
26
`endif
27
 
28
        // External Debug Interface
29
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
30
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
31
 
32
`ifdef OR1200_BIST
33
        // RAM BIST
34
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
35
`endif
36
        // Power Management
37
        pm_cpustall_i,
38
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
39
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
40
 
41
,sig_tick
42
 
43
);
44
 
45
parameter dw = `OR1200_OPERAND_WIDTH;
46
parameter aw = `OR1200_OPERAND_WIDTH;
47
parameter ppic_ints = `OR1200_PIC_INTS;
48
 
49
//
50
// I/O
51
//
52
 
53
//
54
// System
55
//
56
input                   clk_i;
57
input                   rst_i;
58
input   [1:0]            clmode_i;       // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
59
input   [ppic_ints-1:0]  pic_ints_i;
60
 
61
//
62
// Instruction WISHBONE interface
63
//
64
input                   iwb_clk_i;      // clock input
65
input                   iwb_rst_i;      // reset input
66
input                   iwb_ack_i;      // normal termination
67
input                   iwb_err_i;      // termination w/ error
68
input                   iwb_rty_i;      // termination w/ retry
69
input   [dw-1:0] iwb_dat_i;      // input data bus
70
output                  iwb_cyc_o;      // cycle valid output
71
output  [aw-1:0] iwb_adr_o;      // address bus outputs
72
output                  iwb_stb_o;      // strobe output
73
output                  iwb_we_o;       // indicates write transfer
74
output  [3:0]            iwb_sel_o;      // byte select outputs
75
output  [dw-1:0] iwb_dat_o;      // output data bus
76
`ifdef OR1200_WB_CAB
77
output                  iwb_cab_o;      // indicates consecutive address burst
78
`endif
79
`ifdef OR1200_WB_B3
80
output  [2:0]            iwb_cti_o;      // cycle type identifier
81
output  [1:0]            iwb_bte_o;      // burst type extension
82
`endif
83
 
84
//
85
// Data WISHBONE interface
86
//
87
input                   dwb_clk_i;      // clock input
88
input                   dwb_rst_i;      // reset input
89
input                   dwb_ack_i;      // normal termination
90
input                   dwb_err_i;      // termination w/ error
91
input                   dwb_rty_i;      // termination w/ retry
92
input   [dw-1:0] dwb_dat_i;      // input data bus
93
output                  dwb_cyc_o;      // cycle valid output
94
output  [aw-1:0] dwb_adr_o;      // address bus outputs
95
output                  dwb_stb_o;      // strobe output
96
output                  dwb_we_o;       // indicates write transfer
97
output  [3:0]            dwb_sel_o;      // byte select outputs
98
output  [dw-1:0] dwb_dat_o;      // output data bus
99
`ifdef OR1200_WB_CAB
100
output                  dwb_cab_o;      // indicates consecutive address burst
101
`endif
102
`ifdef OR1200_WB_B3
103
output  [2:0]            dwb_cti_o;      // cycle type identifier
104
output  [1:0]            dwb_bte_o;      // burst type extension
105
`endif
106
 
107
//
108
// External Debug Interface
109
//
110
input                   dbg_stall_i;    // External Stall Input
111
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
112
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
113
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
114
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
115
output                  dbg_bp_o;       // Breakpoint Output
116
input                   dbg_stb_i;      // External Address/Data Strobe
117
input                   dbg_we_i;       // External Write Enable
118
input   [aw-1:0] dbg_adr_i;      // External Address Input
119
input   [dw-1:0] dbg_dat_i;      // External Data Input
120
output  [dw-1:0] dbg_dat_o;      // External Data Output
121
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
122
 
123
`ifdef OR1200_BIST
124
//
125
// RAM BIST
126
//
127
input mbist_si_i;
128
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
129
output mbist_so_o;
130
`endif
131
 
132
//
133
// Power Management
134
//
135
input                   pm_cpustall_i;
136
output  [3:0]            pm_clksd_o;
137
output                  pm_dc_gate_o;
138
output                  pm_ic_gate_o;
139
output                  pm_dmmu_gate_o;
140
output                  pm_immu_gate_o;
141
output                  pm_tt_gate_o;
142
output                  pm_cpu_gate_o;
143
output                  pm_wakeup_o;
144
output                  pm_lvolt_o;
145
 
146
//
147
// CPU and TT
148
//
149
output          sig_tick; // jb
150
 
151
 
152
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.