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[/] [minsoc/] [trunk/] [prj/] [src/] [minsoc_top.prj] - Blame information for rev 85

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Line No. Rev Author Line
1 85 rfajardo
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup)
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PROJECT_SRC=(minsoc_defines.v
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minsoc_bench_defines.v
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minsoc_bench.v
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minsoc_memory_model.v
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dbg_comm_vpi.v
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fpga_memory_primitives.v
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timescale.v
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minsoc_top.v
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spi_top.v
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spi_defines.v
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spi_shift.v
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spi_clgen.v
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OR1K_startup_generic.v
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minsoc_tc_top.v
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minsoc_onchip_ram.v
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minsoc_clock_manager.v
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minsoc_onchip_ram_top.v)

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