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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [interconnect_defines.v] - Blame information for rev 158

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Line No. Rev Author Line
1 158 rfajardo
//
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// Interrupts
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//
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`define APP_INT_RES1        1:0
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`define APP_INT_UART        2
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`define APP_INT_RES2        3
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`define APP_INT_ETH         4
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`define APP_INT_PS2         5
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`define APP_INT_JSP         6
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`define APP_INT_RES3        19:7
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//
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// Address map
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//
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`define APP_ADDR_DEC_W      8
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`define APP_ADDR_SRAM       `APP_ADDR_DEC_W'h00
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`define APP_ADDR_FLASH      `APP_ADDR_DEC_W'h04
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`define APP_ADDR_DECP_W     4
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`define APP_ADDR_PERIP      `APP_ADDR_DECP_W'h9
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`define APP_ADDR_SPI        `APP_ADDR_DEC_W'h97
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`define APP_ADDR_ETH        `APP_ADDR_DEC_W'h92
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`define APP_ADDR_AUDIO      `APP_ADDR_DEC_W'h9d
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`define APP_ADDR_UART       `APP_ADDR_DEC_W'h90
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`define APP_ADDR_PS2        `APP_ADDR_DEC_W'h94
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`define APP_ADDR_JSP        `APP_ADDR_DEC_W'h9e
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`define APP_ADDR_RES2       `APP_ADDR_DEC_W'h9f

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