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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_onchip_ram.v] - Blame information for rev 173

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/minsoc/               ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Raul Fajardo, rfajardo@gmail.com                      ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.gnu.org/licenses/lgpl.html                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
//
// Revision 2.1 2009/08/23 16:41:00   fajardo
// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY
// This actually models appropriately the behavior of the FPGA internal RAMs
//
// Revision 2.0 2009/09/10 11:30:00   fajardo
// Added tri-state buffering for altera output
// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY
//
// Revision 1.9 2009/08/18 15:15:00   fajardo
// Added tri-state buffering for xilinx and generic memory output
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "minsoc_defines.v"
 
module minsoc_onchip_ram(
`ifdef BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 8;
 
`ifdef BIST
//
// RAM BIST
//
input mbist_si_i;
input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Decide memory implementation for Xilinx FPGAs
//
`ifdef SPARTAN2
        `define MINSOC_XILINX_RAMB4
`elsif VIRTEX
        `define MINSOC_XILINX_RAMB4
`endif  // !SPARTAN2/VIRTEX
 
`ifdef SPARTAN3
        `define MINSOC_XILINX_RAMB16
`elsif SPARTAN3E
        `define MINSOC_XILINX_RAMB16
`elsif SPARTAN3A
        `define MINSOC_XILINX_RAMB16
`elsif VIRTEX2
        `define MINSOC_XILINX_RAMB16
`elsif VIRTEX4
        `define MINSOC_XILINX_RAMB16
`elsif VIRTEX5
        `define MINSOC_XILINX_RAMB16
`elsif SPARTAN6
        `define MINSOC_XILINX_RAMB16
`endif  // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5/SPARTAN6
 
 
//
// Internal wires and registers
//
 
`ifdef ARTISAN_SSP
`else
`ifdef VIRTUALSILICON_SSP
`else
`ifdef BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
 
`ifdef GENERIC_MEMORY
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
 
`elsif ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef BIST
art_hssp_2048x8_bist artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
`endif
`ifdef BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
 
`elsif AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
 
`elsif VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
 
`elsif VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef BIST
vs_hdsp_2048x8_bist vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
`endif
`ifdef BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
 
`elsif MINSOC_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// SPARTAN2/VIRTEX
//
 
wire    [dw-1:0] doq_internal;   // output data bus
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we),
        .DO(doq_internal[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we),
        .DO(doq_internal[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we),
        .DO(doq_internal[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we),
        .DO(doq_internal[7:6])
);
 
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
 
 
`elsif MINSOC_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// SPARTAN3/SPARTAN3E/VIRTEX2
// SPARTAN3A/VIRTEX4/VIRTEX5 are automatically reallocated by ISE
//
// Added By Nir Mor
//
 
wire    [dw-1:0] doq_internal;   // output data bus
 
RAMB16_S9 ramb16_s9(
        .CLK(clk),
        .SSR(rst),
        .ADDR(addr),
        .DI(di),
        .DIP(1'b0),
        .EN(ce),
        .WE(we),
        .DO(doq_internal),
        .DOP()
);
 
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
 
 
`elsif ALTERA_FPGA
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
wire    [dw-1:0] doq_internal;   // output data bus
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .data(di),
        .we(wr),
        .q(doq_internal)
);
 
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
 
`endif  // !ALTERA_FPGA/MINCON_XILINX_RAMB16/MINCON_XILINX_RAMB4/VIRTUALSILICON_SSP/VIRAGE_SSP/AVANT_ATP/ARTISAN_SSP/GENERIC_MEMORY
 
 
endmodule

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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_onchip_ram.v] - Blame information for rev 173

Line No.	Rev	Author	Line
1	2	rfajardo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Raul Fajardo, rfajardo@gmail.com ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.gnu.org/licenses/lgpl.html ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// Revision History`
65			`//`
66			`//`
67	6	rfajardo	`// Revision 2.1 2009/08/23 16:41:00 fajardo`
68			`// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY`
69			`// This actually models appropriately the behavior of the FPGA internal RAMs`
70			`//`
71	2	rfajardo	`// Revision 2.0 2009/09/10 11:30:00 fajardo`
72			`// Added tri-state buffering for altera output`
73			`// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY`
74			`//`
75			`// Revision 1.9 2009/08/18 15:15:00 fajardo`
76			`// Added tri-state buffering for xilinx and generic memory output`
77			`//`
78			`// $Log: not supported by cvs2svn $`
79			`// Revision 1.8 2004/06/08 18:15:32 lampret`
80			`// Changed behavior of the simulation generic models`
81			`//`
82			`// Revision 1.7 2004/04/05 08:29:57 lampret`
83			`// Merged branch_qmem into main tree.`
84			`//`
85			`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
86			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
87			`//`
88			`// Revision 1.3 2003/04/07 01:19:07 lampret`
89			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
90			`//`
91			`// Revision 1.2 2002/10/17 20:04:40 lampret`
92			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
93			`//`
94			`// Revision 1.1 2002/01/03 08:16:15 lampret`
95			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
96			`//`
97			`// Revision 1.8 2001/11/02 18:57:14 lampret`
98			`// Modified virtual silicon instantiations.`
99			`//`
100			`// Revision 1.7 2001/10/21 17:57:16 lampret`
101			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
102			`//`
103			`// Revision 1.6 2001/10/14 13:12:09 lampret`
104			`// MP3 version.`
105			`//`
106			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
107			`// no message`
108			`//`
109			`// Revision 1.1 2001/08/09 13:39:33 lampret`
110			`// Major clean-up.`
111			`//`
112			`// Revision 1.2 2001/07/30 05:38:02 lampret`
113			`// Adding empty directories required by HDL coding guidelines`
114			`//`
115			`//`
116
117			`// synopsys translate_off`
118			`include "timescale.v"
119			`// synopsys translate_on`
120			`include "minsoc_defines.v"
121
122			`module minsoc_onchip_ram(`
123			`ifdef BIST
124			`// RAM BIST`
125			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
126			`endif
127			`// Generic synchronous single-port RAM interface`
128			`clk, rst, ce, we, oe, addr, di, doq`
129			`);`
130
131			`//`
132			`// Default address and data buses width`
133			`//`
134			`parameter aw = 11;`
135			`parameter dw = 8;`
136
137			`ifdef BIST
138			`//`
139			`// RAM BIST`
140			`//`
141			`input mbist_si_i;`
142			input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
143			`output mbist_so_o;`
144			`endif
145
146			`//`
147			`// Generic synchronous single-port RAM interface`
148			`//`
149			`input clk; // Clock`
150			`input rst; // Reset`
151			`input ce; // Chip enable input`
152			`input we; // Write enable input`
153			`input oe; // Output enable input`
154			`input [aw-1:0] addr; // address bus inputs`
155			`input [dw-1:0] di; // input data bus`
156			`output [dw-1:0] doq; // output data bus`
157
158			`//`
159			`// Decide memory implementation for Xilinx FPGAs`
160			`//`
161			`ifdef SPARTAN2
162			`define MINSOC_XILINX_RAMB4
163			`elsif VIRTEX
164			`define MINSOC_XILINX_RAMB4
165			`endif // !SPARTAN2/VIRTEX
166
167			`ifdef SPARTAN3
168			`define MINSOC_XILINX_RAMB16
169			`elsif SPARTAN3E
170			`define MINSOC_XILINX_RAMB16
171			`elsif SPARTAN3A
172			`define MINSOC_XILINX_RAMB16
173			`elsif VIRTEX2
174			`define MINSOC_XILINX_RAMB16
175			`elsif VIRTEX4
176			`define MINSOC_XILINX_RAMB16
177			`elsif VIRTEX5
178			`define MINSOC_XILINX_RAMB16
179	173	rfajardo	`elsif SPARTAN6
180			`define MINSOC_XILINX_RAMB16
181			`endif // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5/SPARTAN6
182	2	rfajardo
183
184			`//`
185			`// Internal wires and registers`
186			`//`
187
188			`ifdef ARTISAN_SSP
189			`else
190			`ifdef VIRTUALSILICON_SSP
191			`else
192			`ifdef BIST
193			`assign mbist_so_o = mbist_si_i;`
194			`endif
195			`endif
196			`endif
197
198
199			`ifdef GENERIC_MEMORY
200			`//`
201			`// Generic single-port synchronous RAM model`
202			`//`
203
204			`//`
205			`// Generic RAM's registers and wires`
206			`//`
207			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
208			`reg [aw-1:0] addr_reg; // RAM address register`
209
210			`//`
211			`// Data output drivers`
212			`//`
213			`assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};`
214
215			`//`
216			`// RAM address register`
217			`//`
218	6	rfajardo	`always @(posedge clk or posedge rst)`
219	2	rfajardo	`if (rst)`
220			`addr_reg <= #1 {aw{1'b0}};`
221			`else if (ce)`
222			`addr_reg <= #1 addr;`
223
224			`//`
225			`// RAM write`
226			`//`
227	6	rfajardo	`always @(posedge clk)`
228	2	rfajardo	`if (ce && we)`
229			`mem[addr] <= #1 di;`
230
231
232			`elsif ARTISAN_SSP
233			`//`
234			`// Instantiation of ASIC memory:`
235			`//`
236			`// Artisan Synchronous Single-Port RAM (ra1sh)`
237			`//`
238			`ifdef UNUSED
239			`art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(`
240			`else
241			`ifdef BIST
242			`art_hssp_2048x8_bist artisan_ssp(`
243			`else
244			`art_hssp_2048x8 artisan_ssp(`
245			`endif
246			`endif
247			`ifdef BIST
248			`// RAM BIST`
249			`.mbist_si_i(mbist_si_i),`
250			`.mbist_so_o(mbist_so_o),`
251			`.mbist_ctrl_i(mbist_ctrl_i),`
252			`endif
253			`.CLK(clk),`
254			`.CEN(~ce),`
255			`.WEN(~we),`
256			`.A(addr),`
257			`.D(di),`
258			`.OEN(~oe),`
259			`.Q(doq)`
260			`);`
261
262
263			`elsif AVANT_ATP
264			`//`
265			`// Instantiation of ASIC memory:`
266			`//`
267			`// Avant! Asynchronous Two-Port RAM`
268			`//`
269			`avant_atp avant_atp(`
270			`.web(~we),`
271			`.reb(),`
272			`.oeb(~oe),`
273			`.rcsb(),`
274			`.wcsb(),`
275			`.ra(addr),`
276			`.wa(addr),`
277			`.di(di),`
278			`.doq(doq)`
279			`);`
280
281
282			`elsif VIRAGE_SSP
283			`//`
284			`// Instantiation of ASIC memory:`
285			`//`
286			`// Virage Synchronous 1-port R/W RAM`
287			`//`
288			`virage_ssp virage_ssp(`
289			`.clk(clk),`
290			`.adr(addr),`
291			`.d(di),`
292			`.we(we),`
293			`.oe(oe),`
294			`.me(ce),`
295			`.q(doq)`
296			`);`
297
298
299			`elsif VIRTUALSILICON_SSP
300			`//`
301			`// Instantiation of ASIC memory:`
302			`//`
303			`// Virtual Silicon Single-Port Synchronous SRAM`
304			`//`
305			`ifdef UNUSED
306			`vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(`
307			`else
308			`ifdef BIST
309			`vs_hdsp_2048x8_bist vs_ssp(`
310			`else
311			`vs_hdsp_2048x8 vs_ssp(`
312			`endif
313			`endif
314			`ifdef BIST
315			`// RAM BIST`
316			`.mbist_si_i(mbist_si_i),`
317			`.mbist_so_o(mbist_so_o),`
318			`.mbist_ctrl_i(mbist_ctrl_i),`
319			`endif
320			`.CK(clk),`
321			`.ADR(addr),`
322			`.DI(di),`
323			`.WEN(~we),`
324			`.CEN(~ce),`
325			`.OEN(~oe),`
326			`.DOUT(doq)`
327			`);`
328
329
330			`elsif MINSOC_XILINX_RAMB4
331			`//`
332			`// Instantiation of FPGA memory:`
333			`//`
334			`// SPARTAN2/VIRTEX`
335			`//`
336
337			`wire [dw-1:0] doq_internal; // output data bus`
338
339			`//`
340			`// Block 0`
341			`//`
342			`RAMB4_S2 ramb4_s2_0(`
343			`.CLK(clk),`
344			`.RST(rst),`
345			`.ADDR(addr),`
346			`.DI(di[1:0]),`
347			`.EN(ce),`
348			`.WE(we),`
349			`.DO(doq_internal[1:0])`
350			`);`
351
352			`//`
353			`// Block 1`
354			`//`
355			`RAMB4_S2 ramb4_s2_1(`
356			`.CLK(clk),`
357			`.RST(rst),`
358			`.ADDR(addr),`
359			`.DI(di[3:2]),`
360			`.EN(ce),`
361			`.WE(we),`
362			`.DO(doq_internal[3:2])`
363			`);`
364
365			`//`
366			`// Block 2`
367			`//`
368			`RAMB4_S2 ramb4_s2_2(`
369			`.CLK(clk),`
370			`.RST(rst),`
371			`.ADDR(addr),`
372			`.DI(di[5:4]),`
373			`.EN(ce),`
374			`.WE(we),`
375			`.DO(doq_internal[5:4])`
376			`);`
377
378			`//`
379			`// Block 3`
380			`//`
381			`RAMB4_S2 ramb4_s2_3(`
382			`.CLK(clk),`
383			`.RST(rst),`
384			`.ADDR(addr),`
385			`.DI(di[7:6]),`
386			`.EN(ce),`
387			`.WE(we),`
388			`.DO(doq_internal[7:6])`
389			`);`
390
391			`assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };`
392
393
394			`elsif MINSOC_XILINX_RAMB16
395			`//`
396			`// Instantiation of FPGA memory:`
397			`//`
398			`// SPARTAN3/SPARTAN3E/VIRTEX2`
399			`// SPARTAN3A/VIRTEX4/VIRTEX5 are automatically reallocated by ISE`
400			`//`
401			`// Added By Nir Mor`
402			`//`
403
404			`wire [dw-1:0] doq_internal; // output data bus`
405
406			`RAMB16_S9 ramb16_s9(`
407			`.CLK(clk),`
408			`.SSR(rst),`
409			`.ADDR(addr),`
410			`.DI(di),`
411			`.DIP(1'b0),`
412			`.EN(ce),`
413			`.WE(we),`
414			`.DO(doq_internal),`
415			`.DOP()`
416			`);`
417
418			`assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };`
419
420
421			`elsif ALTERA_FPGA
422			`//`
423			`// Instantiation of FPGA memory:`
424			`//`
425			`// Altera LPM`
426			`//`
427			`// Added By Jamil Khatib`
428			`//`
429
430			`wire wr;`
431
432			`assign wr = ce & we;`
433
434			`wire [dw-1:0] doq_internal; // output data bus`
435
436			`initial $display("Using Altera LPM.");`
437
438			`lpm_ram_dq lpm_ram_dq_component (`
439			`.address(addr),`
440			`.inclock(clk),`
441			`.data(di),`
442			`.we(wr),`
443			`.q(doq_internal)`
444			`);`
445
446			`assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };`
447
448			`defparam lpm_ram_dq_component.lpm_width = dw,`
449			`lpm_ram_dq_component.lpm_widthad = aw,`
450			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
451			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
452			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
453			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
454			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
455
456
457			`endif // !ALTERA_FPGA/MINCON_XILINX_RAMB16/MINCON_XILINX_RAMB4/VIRTUALSILICON_SSP/VIRAGE_SSP/AVANT_ATP/ARTISAN_SSP/GENERIC_MEMORY
458
459
460			`endmodule`