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1 2 rfajardo
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Single-Port Synchronous RAM                         ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/minsoc/               ////
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////                                                              ////
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////  Description                                                 ////
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////  This block is a wrapper with common single-port             ////
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////  synchronous memory interface for different                  ////
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////  types of ASIC and FPGA RAMs. Beside universal memory        ////
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////  interface it also provides behavioral model of generic      ////
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////  single-port synchronous RAM.                                ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Supported ASIC RAMs are:                                    ////
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////  - Artisan Single-Port Sync RAM                              ////
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////  - Avant! Two-Port Sync RAM (*)                              ////
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////  - Virage Single-Port Sync RAM                               ////
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////  - Virtual Silicon Single-Port Sync RAM                      ////
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////                                                              ////
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////  Supported FPGA RAMs are:                                    ////
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////  - Xilinx Virtex RAMB16                                      ////
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////  - Xilinx Virtex RAMB4                                       ////
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////  - Altera LPM                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - fix avant! two-port ram                                  ////
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////   - add additional RAMs                                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Raul Fajardo, rfajardo@gmail.com                      ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.gnu.org/licenses/lgpl.html                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// Revision History
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//
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//
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// Revision 2.0 2009/09/10 11:30:00   fajardo
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// Added tri-state buffering for altera output
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// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY
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//
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// Revision 1.9 2009/08/18 15:15:00   fajardo
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// Added tri-state buffering for xilinx and generic memory output
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.8  2004/06/08 18:15:32  lampret
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// Changed behavior of the simulation generic models
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//
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// Revision 1.7  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.3.4.1  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.3  2003/04/07 01:19:07  lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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// Revision 1.2  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8  2001/11/02 18:57:14  lampret
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// Modified virtual silicon instantiations.
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//
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// Revision 1.7  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.6  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.1  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.2  2001/07/30 05:38:02  lampret
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// Adding empty directories required by HDL coding guidelines
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//
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//
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113
// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "minsoc_defines.v"
117
 
118
module minsoc_onchip_ram(
119
`ifdef BIST
120
        // RAM BIST
121
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
122
`endif
123
        // Generic synchronous single-port RAM interface
124
        clk, rst, ce, we, oe, addr, di, doq
125
);
126
 
127
//
128
// Default address and data buses width
129
//
130
parameter aw = 11;
131
parameter dw = 8;
132
 
133
`ifdef BIST
134
//
135
// RAM BIST
136
//
137
input mbist_si_i;
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input [`MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
139
output mbist_so_o;
140
`endif
141
 
142
//
143
// Generic synchronous single-port RAM interface
144
//
145
input                   clk;    // Clock
146
input                   rst;    // Reset
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input                   ce;     // Chip enable input
148
input                   we;     // Write enable input
149
input                   oe;     // Output enable input
150
input   [aw-1:0] addr;   // address bus inputs
151
input   [dw-1:0] di;     // input data bus
152
output  [dw-1:0] doq;    // output data bus
153
 
154
//
155
// Decide memory implementation for Xilinx FPGAs
156
//
157
`ifdef SPARTAN2
158
        `define MINSOC_XILINX_RAMB4
159
`elsif VIRTEX
160
        `define MINSOC_XILINX_RAMB4
161
`endif  // !SPARTAN2/VIRTEX
162
 
163
`ifdef SPARTAN3
164
        `define MINSOC_XILINX_RAMB16
165
`elsif SPARTAN3E
166
        `define MINSOC_XILINX_RAMB16
167
`elsif SPARTAN3A
168
        `define MINSOC_XILINX_RAMB16
169
`elsif VIRTEX2
170
        `define MINSOC_XILINX_RAMB16
171
`elsif VIRTEX4
172
        `define MINSOC_XILINX_RAMB16
173
`elsif VIRTEX5
174
        `define MINSOC_XILINX_RAMB16
175
`endif  // !SPARTAN3/SPARTAN3E/SPARTAN3A/VIRTEX2/VIRTEX4/VIRTEX5
176
 
177
 
178
//
179
// Internal wires and registers
180
//
181
 
182
`ifdef ARTISAN_SSP
183
`else
184
`ifdef VIRTUALSILICON_SSP
185
`else
186
`ifdef BIST
187
assign mbist_so_o = mbist_si_i;
188
`endif
189
`endif
190
`endif
191
 
192
 
193
`ifdef GENERIC_MEMORY
194
//
195
// Generic single-port synchronous RAM model
196
//
197
 
198
//
199
// Generic RAM's registers and wires
200
//
201
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
202
reg     [aw-1:0] addr_reg;               // RAM address register
203
 
204
//
205
// Data output drivers
206
//
207
assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};
208
 
209
//
210
// RAM address register
211
//
212
always @(negedge clk or posedge rst)
213
        if (rst)
214
                addr_reg <= #1 {aw{1'b0}};
215
        else if (ce)
216
                addr_reg <= #1 addr;
217
 
218
//
219
// RAM write
220
//
221
always @(negedge clk)
222
        if (ce && we)
223
                mem[addr] <= #1 di;
224
 
225
 
226
`elsif ARTISAN_SSP
227
//
228
// Instantiation of ASIC memory:
229
//
230
// Artisan Synchronous Single-Port RAM (ra1sh)
231
//
232
`ifdef UNUSED
233
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
234
`else
235
`ifdef BIST
236
art_hssp_2048x8_bist artisan_ssp(
237
`else
238
art_hssp_2048x8 artisan_ssp(
239
`endif
240
`endif
241
`ifdef BIST
242
        // RAM BIST
243
        .mbist_si_i(mbist_si_i),
244
        .mbist_so_o(mbist_so_o),
245
        .mbist_ctrl_i(mbist_ctrl_i),
246
`endif
247
        .CLK(clk),
248
        .CEN(~ce),
249
        .WEN(~we),
250
        .A(addr),
251
        .D(di),
252
        .OEN(~oe),
253
        .Q(doq)
254
);
255
 
256
 
257
`elsif AVANT_ATP
258
//
259
// Instantiation of ASIC memory:
260
//
261
// Avant! Asynchronous Two-Port RAM
262
//
263
avant_atp avant_atp(
264
        .web(~we),
265
        .reb(),
266
        .oeb(~oe),
267
        .rcsb(),
268
        .wcsb(),
269
        .ra(addr),
270
        .wa(addr),
271
        .di(di),
272
        .doq(doq)
273
);
274
 
275
 
276
`elsif VIRAGE_SSP
277
//
278
// Instantiation of ASIC memory:
279
//
280
// Virage Synchronous 1-port R/W RAM
281
//
282
virage_ssp virage_ssp(
283
        .clk(clk),
284
        .adr(addr),
285
        .d(di),
286
        .we(we),
287
        .oe(oe),
288
        .me(ce),
289
        .q(doq)
290
);
291
 
292
 
293
`elsif VIRTUALSILICON_SSP
294
//
295
// Instantiation of ASIC memory:
296
//
297
// Virtual Silicon Single-Port Synchronous SRAM
298
//
299
`ifdef UNUSED
300
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
301
`else
302
`ifdef BIST
303
vs_hdsp_2048x8_bist vs_ssp(
304
`else
305
vs_hdsp_2048x8 vs_ssp(
306
`endif
307
`endif
308
`ifdef BIST
309
        // RAM BIST
310
        .mbist_si_i(mbist_si_i),
311
        .mbist_so_o(mbist_so_o),
312
        .mbist_ctrl_i(mbist_ctrl_i),
313
`endif
314
        .CK(clk),
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        .ADR(addr),
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        .DI(di),
317
        .WEN(~we),
318
        .CEN(~ce),
319
        .OEN(~oe),
320
        .DOUT(doq)
321
);
322
 
323
 
324
`elsif MINSOC_XILINX_RAMB4
325
//
326
// Instantiation of FPGA memory:
327
//
328
// SPARTAN2/VIRTEX
329
//
330
 
331
wire    [dw-1:0] doq_internal;   // output data bus
332
 
333
//
334
// Block 0
335
//
336
RAMB4_S2 ramb4_s2_0(
337
        .CLK(clk),
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        .RST(rst),
339
        .ADDR(addr),
340
        .DI(di[1:0]),
341
        .EN(ce),
342
        .WE(we),
343
        .DO(doq_internal[1:0])
344
);
345
 
346
//
347
// Block 1
348
//
349
RAMB4_S2 ramb4_s2_1(
350
        .CLK(clk),
351
        .RST(rst),
352
        .ADDR(addr),
353
        .DI(di[3:2]),
354
        .EN(ce),
355
        .WE(we),
356
        .DO(doq_internal[3:2])
357
);
358
 
359
//
360
// Block 2
361
//
362
RAMB4_S2 ramb4_s2_2(
363
        .CLK(clk),
364
        .RST(rst),
365
        .ADDR(addr),
366
        .DI(di[5:4]),
367
        .EN(ce),
368
        .WE(we),
369
        .DO(doq_internal[5:4])
370
);
371
 
372
//
373
// Block 3
374
//
375
RAMB4_S2 ramb4_s2_3(
376
        .CLK(clk),
377
        .RST(rst),
378
        .ADDR(addr),
379
        .DI(di[7:6]),
380
        .EN(ce),
381
        .WE(we),
382
        .DO(doq_internal[7:6])
383
);
384
 
385
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
386
 
387
 
388
`elsif MINSOC_XILINX_RAMB16
389
//
390
// Instantiation of FPGA memory:
391
//
392
// SPARTAN3/SPARTAN3E/VIRTEX2
393
// SPARTAN3A/VIRTEX4/VIRTEX5 are automatically reallocated by ISE
394
//
395
// Added By Nir Mor
396
//
397
 
398
wire    [dw-1:0] doq_internal;   // output data bus
399
 
400
RAMB16_S9 ramb16_s9(
401
        .CLK(clk),
402
        .SSR(rst),
403
        .ADDR(addr),
404
        .DI(di),
405
        .DIP(1'b0),
406
        .EN(ce),
407
        .WE(we),
408
        .DO(doq_internal),
409
        .DOP()
410
);
411
 
412
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
413
 
414
 
415
`elsif ALTERA_FPGA
416
//
417
// Instantiation of FPGA memory:
418
//
419
// Altera LPM
420
//
421
// Added By Jamil Khatib
422
//
423
 
424
wire    wr;
425
 
426
assign  wr = ce & we;
427
 
428
wire    [dw-1:0] doq_internal;   // output data bus
429
 
430
initial $display("Using Altera LPM.");
431
 
432
lpm_ram_dq lpm_ram_dq_component (
433
        .address(addr),
434
        .inclock(clk),
435
//        .outclock(clk),
436
        .data(di),
437
        .we(wr),
438
        .q(doq_internal)
439
);
440
 
441
assign doq = (oe) ? (doq_internal) : { dw{1'bZ} };
442
 
443
defparam lpm_ram_dq_component.lpm_width = dw,
444
        lpm_ram_dq_component.lpm_widthad = aw,
445
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
446
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
447
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
448
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
449
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
450
 
451
 
452
`endif  // !ALTERA_FPGA/MINCON_XILINX_RAMB16/MINCON_XILINX_RAMB4/VIRTUALSILICON_SSP/VIRAGE_SSP/AVANT_ATP/ARTISAN_SSP/GENERIC_MEMORY
453
 
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endmodule

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