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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_tc_top.v] - Blame information for rev 2

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1 2 rfajardo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Xess Traffic Cop                                            ////
4
////                                                              ////
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////  This file is part of the OR1K test application              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
9
////  This block connectes the RISC and peripheral controller     ////
10
////  cores together.                                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - nothing really                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2002 OpenCores                                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: tc_top.v,v $
48
// Revision 1.4  2004/04/05 08:44:34  lampret
49
// Merged branch_qmem into main tree.
50
//
51
// Revision 1.2  2002/03/29 20:57:30  lampret
52
// Removed unused ports wb_clki and wb_rst_i
53
//
54
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
55
// First import of the "new" XESS XSV environment.
56
//
57
//
58
//
59
 
60
// synopsys translate_off
61
`include "timescale.v"
62
// synopsys translate_on
63
 
64
//
65
// Width of address bus
66
//
67
`define TC_AW           32
68
 
69
//
70
// Width of data bus
71
//
72
`define TC_DW           32
73
 
74
//
75
// Width of byte select bus
76
//
77
`define TC_BSW          4
78
 
79
//
80
// Width of WB target inputs (coming from WB slave)
81
//
82
// data bus width + ack + err
83
//
84
`define TC_TIN_W        `TC_DW+1+1
85
 
86
//
87
// Width of WB initiator inputs (coming from WB masters)
88
//
89
// cyc + stb + cab + address bus width +
90
// byte select bus width + we + data bus width
91
//
92
`define TC_IIN_W        1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
93
 
94
//
95
// Traffic Cop Top
96
//
97
module minsoc_tc_top (
98
        wb_clk_i,
99
        wb_rst_i,
100
 
101
        i0_wb_cyc_i,
102
        i0_wb_stb_i,
103
        i0_wb_cab_i,
104
        i0_wb_adr_i,
105
        i0_wb_sel_i,
106
        i0_wb_we_i,
107
        i0_wb_dat_i,
108
        i0_wb_dat_o,
109
        i0_wb_ack_o,
110
        i0_wb_err_o,
111
 
112
        i1_wb_cyc_i,
113
        i1_wb_stb_i,
114
        i1_wb_cab_i,
115
        i1_wb_adr_i,
116
        i1_wb_sel_i,
117
        i1_wb_we_i,
118
        i1_wb_dat_i,
119
        i1_wb_dat_o,
120
        i1_wb_ack_o,
121
        i1_wb_err_o,
122
 
123
        i2_wb_cyc_i,
124
        i2_wb_stb_i,
125
        i2_wb_cab_i,
126
        i2_wb_adr_i,
127
        i2_wb_sel_i,
128
        i2_wb_we_i,
129
        i2_wb_dat_i,
130
        i2_wb_dat_o,
131
        i2_wb_ack_o,
132
        i2_wb_err_o,
133
 
134
        i3_wb_cyc_i,
135
        i3_wb_stb_i,
136
        i3_wb_cab_i,
137
        i3_wb_adr_i,
138
        i3_wb_sel_i,
139
        i3_wb_we_i,
140
        i3_wb_dat_i,
141
        i3_wb_dat_o,
142
        i3_wb_ack_o,
143
        i3_wb_err_o,
144
 
145
        i4_wb_cyc_i,
146
        i4_wb_stb_i,
147
        i4_wb_cab_i,
148
        i4_wb_adr_i,
149
        i4_wb_sel_i,
150
        i4_wb_we_i,
151
        i4_wb_dat_i,
152
        i4_wb_dat_o,
153
        i4_wb_ack_o,
154
        i4_wb_err_o,
155
 
156
        i5_wb_cyc_i,
157
        i5_wb_stb_i,
158
        i5_wb_cab_i,
159
        i5_wb_adr_i,
160
        i5_wb_sel_i,
161
        i5_wb_we_i,
162
        i5_wb_dat_i,
163
        i5_wb_dat_o,
164
        i5_wb_ack_o,
165
        i5_wb_err_o,
166
 
167
        i6_wb_cyc_i,
168
        i6_wb_stb_i,
169
        i6_wb_cab_i,
170
        i6_wb_adr_i,
171
        i6_wb_sel_i,
172
        i6_wb_we_i,
173
        i6_wb_dat_i,
174
        i6_wb_dat_o,
175
        i6_wb_ack_o,
176
        i6_wb_err_o,
177
 
178
        i7_wb_cyc_i,
179
        i7_wb_stb_i,
180
        i7_wb_cab_i,
181
        i7_wb_adr_i,
182
        i7_wb_sel_i,
183
        i7_wb_we_i,
184
        i7_wb_dat_i,
185
        i7_wb_dat_o,
186
        i7_wb_ack_o,
187
        i7_wb_err_o,
188
 
189
        t0_wb_cyc_o,
190
        t0_wb_stb_o,
191
        t0_wb_cab_o,
192
        t0_wb_adr_o,
193
        t0_wb_sel_o,
194
        t0_wb_we_o,
195
        t0_wb_dat_o,
196
        t0_wb_dat_i,
197
        t0_wb_ack_i,
198
        t0_wb_err_i,
199
 
200
        t1_wb_cyc_o,
201
        t1_wb_stb_o,
202
        t1_wb_cab_o,
203
        t1_wb_adr_o,
204
        t1_wb_sel_o,
205
        t1_wb_we_o,
206
        t1_wb_dat_o,
207
        t1_wb_dat_i,
208
        t1_wb_ack_i,
209
        t1_wb_err_i,
210
 
211
        t2_wb_cyc_o,
212
        t2_wb_stb_o,
213
        t2_wb_cab_o,
214
        t2_wb_adr_o,
215
        t2_wb_sel_o,
216
        t2_wb_we_o,
217
        t2_wb_dat_o,
218
        t2_wb_dat_i,
219
        t2_wb_ack_i,
220
        t2_wb_err_i,
221
 
222
        t3_wb_cyc_o,
223
        t3_wb_stb_o,
224
        t3_wb_cab_o,
225
        t3_wb_adr_o,
226
        t3_wb_sel_o,
227
        t3_wb_we_o,
228
        t3_wb_dat_o,
229
        t3_wb_dat_i,
230
        t3_wb_ack_i,
231
        t3_wb_err_i,
232
 
233
        t4_wb_cyc_o,
234
        t4_wb_stb_o,
235
        t4_wb_cab_o,
236
        t4_wb_adr_o,
237
        t4_wb_sel_o,
238
        t4_wb_we_o,
239
        t4_wb_dat_o,
240
        t4_wb_dat_i,
241
        t4_wb_ack_i,
242
        t4_wb_err_i,
243
 
244
        t5_wb_cyc_o,
245
        t5_wb_stb_o,
246
        t5_wb_cab_o,
247
        t5_wb_adr_o,
248
        t5_wb_sel_o,
249
        t5_wb_we_o,
250
        t5_wb_dat_o,
251
        t5_wb_dat_i,
252
        t5_wb_ack_i,
253
        t5_wb_err_i,
254
 
255
        t6_wb_cyc_o,
256
        t6_wb_stb_o,
257
        t6_wb_cab_o,
258
        t6_wb_adr_o,
259
        t6_wb_sel_o,
260
        t6_wb_we_o,
261
        t6_wb_dat_o,
262
        t6_wb_dat_i,
263
        t6_wb_ack_i,
264
        t6_wb_err_i,
265
 
266
        t7_wb_cyc_o,
267
        t7_wb_stb_o,
268
        t7_wb_cab_o,
269
        t7_wb_adr_o,
270
        t7_wb_sel_o,
271
        t7_wb_we_o,
272
        t7_wb_dat_o,
273
        t7_wb_dat_i,
274
        t7_wb_ack_i,
275
        t7_wb_err_i,
276
 
277
        t8_wb_cyc_o,
278
        t8_wb_stb_o,
279
        t8_wb_cab_o,
280
        t8_wb_adr_o,
281
        t8_wb_sel_o,
282
        t8_wb_we_o,
283
        t8_wb_dat_o,
284
        t8_wb_dat_i,
285
        t8_wb_ack_i,
286
        t8_wb_err_i
287
 
288
);
289
 
290
//
291
// Parameters
292
//
293
parameter               t0_addr_w = 4;
294
parameter               t0_addr = 4'd8;
295
parameter               t1_addr_w = 4;
296
parameter               t1_addr = 4'd0;
297
parameter               t28c_addr_w = 4;
298
parameter               t28_addr = 4'd0;
299
parameter               t28i_addr_w = 4;
300
parameter               t2_addr = 4'd1;
301
parameter               t3_addr = 4'd2;
302
parameter               t4_addr = 4'd3;
303
parameter               t5_addr = 4'd4;
304
parameter               t6_addr = 4'd5;
305
parameter               t7_addr = 4'd6;
306
parameter               t8_addr = 4'd7;
307
 
308
//
309
// I/O Ports
310
//
311
input                   wb_clk_i;
312
input                   wb_rst_i;
313
 
314
//
315
// WB slave i/f connecting initiator 0
316
//
317
input                   i0_wb_cyc_i;
318
input                   i0_wb_stb_i;
319
input                   i0_wb_cab_i;
320
input   [`TC_AW-1:0]     i0_wb_adr_i;
321
input   [`TC_BSW-1:0]    i0_wb_sel_i;
322
input                   i0_wb_we_i;
323
input   [`TC_DW-1:0]     i0_wb_dat_i;
324
output  [`TC_DW-1:0]     i0_wb_dat_o;
325
output                  i0_wb_ack_o;
326
output                  i0_wb_err_o;
327
 
328
//
329
// WB slave i/f connecting initiator 1
330
//
331
input                   i1_wb_cyc_i;
332
input                   i1_wb_stb_i;
333
input                   i1_wb_cab_i;
334
input   [`TC_AW-1:0]     i1_wb_adr_i;
335
input   [`TC_BSW-1:0]    i1_wb_sel_i;
336
input                   i1_wb_we_i;
337
input   [`TC_DW-1:0]     i1_wb_dat_i;
338
output  [`TC_DW-1:0]     i1_wb_dat_o;
339
output                  i1_wb_ack_o;
340
output                  i1_wb_err_o;
341
 
342
//
343
// WB slave i/f connecting initiator 2
344
//
345
input                   i2_wb_cyc_i;
346
input                   i2_wb_stb_i;
347
input                   i2_wb_cab_i;
348
input   [`TC_AW-1:0]     i2_wb_adr_i;
349
input   [`TC_BSW-1:0]    i2_wb_sel_i;
350
input                   i2_wb_we_i;
351
input   [`TC_DW-1:0]     i2_wb_dat_i;
352
output  [`TC_DW-1:0]     i2_wb_dat_o;
353
output                  i2_wb_ack_o;
354
output                  i2_wb_err_o;
355
 
356
//
357
// WB slave i/f connecting initiator 3
358
//
359
input                   i3_wb_cyc_i;
360
input                   i3_wb_stb_i;
361
input                   i3_wb_cab_i;
362
input   [`TC_AW-1:0]     i3_wb_adr_i;
363
input   [`TC_BSW-1:0]    i3_wb_sel_i;
364
input                   i3_wb_we_i;
365
input   [`TC_DW-1:0]     i3_wb_dat_i;
366
output  [`TC_DW-1:0]     i3_wb_dat_o;
367
output                  i3_wb_ack_o;
368
output                  i3_wb_err_o;
369
 
370
//
371
// WB slave i/f connecting initiator 4
372
//
373
input                   i4_wb_cyc_i;
374
input                   i4_wb_stb_i;
375
input                   i4_wb_cab_i;
376
input   [`TC_AW-1:0]     i4_wb_adr_i;
377
input   [`TC_BSW-1:0]    i4_wb_sel_i;
378
input                   i4_wb_we_i;
379
input   [`TC_DW-1:0]     i4_wb_dat_i;
380
output  [`TC_DW-1:0]     i4_wb_dat_o;
381
output                  i4_wb_ack_o;
382
output                  i4_wb_err_o;
383
 
384
//
385
// WB slave i/f connecting initiator 5
386
//
387
input                   i5_wb_cyc_i;
388
input                   i5_wb_stb_i;
389
input                   i5_wb_cab_i;
390
input   [`TC_AW-1:0]     i5_wb_adr_i;
391
input   [`TC_BSW-1:0]    i5_wb_sel_i;
392
input                   i5_wb_we_i;
393
input   [`TC_DW-1:0]     i5_wb_dat_i;
394
output  [`TC_DW-1:0]     i5_wb_dat_o;
395
output                  i5_wb_ack_o;
396
output                  i5_wb_err_o;
397
 
398
//
399
// WB slave i/f connecting initiator 6
400
//
401
input                   i6_wb_cyc_i;
402
input                   i6_wb_stb_i;
403
input                   i6_wb_cab_i;
404
input   [`TC_AW-1:0]     i6_wb_adr_i;
405
input   [`TC_BSW-1:0]    i6_wb_sel_i;
406
input                   i6_wb_we_i;
407
input   [`TC_DW-1:0]     i6_wb_dat_i;
408
output  [`TC_DW-1:0]     i6_wb_dat_o;
409
output                  i6_wb_ack_o;
410
output                  i6_wb_err_o;
411
 
412
//
413
// WB slave i/f connecting initiator 7
414
//
415
input                   i7_wb_cyc_i;
416
input                   i7_wb_stb_i;
417
input                   i7_wb_cab_i;
418
input   [`TC_AW-1:0]     i7_wb_adr_i;
419
input   [`TC_BSW-1:0]    i7_wb_sel_i;
420
input                   i7_wb_we_i;
421
input   [`TC_DW-1:0]     i7_wb_dat_i;
422
output  [`TC_DW-1:0]     i7_wb_dat_o;
423
output                  i7_wb_ack_o;
424
output                  i7_wb_err_o;
425
 
426
//
427
// WB master i/f connecting target 0
428
//
429
output                  t0_wb_cyc_o;
430
output                  t0_wb_stb_o;
431
output                  t0_wb_cab_o;
432
output  [`TC_AW-1:0]     t0_wb_adr_o;
433
output  [`TC_BSW-1:0]    t0_wb_sel_o;
434
output                  t0_wb_we_o;
435
output  [`TC_DW-1:0]     t0_wb_dat_o;
436
input   [`TC_DW-1:0]     t0_wb_dat_i;
437
input                   t0_wb_ack_i;
438
input                   t0_wb_err_i;
439
 
440
//
441
// WB master i/f connecting target 1
442
//
443
output                  t1_wb_cyc_o;
444
output                  t1_wb_stb_o;
445
output                  t1_wb_cab_o;
446
output  [`TC_AW-1:0]     t1_wb_adr_o;
447
output  [`TC_BSW-1:0]    t1_wb_sel_o;
448
output                  t1_wb_we_o;
449
output  [`TC_DW-1:0]     t1_wb_dat_o;
450
input   [`TC_DW-1:0]     t1_wb_dat_i;
451
input                   t1_wb_ack_i;
452
input                   t1_wb_err_i;
453
 
454
//
455
// WB master i/f connecting target 2
456
//
457
output                  t2_wb_cyc_o;
458
output                  t2_wb_stb_o;
459
output                  t2_wb_cab_o;
460
output  [`TC_AW-1:0]     t2_wb_adr_o;
461
output  [`TC_BSW-1:0]    t2_wb_sel_o;
462
output                  t2_wb_we_o;
463
output  [`TC_DW-1:0]     t2_wb_dat_o;
464
input   [`TC_DW-1:0]     t2_wb_dat_i;
465
input                   t2_wb_ack_i;
466
input                   t2_wb_err_i;
467
 
468
//
469
// WB master i/f connecting target 3
470
//
471
output                  t3_wb_cyc_o;
472
output                  t3_wb_stb_o;
473
output                  t3_wb_cab_o;
474
output  [`TC_AW-1:0]     t3_wb_adr_o;
475
output  [`TC_BSW-1:0]    t3_wb_sel_o;
476
output                  t3_wb_we_o;
477
output  [`TC_DW-1:0]     t3_wb_dat_o;
478
input   [`TC_DW-1:0]     t3_wb_dat_i;
479
input                   t3_wb_ack_i;
480
input                   t3_wb_err_i;
481
 
482
//
483
// WB master i/f connecting target 4
484
//
485
output                  t4_wb_cyc_o;
486
output                  t4_wb_stb_o;
487
output                  t4_wb_cab_o;
488
output  [`TC_AW-1:0]     t4_wb_adr_o;
489
output  [`TC_BSW-1:0]    t4_wb_sel_o;
490
output                  t4_wb_we_o;
491
output  [`TC_DW-1:0]     t4_wb_dat_o;
492
input   [`TC_DW-1:0]     t4_wb_dat_i;
493
input                   t4_wb_ack_i;
494
input                   t4_wb_err_i;
495
 
496
//
497
// WB master i/f connecting target 5
498
//
499
output                  t5_wb_cyc_o;
500
output                  t5_wb_stb_o;
501
output                  t5_wb_cab_o;
502
output  [`TC_AW-1:0]     t5_wb_adr_o;
503
output  [`TC_BSW-1:0]    t5_wb_sel_o;
504
output                  t5_wb_we_o;
505
output  [`TC_DW-1:0]     t5_wb_dat_o;
506
input   [`TC_DW-1:0]     t5_wb_dat_i;
507
input                   t5_wb_ack_i;
508
input                   t5_wb_err_i;
509
 
510
//
511
// WB master i/f connecting target 6
512
//
513
output                  t6_wb_cyc_o;
514
output                  t6_wb_stb_o;
515
output                  t6_wb_cab_o;
516
output  [`TC_AW-1:0]     t6_wb_adr_o;
517
output  [`TC_BSW-1:0]    t6_wb_sel_o;
518
output                  t6_wb_we_o;
519
output  [`TC_DW-1:0]     t6_wb_dat_o;
520
input   [`TC_DW-1:0]     t6_wb_dat_i;
521
input                   t6_wb_ack_i;
522
input                   t6_wb_err_i;
523
 
524
//
525
// WB master i/f connecting target 7
526
//
527
output                  t7_wb_cyc_o;
528
output                  t7_wb_stb_o;
529
output                  t7_wb_cab_o;
530
output  [`TC_AW-1:0]     t7_wb_adr_o;
531
output  [`TC_BSW-1:0]    t7_wb_sel_o;
532
output                  t7_wb_we_o;
533
output  [`TC_DW-1:0]     t7_wb_dat_o;
534
input   [`TC_DW-1:0]     t7_wb_dat_i;
535
input                   t7_wb_ack_i;
536
input                   t7_wb_err_i;
537
 
538
//
539
// WB master i/f connecting target 8
540
//
541
output                  t8_wb_cyc_o;
542
output                  t8_wb_stb_o;
543
output                  t8_wb_cab_o;
544
output  [`TC_AW-1:0]     t8_wb_adr_o;
545
output  [`TC_BSW-1:0]    t8_wb_sel_o;
546
output                  t8_wb_we_o;
547
output  [`TC_DW-1:0]     t8_wb_dat_o;
548
input   [`TC_DW-1:0]     t8_wb_dat_i;
549
input                   t8_wb_ack_i;
550
input                   t8_wb_err_i;
551
 
552
//
553
// Internal wires & registers
554
//
555
 
556
//
557
// Outputs for initiators from both mi_to_st blocks
558
//
559
wire    [`TC_DW-1:0]     xi0_wb_dat_o;
560
wire                    xi0_wb_ack_o;
561
wire                    xi0_wb_err_o;
562
wire    [`TC_DW-1:0]     xi1_wb_dat_o;
563
wire                    xi1_wb_ack_o;
564
wire                    xi1_wb_err_o;
565
wire    [`TC_DW-1:0]     xi2_wb_dat_o;
566
wire                    xi2_wb_ack_o;
567
wire                    xi2_wb_err_o;
568
wire    [`TC_DW-1:0]     xi3_wb_dat_o;
569
wire                    xi3_wb_ack_o;
570
wire                    xi3_wb_err_o;
571
wire    [`TC_DW-1:0]     xi4_wb_dat_o;
572
wire                    xi4_wb_ack_o;
573
wire                    xi4_wb_err_o;
574
wire    [`TC_DW-1:0]     xi5_wb_dat_o;
575
wire                    xi5_wb_ack_o;
576
wire                    xi5_wb_err_o;
577
wire    [`TC_DW-1:0]     xi6_wb_dat_o;
578
wire                    xi6_wb_ack_o;
579
wire                    xi6_wb_err_o;
580
wire    [`TC_DW-1:0]     xi7_wb_dat_o;
581
wire                    xi7_wb_ack_o;
582
wire                    xi7_wb_err_o;
583
wire    [`TC_DW-1:0]     yi0_wb_dat_o;
584
wire                    yi0_wb_ack_o;
585
wire                    yi0_wb_err_o;
586
wire    [`TC_DW-1:0]     yi1_wb_dat_o;
587
wire                    yi1_wb_ack_o;
588
wire                    yi1_wb_err_o;
589
wire    [`TC_DW-1:0]     yi2_wb_dat_o;
590
wire                    yi2_wb_ack_o;
591
wire                    yi2_wb_err_o;
592
wire    [`TC_DW-1:0]     yi3_wb_dat_o;
593
wire                    yi3_wb_ack_o;
594
wire                    yi3_wb_err_o;
595
wire    [`TC_DW-1:0]     yi4_wb_dat_o;
596
wire                    yi4_wb_ack_o;
597
wire                    yi4_wb_err_o;
598
wire    [`TC_DW-1:0]     yi5_wb_dat_o;
599
wire                    yi5_wb_ack_o;
600
wire                    yi5_wb_err_o;
601
wire    [`TC_DW-1:0]     yi6_wb_dat_o;
602
wire                    yi6_wb_ack_o;
603
wire                    yi6_wb_err_o;
604
wire    [`TC_DW-1:0]     yi7_wb_dat_o;
605
wire                    yi7_wb_ack_o;
606
wire                    yi7_wb_err_o;
607
 
608
//
609
// Intermediate signals connecting peripheral channel's
610
// mi_to_st and si_to_mt blocks.
611
//
612
wire                    z_wb_cyc_i;
613
wire                    z_wb_stb_i;
614
wire                    z_wb_cab_i;
615
wire    [`TC_AW-1:0]     z_wb_adr_i;
616
wire    [`TC_BSW-1:0]    z_wb_sel_i;
617
wire                    z_wb_we_i;
618
wire    [`TC_DW-1:0]     z_wb_dat_i;
619
wire    [`TC_DW-1:0]     z_wb_dat_t;
620
wire                    z_wb_ack_t;
621
wire                    z_wb_err_t;
622
 
623
//
624
// Outputs for initiators are ORed from both mi_to_st blocks
625
//
626
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
627
assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
628
assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o;
629
assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o;
630
assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o;
631
assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o;
632
assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o;
633
assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o;
634
assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o;
635
assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o;
636
assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o;
637
assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o;
638
assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o;
639
assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o;
640
assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o;
641
assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o;
642
assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o;
643
assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o;
644
assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o;
645
assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o;
646
assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o;
647
assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o;
648
assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o;
649
assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o;
650
 
651
//
652
// From initiators to target 0
653
//
654
tc_mi_to_st #(t0_addr_w, t0_addr,
655
        0, t0_addr_w, t0_addr) t0_ch(
656
        .wb_clk_i(wb_clk_i),
657
        .wb_rst_i(wb_rst_i),
658
 
659
        .i0_wb_cyc_i(i0_wb_cyc_i),
660
        .i0_wb_stb_i(i0_wb_stb_i),
661
        .i0_wb_cab_i(i0_wb_cab_i),
662
        .i0_wb_adr_i(i0_wb_adr_i),
663
        .i0_wb_sel_i(i0_wb_sel_i),
664
        .i0_wb_we_i(i0_wb_we_i),
665
        .i0_wb_dat_i(i0_wb_dat_i),
666
        .i0_wb_dat_o(xi0_wb_dat_o),
667
        .i0_wb_ack_o(xi0_wb_ack_o),
668
        .i0_wb_err_o(xi0_wb_err_o),
669
 
670
        .i1_wb_cyc_i(i1_wb_cyc_i),
671
        .i1_wb_stb_i(i1_wb_stb_i),
672
        .i1_wb_cab_i(i1_wb_cab_i),
673
        .i1_wb_adr_i(i1_wb_adr_i),
674
        .i1_wb_sel_i(i1_wb_sel_i),
675
        .i1_wb_we_i(i1_wb_we_i),
676
        .i1_wb_dat_i(i1_wb_dat_i),
677
        .i1_wb_dat_o(xi1_wb_dat_o),
678
        .i1_wb_ack_o(xi1_wb_ack_o),
679
        .i1_wb_err_o(xi1_wb_err_o),
680
 
681
        .i2_wb_cyc_i(i2_wb_cyc_i),
682
        .i2_wb_stb_i(i2_wb_stb_i),
683
        .i2_wb_cab_i(i2_wb_cab_i),
684
        .i2_wb_adr_i(i2_wb_adr_i),
685
        .i2_wb_sel_i(i2_wb_sel_i),
686
        .i2_wb_we_i(i2_wb_we_i),
687
        .i2_wb_dat_i(i2_wb_dat_i),
688
        .i2_wb_dat_o(xi2_wb_dat_o),
689
        .i2_wb_ack_o(xi2_wb_ack_o),
690
        .i2_wb_err_o(xi2_wb_err_o),
691
 
692
        .i3_wb_cyc_i(i3_wb_cyc_i),
693
        .i3_wb_stb_i(i3_wb_stb_i),
694
        .i3_wb_cab_i(i3_wb_cab_i),
695
        .i3_wb_adr_i(i3_wb_adr_i),
696
        .i3_wb_sel_i(i3_wb_sel_i),
697
        .i3_wb_we_i(i3_wb_we_i),
698
        .i3_wb_dat_i(i3_wb_dat_i),
699
        .i3_wb_dat_o(xi3_wb_dat_o),
700
        .i3_wb_ack_o(xi3_wb_ack_o),
701
        .i3_wb_err_o(xi3_wb_err_o),
702
 
703
        .i4_wb_cyc_i(i4_wb_cyc_i),
704
        .i4_wb_stb_i(i4_wb_stb_i),
705
        .i4_wb_cab_i(i4_wb_cab_i),
706
        .i4_wb_adr_i(i4_wb_adr_i),
707
        .i4_wb_sel_i(i4_wb_sel_i),
708
        .i4_wb_we_i(i4_wb_we_i),
709
        .i4_wb_dat_i(i4_wb_dat_i),
710
        .i4_wb_dat_o(xi4_wb_dat_o),
711
        .i4_wb_ack_o(xi4_wb_ack_o),
712
        .i4_wb_err_o(xi4_wb_err_o),
713
 
714
        .i5_wb_cyc_i(i5_wb_cyc_i),
715
        .i5_wb_stb_i(i5_wb_stb_i),
716
        .i5_wb_cab_i(i5_wb_cab_i),
717
        .i5_wb_adr_i(i5_wb_adr_i),
718
        .i5_wb_sel_i(i5_wb_sel_i),
719
        .i5_wb_we_i(i5_wb_we_i),
720
        .i5_wb_dat_i(i5_wb_dat_i),
721
        .i5_wb_dat_o(xi5_wb_dat_o),
722
        .i5_wb_ack_o(xi5_wb_ack_o),
723
        .i5_wb_err_o(xi5_wb_err_o),
724
 
725
        .i6_wb_cyc_i(i6_wb_cyc_i),
726
        .i6_wb_stb_i(i6_wb_stb_i),
727
        .i6_wb_cab_i(i6_wb_cab_i),
728
        .i6_wb_adr_i(i6_wb_adr_i),
729
        .i6_wb_sel_i(i6_wb_sel_i),
730
        .i6_wb_we_i(i6_wb_we_i),
731
        .i6_wb_dat_i(i6_wb_dat_i),
732
        .i6_wb_dat_o(xi6_wb_dat_o),
733
        .i6_wb_ack_o(xi6_wb_ack_o),
734
        .i6_wb_err_o(xi6_wb_err_o),
735
 
736
        .i7_wb_cyc_i(i7_wb_cyc_i),
737
        .i7_wb_stb_i(i7_wb_stb_i),
738
        .i7_wb_cab_i(i7_wb_cab_i),
739
        .i7_wb_adr_i(i7_wb_adr_i),
740
        .i7_wb_sel_i(i7_wb_sel_i),
741
        .i7_wb_we_i(i7_wb_we_i),
742
        .i7_wb_dat_i(i7_wb_dat_i),
743
        .i7_wb_dat_o(xi7_wb_dat_o),
744
        .i7_wb_ack_o(xi7_wb_ack_o),
745
        .i7_wb_err_o(xi7_wb_err_o),
746
 
747
        .t0_wb_cyc_o(t0_wb_cyc_o),
748
        .t0_wb_stb_o(t0_wb_stb_o),
749
        .t0_wb_cab_o(t0_wb_cab_o),
750
        .t0_wb_adr_o(t0_wb_adr_o),
751
        .t0_wb_sel_o(t0_wb_sel_o),
752
        .t0_wb_we_o(t0_wb_we_o),
753
        .t0_wb_dat_o(t0_wb_dat_o),
754
        .t0_wb_dat_i(t0_wb_dat_i),
755
        .t0_wb_ack_i(t0_wb_ack_i),
756
        .t0_wb_err_i(t0_wb_err_i)
757
 
758
);
759
 
760
//
761
// From initiators to targets 1-8 (upper part)
762
//
763
tc_mi_to_st #(t1_addr_w, t1_addr,
764
        1, t28c_addr_w, t28_addr) t18_ch_upper(
765
        .wb_clk_i(wb_clk_i),
766
        .wb_rst_i(wb_rst_i),
767
 
768
        .i0_wb_cyc_i(i0_wb_cyc_i),
769
        .i0_wb_stb_i(i0_wb_stb_i),
770
        .i0_wb_cab_i(i0_wb_cab_i),
771
        .i0_wb_adr_i(i0_wb_adr_i),
772
        .i0_wb_sel_i(i0_wb_sel_i),
773
        .i0_wb_we_i(i0_wb_we_i),
774
        .i0_wb_dat_i(i0_wb_dat_i),
775
        .i0_wb_dat_o(yi0_wb_dat_o),
776
        .i0_wb_ack_o(yi0_wb_ack_o),
777
        .i0_wb_err_o(yi0_wb_err_o),
778
 
779
        .i1_wb_cyc_i(i1_wb_cyc_i),
780
        .i1_wb_stb_i(i1_wb_stb_i),
781
        .i1_wb_cab_i(i1_wb_cab_i),
782
        .i1_wb_adr_i(i1_wb_adr_i),
783
        .i1_wb_sel_i(i1_wb_sel_i),
784
        .i1_wb_we_i(i1_wb_we_i),
785
        .i1_wb_dat_i(i1_wb_dat_i),
786
        .i1_wb_dat_o(yi1_wb_dat_o),
787
        .i1_wb_ack_o(yi1_wb_ack_o),
788
        .i1_wb_err_o(yi1_wb_err_o),
789
 
790
        .i2_wb_cyc_i(i2_wb_cyc_i),
791
        .i2_wb_stb_i(i2_wb_stb_i),
792
        .i2_wb_cab_i(i2_wb_cab_i),
793
        .i2_wb_adr_i(i2_wb_adr_i),
794
        .i2_wb_sel_i(i2_wb_sel_i),
795
        .i2_wb_we_i(i2_wb_we_i),
796
        .i2_wb_dat_i(i2_wb_dat_i),
797
        .i2_wb_dat_o(yi2_wb_dat_o),
798
        .i2_wb_ack_o(yi2_wb_ack_o),
799
        .i2_wb_err_o(yi2_wb_err_o),
800
 
801
        .i3_wb_cyc_i(i3_wb_cyc_i),
802
        .i3_wb_stb_i(i3_wb_stb_i),
803
        .i3_wb_cab_i(i3_wb_cab_i),
804
        .i3_wb_adr_i(i3_wb_adr_i),
805
        .i3_wb_sel_i(i3_wb_sel_i),
806
        .i3_wb_we_i(i3_wb_we_i),
807
        .i3_wb_dat_i(i3_wb_dat_i),
808
        .i3_wb_dat_o(yi3_wb_dat_o),
809
        .i3_wb_ack_o(yi3_wb_ack_o),
810
        .i3_wb_err_o(yi3_wb_err_o),
811
 
812
        .i4_wb_cyc_i(i4_wb_cyc_i),
813
        .i4_wb_stb_i(i4_wb_stb_i),
814
        .i4_wb_cab_i(i4_wb_cab_i),
815
        .i4_wb_adr_i(i4_wb_adr_i),
816
        .i4_wb_sel_i(i4_wb_sel_i),
817
        .i4_wb_we_i(i4_wb_we_i),
818
        .i4_wb_dat_i(i4_wb_dat_i),
819
        .i4_wb_dat_o(yi4_wb_dat_o),
820
        .i4_wb_ack_o(yi4_wb_ack_o),
821
        .i4_wb_err_o(yi4_wb_err_o),
822
 
823
        .i5_wb_cyc_i(i5_wb_cyc_i),
824
        .i5_wb_stb_i(i5_wb_stb_i),
825
        .i5_wb_cab_i(i5_wb_cab_i),
826
        .i5_wb_adr_i(i5_wb_adr_i),
827
        .i5_wb_sel_i(i5_wb_sel_i),
828
        .i5_wb_we_i(i5_wb_we_i),
829
        .i5_wb_dat_i(i5_wb_dat_i),
830
        .i5_wb_dat_o(yi5_wb_dat_o),
831
        .i5_wb_ack_o(yi5_wb_ack_o),
832
        .i5_wb_err_o(yi5_wb_err_o),
833
 
834
        .i6_wb_cyc_i(i6_wb_cyc_i),
835
        .i6_wb_stb_i(i6_wb_stb_i),
836
        .i6_wb_cab_i(i6_wb_cab_i),
837
        .i6_wb_adr_i(i6_wb_adr_i),
838
        .i6_wb_sel_i(i6_wb_sel_i),
839
        .i6_wb_we_i(i6_wb_we_i),
840
        .i6_wb_dat_i(i6_wb_dat_i),
841
        .i6_wb_dat_o(yi6_wb_dat_o),
842
        .i6_wb_ack_o(yi6_wb_ack_o),
843
        .i6_wb_err_o(yi6_wb_err_o),
844
 
845
        .i7_wb_cyc_i(i7_wb_cyc_i),
846
        .i7_wb_stb_i(i7_wb_stb_i),
847
        .i7_wb_cab_i(i7_wb_cab_i),
848
        .i7_wb_adr_i(i7_wb_adr_i),
849
        .i7_wb_sel_i(i7_wb_sel_i),
850
        .i7_wb_we_i(i7_wb_we_i),
851
        .i7_wb_dat_i(i7_wb_dat_i),
852
        .i7_wb_dat_o(yi7_wb_dat_o),
853
        .i7_wb_ack_o(yi7_wb_ack_o),
854
        .i7_wb_err_o(yi7_wb_err_o),
855
 
856
        .t0_wb_cyc_o(z_wb_cyc_i),
857
        .t0_wb_stb_o(z_wb_stb_i),
858
        .t0_wb_cab_o(z_wb_cab_i),
859
        .t0_wb_adr_o(z_wb_adr_i),
860
        .t0_wb_sel_o(z_wb_sel_i),
861
        .t0_wb_we_o(z_wb_we_i),
862
        .t0_wb_dat_o(z_wb_dat_i),
863
        .t0_wb_dat_i(z_wb_dat_t),
864
        .t0_wb_ack_i(z_wb_ack_t),
865
        .t0_wb_err_i(z_wb_err_t)
866
 
867
);
868
 
869
//
870
// From initiators to targets 1-8 (lower part)
871
//
872
tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,
873
        t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(
874
 
875
        .i0_wb_cyc_i(z_wb_cyc_i),
876
        .i0_wb_stb_i(z_wb_stb_i),
877
        .i0_wb_cab_i(z_wb_cab_i),
878
        .i0_wb_adr_i(z_wb_adr_i),
879
        .i0_wb_sel_i(z_wb_sel_i),
880
        .i0_wb_we_i(z_wb_we_i),
881
        .i0_wb_dat_i(z_wb_dat_i),
882
        .i0_wb_dat_o(z_wb_dat_t),
883
        .i0_wb_ack_o(z_wb_ack_t),
884
        .i0_wb_err_o(z_wb_err_t),
885
 
886
        .t0_wb_cyc_o(t1_wb_cyc_o),
887
        .t0_wb_stb_o(t1_wb_stb_o),
888
        .t0_wb_cab_o(t1_wb_cab_o),
889
        .t0_wb_adr_o(t1_wb_adr_o),
890
        .t0_wb_sel_o(t1_wb_sel_o),
891
        .t0_wb_we_o(t1_wb_we_o),
892
        .t0_wb_dat_o(t1_wb_dat_o),
893
        .t0_wb_dat_i(t1_wb_dat_i),
894
        .t0_wb_ack_i(t1_wb_ack_i),
895
        .t0_wb_err_i(t1_wb_err_i),
896
 
897
        .t1_wb_cyc_o(t2_wb_cyc_o),
898
        .t1_wb_stb_o(t2_wb_stb_o),
899
        .t1_wb_cab_o(t2_wb_cab_o),
900
        .t1_wb_adr_o(t2_wb_adr_o),
901
        .t1_wb_sel_o(t2_wb_sel_o),
902
        .t1_wb_we_o(t2_wb_we_o),
903
        .t1_wb_dat_o(t2_wb_dat_o),
904
        .t1_wb_dat_i(t2_wb_dat_i),
905
        .t1_wb_ack_i(t2_wb_ack_i),
906
        .t1_wb_err_i(t2_wb_err_i),
907
 
908
        .t2_wb_cyc_o(t3_wb_cyc_o),
909
        .t2_wb_stb_o(t3_wb_stb_o),
910
        .t2_wb_cab_o(t3_wb_cab_o),
911
        .t2_wb_adr_o(t3_wb_adr_o),
912
        .t2_wb_sel_o(t3_wb_sel_o),
913
        .t2_wb_we_o(t3_wb_we_o),
914
        .t2_wb_dat_o(t3_wb_dat_o),
915
        .t2_wb_dat_i(t3_wb_dat_i),
916
        .t2_wb_ack_i(t3_wb_ack_i),
917
        .t2_wb_err_i(t3_wb_err_i),
918
 
919
        .t3_wb_cyc_o(t4_wb_cyc_o),
920
        .t3_wb_stb_o(t4_wb_stb_o),
921
        .t3_wb_cab_o(t4_wb_cab_o),
922
        .t3_wb_adr_o(t4_wb_adr_o),
923
        .t3_wb_sel_o(t4_wb_sel_o),
924
        .t3_wb_we_o(t4_wb_we_o),
925
        .t3_wb_dat_o(t4_wb_dat_o),
926
        .t3_wb_dat_i(t4_wb_dat_i),
927
        .t3_wb_ack_i(t4_wb_ack_i),
928
        .t3_wb_err_i(t4_wb_err_i),
929
 
930
        .t4_wb_cyc_o(t5_wb_cyc_o),
931
        .t4_wb_stb_o(t5_wb_stb_o),
932
        .t4_wb_cab_o(t5_wb_cab_o),
933
        .t4_wb_adr_o(t5_wb_adr_o),
934
        .t4_wb_sel_o(t5_wb_sel_o),
935
        .t4_wb_we_o(t5_wb_we_o),
936
        .t4_wb_dat_o(t5_wb_dat_o),
937
        .t4_wb_dat_i(t5_wb_dat_i),
938
        .t4_wb_ack_i(t5_wb_ack_i),
939
        .t4_wb_err_i(t5_wb_err_i),
940
 
941
        .t5_wb_cyc_o(t6_wb_cyc_o),
942
        .t5_wb_stb_o(t6_wb_stb_o),
943
        .t5_wb_cab_o(t6_wb_cab_o),
944
        .t5_wb_adr_o(t6_wb_adr_o),
945
        .t5_wb_sel_o(t6_wb_sel_o),
946
        .t5_wb_we_o(t6_wb_we_o),
947
        .t5_wb_dat_o(t6_wb_dat_o),
948
        .t5_wb_dat_i(t6_wb_dat_i),
949
        .t5_wb_ack_i(t6_wb_ack_i),
950
        .t5_wb_err_i(t6_wb_err_i),
951
 
952
        .t6_wb_cyc_o(t7_wb_cyc_o),
953
        .t6_wb_stb_o(t7_wb_stb_o),
954
        .t6_wb_cab_o(t7_wb_cab_o),
955
        .t6_wb_adr_o(t7_wb_adr_o),
956
        .t6_wb_sel_o(t7_wb_sel_o),
957
        .t6_wb_we_o(t7_wb_we_o),
958
        .t6_wb_dat_o(t7_wb_dat_o),
959
        .t6_wb_dat_i(t7_wb_dat_i),
960
        .t6_wb_ack_i(t7_wb_ack_i),
961
        .t6_wb_err_i(t7_wb_err_i),
962
 
963
        .t7_wb_cyc_o(t8_wb_cyc_o),
964
        .t7_wb_stb_o(t8_wb_stb_o),
965
        .t7_wb_cab_o(t8_wb_cab_o),
966
        .t7_wb_adr_o(t8_wb_adr_o),
967
        .t7_wb_sel_o(t8_wb_sel_o),
968
        .t7_wb_we_o(t8_wb_we_o),
969
        .t7_wb_dat_o(t8_wb_dat_o),
970
        .t7_wb_dat_i(t8_wb_dat_i),
971
        .t7_wb_ack_i(t8_wb_ack_i),
972
        .t7_wb_err_i(t8_wb_err_i)
973
 
974
);
975
 
976
endmodule
977
 
978
//
979
// Multiple initiator to single target
980
//
981
module tc_mi_to_st (
982
        wb_clk_i,
983
        wb_rst_i,
984
 
985
        i0_wb_cyc_i,
986
        i0_wb_stb_i,
987
        i0_wb_cab_i,
988
        i0_wb_adr_i,
989
        i0_wb_sel_i,
990
        i0_wb_we_i,
991
        i0_wb_dat_i,
992
        i0_wb_dat_o,
993
        i0_wb_ack_o,
994
        i0_wb_err_o,
995
 
996
        i1_wb_cyc_i,
997
        i1_wb_stb_i,
998
        i1_wb_cab_i,
999
        i1_wb_adr_i,
1000
        i1_wb_sel_i,
1001
        i1_wb_we_i,
1002
        i1_wb_dat_i,
1003
        i1_wb_dat_o,
1004
        i1_wb_ack_o,
1005
        i1_wb_err_o,
1006
 
1007
        i2_wb_cyc_i,
1008
        i2_wb_stb_i,
1009
        i2_wb_cab_i,
1010
        i2_wb_adr_i,
1011
        i2_wb_sel_i,
1012
        i2_wb_we_i,
1013
        i2_wb_dat_i,
1014
        i2_wb_dat_o,
1015
        i2_wb_ack_o,
1016
        i2_wb_err_o,
1017
 
1018
        i3_wb_cyc_i,
1019
        i3_wb_stb_i,
1020
        i3_wb_cab_i,
1021
        i3_wb_adr_i,
1022
        i3_wb_sel_i,
1023
        i3_wb_we_i,
1024
        i3_wb_dat_i,
1025
        i3_wb_dat_o,
1026
        i3_wb_ack_o,
1027
        i3_wb_err_o,
1028
 
1029
        i4_wb_cyc_i,
1030
        i4_wb_stb_i,
1031
        i4_wb_cab_i,
1032
        i4_wb_adr_i,
1033
        i4_wb_sel_i,
1034
        i4_wb_we_i,
1035
        i4_wb_dat_i,
1036
        i4_wb_dat_o,
1037
        i4_wb_ack_o,
1038
        i4_wb_err_o,
1039
 
1040
        i5_wb_cyc_i,
1041
        i5_wb_stb_i,
1042
        i5_wb_cab_i,
1043
        i5_wb_adr_i,
1044
        i5_wb_sel_i,
1045
        i5_wb_we_i,
1046
        i5_wb_dat_i,
1047
        i5_wb_dat_o,
1048
        i5_wb_ack_o,
1049
        i5_wb_err_o,
1050
 
1051
        i6_wb_cyc_i,
1052
        i6_wb_stb_i,
1053
        i6_wb_cab_i,
1054
        i6_wb_adr_i,
1055
        i6_wb_sel_i,
1056
        i6_wb_we_i,
1057
        i6_wb_dat_i,
1058
        i6_wb_dat_o,
1059
        i6_wb_ack_o,
1060
        i6_wb_err_o,
1061
 
1062
        i7_wb_cyc_i,
1063
        i7_wb_stb_i,
1064
        i7_wb_cab_i,
1065
        i7_wb_adr_i,
1066
        i7_wb_sel_i,
1067
        i7_wb_we_i,
1068
        i7_wb_dat_i,
1069
        i7_wb_dat_o,
1070
        i7_wb_ack_o,
1071
        i7_wb_err_o,
1072
 
1073
        t0_wb_cyc_o,
1074
        t0_wb_stb_o,
1075
        t0_wb_cab_o,
1076
        t0_wb_adr_o,
1077
        t0_wb_sel_o,
1078
        t0_wb_we_o,
1079
        t0_wb_dat_o,
1080
        t0_wb_dat_i,
1081
        t0_wb_ack_i,
1082
        t0_wb_err_i
1083
 
1084
);
1085
 
1086
//
1087
// Parameters
1088
//
1089
parameter               t0_addr_w = 2;
1090
parameter               t0_addr = 2'b00;
1091
parameter               multitarg = 1'b0;
1092
parameter               t17_addr_w = 2;
1093
parameter               t17_addr = 2'b00;
1094
 
1095
//
1096
// I/O Ports
1097
//
1098
input                   wb_clk_i;
1099
input                   wb_rst_i;
1100
 
1101
//
1102
// WB slave i/f connecting initiator 0
1103
//
1104
input                   i0_wb_cyc_i;
1105
input                   i0_wb_stb_i;
1106
input                   i0_wb_cab_i;
1107
input   [`TC_AW-1:0]     i0_wb_adr_i;
1108
input   [`TC_BSW-1:0]    i0_wb_sel_i;
1109
input                   i0_wb_we_i;
1110
input   [`TC_DW-1:0]     i0_wb_dat_i;
1111
output  [`TC_DW-1:0]     i0_wb_dat_o;
1112
output                  i0_wb_ack_o;
1113
output                  i0_wb_err_o;
1114
 
1115
//
1116
// WB slave i/f connecting initiator 1
1117
//
1118
input                   i1_wb_cyc_i;
1119
input                   i1_wb_stb_i;
1120
input                   i1_wb_cab_i;
1121
input   [`TC_AW-1:0]     i1_wb_adr_i;
1122
input   [`TC_BSW-1:0]    i1_wb_sel_i;
1123
input                   i1_wb_we_i;
1124
input   [`TC_DW-1:0]     i1_wb_dat_i;
1125
output  [`TC_DW-1:0]     i1_wb_dat_o;
1126
output                  i1_wb_ack_o;
1127
output                  i1_wb_err_o;
1128
 
1129
//
1130
// WB slave i/f connecting initiator 2
1131
//
1132
input                   i2_wb_cyc_i;
1133
input                   i2_wb_stb_i;
1134
input                   i2_wb_cab_i;
1135
input   [`TC_AW-1:0]     i2_wb_adr_i;
1136
input   [`TC_BSW-1:0]    i2_wb_sel_i;
1137
input                   i2_wb_we_i;
1138
input   [`TC_DW-1:0]     i2_wb_dat_i;
1139
output  [`TC_DW-1:0]     i2_wb_dat_o;
1140
output                  i2_wb_ack_o;
1141
output                  i2_wb_err_o;
1142
 
1143
//
1144
// WB slave i/f connecting initiator 3
1145
//
1146
input                   i3_wb_cyc_i;
1147
input                   i3_wb_stb_i;
1148
input                   i3_wb_cab_i;
1149
input   [`TC_AW-1:0]     i3_wb_adr_i;
1150
input   [`TC_BSW-1:0]    i3_wb_sel_i;
1151
input                   i3_wb_we_i;
1152
input   [`TC_DW-1:0]     i3_wb_dat_i;
1153
output  [`TC_DW-1:0]     i3_wb_dat_o;
1154
output                  i3_wb_ack_o;
1155
output                  i3_wb_err_o;
1156
 
1157
//
1158
// WB slave i/f connecting initiator 4
1159
//
1160
input                   i4_wb_cyc_i;
1161
input                   i4_wb_stb_i;
1162
input                   i4_wb_cab_i;
1163
input   [`TC_AW-1:0]     i4_wb_adr_i;
1164
input   [`TC_BSW-1:0]    i4_wb_sel_i;
1165
input                   i4_wb_we_i;
1166
input   [`TC_DW-1:0]     i4_wb_dat_i;
1167
output  [`TC_DW-1:0]     i4_wb_dat_o;
1168
output                  i4_wb_ack_o;
1169
output                  i4_wb_err_o;
1170
 
1171
//
1172
// WB slave i/f connecting initiator 5
1173
//
1174
input                   i5_wb_cyc_i;
1175
input                   i5_wb_stb_i;
1176
input                   i5_wb_cab_i;
1177
input   [`TC_AW-1:0]     i5_wb_adr_i;
1178
input   [`TC_BSW-1:0]    i5_wb_sel_i;
1179
input                   i5_wb_we_i;
1180
input   [`TC_DW-1:0]     i5_wb_dat_i;
1181
output  [`TC_DW-1:0]     i5_wb_dat_o;
1182
output                  i5_wb_ack_o;
1183
output                  i5_wb_err_o;
1184
 
1185
//
1186
// WB slave i/f connecting initiator 6
1187
//
1188
input                   i6_wb_cyc_i;
1189
input                   i6_wb_stb_i;
1190
input                   i6_wb_cab_i;
1191
input   [`TC_AW-1:0]     i6_wb_adr_i;
1192
input   [`TC_BSW-1:0]    i6_wb_sel_i;
1193
input                   i6_wb_we_i;
1194
input   [`TC_DW-1:0]     i6_wb_dat_i;
1195
output  [`TC_DW-1:0]     i6_wb_dat_o;
1196
output                  i6_wb_ack_o;
1197
output                  i6_wb_err_o;
1198
 
1199
//
1200
// WB slave i/f connecting initiator 7
1201
//
1202
input                   i7_wb_cyc_i;
1203
input                   i7_wb_stb_i;
1204
input                   i7_wb_cab_i;
1205
input   [`TC_AW-1:0]     i7_wb_adr_i;
1206
input   [`TC_BSW-1:0]    i7_wb_sel_i;
1207
input                   i7_wb_we_i;
1208
input   [`TC_DW-1:0]     i7_wb_dat_i;
1209
output  [`TC_DW-1:0]     i7_wb_dat_o;
1210
output                  i7_wb_ack_o;
1211
output                  i7_wb_err_o;
1212
 
1213
//
1214
// WB master i/f connecting target
1215
//
1216
output                  t0_wb_cyc_o;
1217
output                  t0_wb_stb_o;
1218
output                  t0_wb_cab_o;
1219
output  [`TC_AW-1:0]     t0_wb_adr_o;
1220
output  [`TC_BSW-1:0]    t0_wb_sel_o;
1221
output                  t0_wb_we_o;
1222
output  [`TC_DW-1:0]     t0_wb_dat_o;
1223
input   [`TC_DW-1:0]     t0_wb_dat_i;
1224
input                   t0_wb_ack_i;
1225
input                   t0_wb_err_i;
1226
 
1227
//
1228
// Internal wires & registers
1229
//
1230
wire    [`TC_IIN_W-1:0]  i0_in, i1_in,
1231
                        i2_in, i3_in,
1232
                        i4_in, i5_in,
1233
                        i6_in, i7_in;
1234
wire    [`TC_TIN_W-1:0]  i0_out, i1_out,
1235
                        i2_out, i3_out,
1236
                        i4_out, i5_out,
1237
                        i6_out, i7_out;
1238
wire    [`TC_IIN_W-1:0]  t0_out;
1239
wire    [`TC_TIN_W-1:0]  t0_in;
1240
wire    [7:0]            req_i;
1241
wire    [2:0]            req_won;
1242
reg                     req_cont;
1243
reg     [2:0]            req_r;
1244
 
1245
//
1246
// Group WB initiator 0 i/f inputs and outputs
1247
//
1248
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_cab_i, i0_wb_adr_i,
1249
                i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i};
1250
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
1251
 
1252
//
1253
// Group WB initiator 1 i/f inputs and outputs
1254
//
1255
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_cab_i, i1_wb_adr_i,
1256
                i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i};
1257
assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out;
1258
 
1259
//
1260
// Group WB initiator 2 i/f inputs and outputs
1261
//
1262
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_cab_i, i2_wb_adr_i,
1263
                i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i};
1264
assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out;
1265
 
1266
//
1267
// Group WB initiator 3 i/f inputs and outputs
1268
//
1269
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_cab_i, i3_wb_adr_i,
1270
                i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i};
1271
assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out;
1272
 
1273
//
1274
// Group WB initiator 4 i/f inputs and outputs
1275
//
1276
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_cab_i, i4_wb_adr_i,
1277
                i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i};
1278
assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out;
1279
 
1280
//
1281
// Group WB initiator 5 i/f inputs and outputs
1282
//
1283
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_cab_i, i5_wb_adr_i,
1284
                i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i};
1285
assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out;
1286
 
1287
//
1288
// Group WB initiator 6 i/f inputs and outputs
1289
//
1290
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_cab_i, i6_wb_adr_i,
1291
                i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i};
1292
assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out;
1293
 
1294
//
1295
// Group WB initiator 7 i/f inputs and outputs
1296
//
1297
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_cab_i, i7_wb_adr_i,
1298
                i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i};
1299
assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out;
1300
 
1301
//
1302
// Group WB target 0 i/f inputs and outputs
1303
//
1304
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_cab_o, t0_wb_adr_o,
1305
                t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out;
1306
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
1307
 
1308
//
1309
// Assign to WB initiator i/f outputs
1310
//
1311
// Either inputs from the target are assigned or zeros.
1312
//
1313
assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}};
1314
assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}};
1315
assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}};
1316
assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}};
1317
assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}};
1318
assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}};
1319
assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}};
1320
assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}};
1321
 
1322
//
1323
// Assign to WB target i/f outputs
1324
//
1325
// Assign inputs from initiator to target outputs according to
1326
// which initiator has won. If there is no request for the target,
1327
// assign zeros.
1328
//
1329
assign t0_out = (req_won == 3'd0) ? i0_in :
1330
                (req_won == 3'd1) ? i1_in :
1331
                (req_won == 3'd2) ? i2_in :
1332
                (req_won == 3'd3) ? i3_in :
1333
                (req_won == 3'd4) ? i4_in :
1334
                (req_won == 3'd5) ? i5_in :
1335
                (req_won == 3'd6) ? i6_in :
1336
                (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}};
1337
 
1338
//
1339
// Determine if an initiator has address of the target.
1340
//
1341
assign req_i[0] = i0_wb_cyc_i &
1342
        ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1343
         multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1344
assign req_i[1] = i1_wb_cyc_i &
1345
        ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1346
         multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1347
assign req_i[2] = i2_wb_cyc_i &
1348
        ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1349
         multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1350
assign req_i[3] = i3_wb_cyc_i &
1351
        ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1352
         multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1353
assign req_i[4] = i4_wb_cyc_i &
1354
        ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1355
         multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1356
assign req_i[5] = i5_wb_cyc_i &
1357
        ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1358
         multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1359
assign req_i[6] = i6_wb_cyc_i &
1360
        ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1361
         multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1362
assign req_i[7] = i7_wb_cyc_i &
1363
        ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1364
         multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1365
 
1366
//
1367
// Determine who gets current access to the target.
1368
//
1369
// If current initiator still asserts request, do nothing
1370
// (keep current initiator).
1371
// Otherwise check each initiator's request, starting from initiator 0
1372
// (highest priority).
1373
// If there is no requests from initiators, park initiator 0.
1374
//
1375
assign req_won = req_cont ? req_r :
1376
                 req_i[0] ? 3'd0 :
1377
                 req_i[1] ? 3'd1 :
1378
                 req_i[2] ? 3'd2 :
1379
                 req_i[3] ? 3'd3 :
1380
                 req_i[4] ? 3'd4 :
1381
                 req_i[5] ? 3'd5 :
1382
                 req_i[6] ? 3'd6 :
1383
                 req_i[7] ? 3'd7 : 3'd0;
1384
 
1385
//
1386
// Check if current initiator still wants access to the target and if
1387
// it does, assert req_cont.
1388
//
1389
always @(req_r or req_i)
1390
        case (req_r)    // synopsys parallel_case
1391
                3'd0: req_cont = req_i[0];
1392
                3'd1: req_cont = req_i[1];
1393
                3'd2: req_cont = req_i[2];
1394
                3'd3: req_cont = req_i[3];
1395
                3'd4: req_cont = req_i[4];
1396
                3'd5: req_cont = req_i[5];
1397
                3'd6: req_cont = req_i[6];
1398
                3'd7: req_cont = req_i[7];
1399
        endcase
1400
 
1401
//
1402
// Register who has current access to the target.
1403
//
1404
always @(posedge wb_clk_i or posedge wb_rst_i)
1405
        if (wb_rst_i)
1406
                req_r <= #1 3'd0;
1407
        else
1408
                req_r <= #1 req_won;
1409
 
1410
endmodule
1411
 
1412
//
1413
// Single initiator to multiple targets
1414
//
1415
module tc_si_to_mt (
1416
 
1417
        i0_wb_cyc_i,
1418
        i0_wb_stb_i,
1419
        i0_wb_cab_i,
1420
        i0_wb_adr_i,
1421
        i0_wb_sel_i,
1422
        i0_wb_we_i,
1423
        i0_wb_dat_i,
1424
        i0_wb_dat_o,
1425
        i0_wb_ack_o,
1426
        i0_wb_err_o,
1427
 
1428
        t0_wb_cyc_o,
1429
        t0_wb_stb_o,
1430
        t0_wb_cab_o,
1431
        t0_wb_adr_o,
1432
        t0_wb_sel_o,
1433
        t0_wb_we_o,
1434
        t0_wb_dat_o,
1435
        t0_wb_dat_i,
1436
        t0_wb_ack_i,
1437
        t0_wb_err_i,
1438
 
1439
        t1_wb_cyc_o,
1440
        t1_wb_stb_o,
1441
        t1_wb_cab_o,
1442
        t1_wb_adr_o,
1443
        t1_wb_sel_o,
1444
        t1_wb_we_o,
1445
        t1_wb_dat_o,
1446
        t1_wb_dat_i,
1447
        t1_wb_ack_i,
1448
        t1_wb_err_i,
1449
 
1450
        t2_wb_cyc_o,
1451
        t2_wb_stb_o,
1452
        t2_wb_cab_o,
1453
        t2_wb_adr_o,
1454
        t2_wb_sel_o,
1455
        t2_wb_we_o,
1456
        t2_wb_dat_o,
1457
        t2_wb_dat_i,
1458
        t2_wb_ack_i,
1459
        t2_wb_err_i,
1460
 
1461
        t3_wb_cyc_o,
1462
        t3_wb_stb_o,
1463
        t3_wb_cab_o,
1464
        t3_wb_adr_o,
1465
        t3_wb_sel_o,
1466
        t3_wb_we_o,
1467
        t3_wb_dat_o,
1468
        t3_wb_dat_i,
1469
        t3_wb_ack_i,
1470
        t3_wb_err_i,
1471
 
1472
        t4_wb_cyc_o,
1473
        t4_wb_stb_o,
1474
        t4_wb_cab_o,
1475
        t4_wb_adr_o,
1476
        t4_wb_sel_o,
1477
        t4_wb_we_o,
1478
        t4_wb_dat_o,
1479
        t4_wb_dat_i,
1480
        t4_wb_ack_i,
1481
        t4_wb_err_i,
1482
 
1483
        t5_wb_cyc_o,
1484
        t5_wb_stb_o,
1485
        t5_wb_cab_o,
1486
        t5_wb_adr_o,
1487
        t5_wb_sel_o,
1488
        t5_wb_we_o,
1489
        t5_wb_dat_o,
1490
        t5_wb_dat_i,
1491
        t5_wb_ack_i,
1492
        t5_wb_err_i,
1493
 
1494
        t6_wb_cyc_o,
1495
        t6_wb_stb_o,
1496
        t6_wb_cab_o,
1497
        t6_wb_adr_o,
1498
        t6_wb_sel_o,
1499
        t6_wb_we_o,
1500
        t6_wb_dat_o,
1501
        t6_wb_dat_i,
1502
        t6_wb_ack_i,
1503
        t6_wb_err_i,
1504
 
1505
        t7_wb_cyc_o,
1506
        t7_wb_stb_o,
1507
        t7_wb_cab_o,
1508
        t7_wb_adr_o,
1509
        t7_wb_sel_o,
1510
        t7_wb_we_o,
1511
        t7_wb_dat_o,
1512
        t7_wb_dat_i,
1513
        t7_wb_ack_i,
1514
        t7_wb_err_i
1515
 
1516
);
1517
 
1518
//
1519
// Parameters
1520
//
1521
parameter               t0_addr_w = 3;
1522
parameter               t0_addr = 3'd0;
1523
parameter               t17_addr_w = 3;
1524
parameter               t1_addr = 3'd1;
1525
parameter               t2_addr = 3'd2;
1526
parameter               t3_addr = 3'd3;
1527
parameter               t4_addr = 3'd4;
1528
parameter               t5_addr = 3'd5;
1529
parameter               t6_addr = 3'd6;
1530
parameter               t7_addr = 3'd7;
1531
 
1532
//
1533
// I/O Ports
1534
//
1535
 
1536
//
1537
// WB slave i/f connecting initiator 0
1538
//
1539
input                   i0_wb_cyc_i;
1540
input                   i0_wb_stb_i;
1541
input                   i0_wb_cab_i;
1542
input   [`TC_AW-1:0]     i0_wb_adr_i;
1543
input   [`TC_BSW-1:0]    i0_wb_sel_i;
1544
input                   i0_wb_we_i;
1545
input   [`TC_DW-1:0]     i0_wb_dat_i;
1546
output  [`TC_DW-1:0]     i0_wb_dat_o;
1547
output                  i0_wb_ack_o;
1548
output                  i0_wb_err_o;
1549
 
1550
//
1551
// WB master i/f connecting target 0
1552
//
1553
output                  t0_wb_cyc_o;
1554
output                  t0_wb_stb_o;
1555
output                  t0_wb_cab_o;
1556
output  [`TC_AW-1:0]     t0_wb_adr_o;
1557
output  [`TC_BSW-1:0]    t0_wb_sel_o;
1558
output                  t0_wb_we_o;
1559
output  [`TC_DW-1:0]     t0_wb_dat_o;
1560
input   [`TC_DW-1:0]     t0_wb_dat_i;
1561
input                   t0_wb_ack_i;
1562
input                   t0_wb_err_i;
1563
 
1564
//
1565
// WB master i/f connecting target 1
1566
//
1567
output                  t1_wb_cyc_o;
1568
output                  t1_wb_stb_o;
1569
output                  t1_wb_cab_o;
1570
output  [`TC_AW-1:0]     t1_wb_adr_o;
1571
output  [`TC_BSW-1:0]    t1_wb_sel_o;
1572
output                  t1_wb_we_o;
1573
output  [`TC_DW-1:0]     t1_wb_dat_o;
1574
input   [`TC_DW-1:0]     t1_wb_dat_i;
1575
input                   t1_wb_ack_i;
1576
input                   t1_wb_err_i;
1577
 
1578
//
1579
// WB master i/f connecting target 2
1580
//
1581
output                  t2_wb_cyc_o;
1582
output                  t2_wb_stb_o;
1583
output                  t2_wb_cab_o;
1584
output  [`TC_AW-1:0]     t2_wb_adr_o;
1585
output  [`TC_BSW-1:0]    t2_wb_sel_o;
1586
output                  t2_wb_we_o;
1587
output  [`TC_DW-1:0]     t2_wb_dat_o;
1588
input   [`TC_DW-1:0]     t2_wb_dat_i;
1589
input                   t2_wb_ack_i;
1590
input                   t2_wb_err_i;
1591
 
1592
//
1593
// WB master i/f connecting target 3
1594
//
1595
output                  t3_wb_cyc_o;
1596
output                  t3_wb_stb_o;
1597
output                  t3_wb_cab_o;
1598
output  [`TC_AW-1:0]     t3_wb_adr_o;
1599
output  [`TC_BSW-1:0]    t3_wb_sel_o;
1600
output                  t3_wb_we_o;
1601
output  [`TC_DW-1:0]     t3_wb_dat_o;
1602
input   [`TC_DW-1:0]     t3_wb_dat_i;
1603
input                   t3_wb_ack_i;
1604
input                   t3_wb_err_i;
1605
 
1606
//
1607
// WB master i/f connecting target 4
1608
//
1609
output                  t4_wb_cyc_o;
1610
output                  t4_wb_stb_o;
1611
output                  t4_wb_cab_o;
1612
output  [`TC_AW-1:0]     t4_wb_adr_o;
1613
output  [`TC_BSW-1:0]    t4_wb_sel_o;
1614
output                  t4_wb_we_o;
1615
output  [`TC_DW-1:0]     t4_wb_dat_o;
1616
input   [`TC_DW-1:0]     t4_wb_dat_i;
1617
input                   t4_wb_ack_i;
1618
input                   t4_wb_err_i;
1619
 
1620
//
1621
// WB master i/f connecting target 5
1622
//
1623
output                  t5_wb_cyc_o;
1624
output                  t5_wb_stb_o;
1625
output                  t5_wb_cab_o;
1626
output  [`TC_AW-1:0]     t5_wb_adr_o;
1627
output  [`TC_BSW-1:0]    t5_wb_sel_o;
1628
output                  t5_wb_we_o;
1629
output  [`TC_DW-1:0]     t5_wb_dat_o;
1630
input   [`TC_DW-1:0]     t5_wb_dat_i;
1631
input                   t5_wb_ack_i;
1632
input                   t5_wb_err_i;
1633
 
1634
//
1635
// WB master i/f connecting target 6
1636
//
1637
output                  t6_wb_cyc_o;
1638
output                  t6_wb_stb_o;
1639
output                  t6_wb_cab_o;
1640
output  [`TC_AW-1:0]     t6_wb_adr_o;
1641
output  [`TC_BSW-1:0]    t6_wb_sel_o;
1642
output                  t6_wb_we_o;
1643
output  [`TC_DW-1:0]     t6_wb_dat_o;
1644
input   [`TC_DW-1:0]     t6_wb_dat_i;
1645
input                   t6_wb_ack_i;
1646
input                   t6_wb_err_i;
1647
 
1648
//
1649
// WB master i/f connecting target 7
1650
//
1651
output                  t7_wb_cyc_o;
1652
output                  t7_wb_stb_o;
1653
output                  t7_wb_cab_o;
1654
output  [`TC_AW-1:0]     t7_wb_adr_o;
1655
output  [`TC_BSW-1:0]    t7_wb_sel_o;
1656
output                  t7_wb_we_o;
1657
output  [`TC_DW-1:0]     t7_wb_dat_o;
1658
input   [`TC_DW-1:0]     t7_wb_dat_i;
1659
input                   t7_wb_ack_i;
1660
input                   t7_wb_err_i;
1661
 
1662
//
1663
// Internal wires & registers
1664
//
1665
wire    [`TC_IIN_W-1:0]  i0_in;
1666
wire    [`TC_TIN_W-1:0]  i0_out;
1667
wire    [`TC_IIN_W-1:0]  t0_out, t1_out,
1668
                        t2_out, t3_out,
1669
                        t4_out, t5_out,
1670
                        t6_out, t7_out;
1671
wire    [`TC_TIN_W-1:0]  t0_in, t1_in,
1672
                        t2_in, t3_in,
1673
                        t4_in, t5_in,
1674
                        t6_in, t7_in;
1675
wire    [7:0]            req_t;
1676
 
1677
//
1678
// Group WB initiator 0 i/f inputs and outputs
1679
//
1680
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_cab_i, i0_wb_adr_i,
1681
                i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i};
1682
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
1683
 
1684
//
1685
// Group WB target 0 i/f inputs and outputs
1686
//
1687
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_cab_o, t0_wb_adr_o,
1688
                t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out;
1689
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
1690
 
1691
//
1692
// Group WB target 1 i/f inputs and outputs
1693
//
1694
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_cab_o, t1_wb_adr_o,
1695
                t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out;
1696
assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i};
1697
 
1698
//
1699
// Group WB target 2 i/f inputs and outputs
1700
//
1701
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_cab_o, t2_wb_adr_o,
1702
                t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out;
1703
assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i};
1704
 
1705
//
1706
// Group WB target 3 i/f inputs and outputs
1707
//
1708
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_cab_o, t3_wb_adr_o,
1709
                t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out;
1710
assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i};
1711
 
1712
//
1713
// Group WB target 4 i/f inputs and outputs
1714
//
1715
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_cab_o, t4_wb_adr_o,
1716
                t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out;
1717
assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i};
1718
 
1719
//
1720
// Group WB target 5 i/f inputs and outputs
1721
//
1722
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_cab_o, t5_wb_adr_o,
1723
                t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out;
1724
assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i};
1725
 
1726
//
1727
// Group WB target 6 i/f inputs and outputs
1728
//
1729
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_cab_o, t6_wb_adr_o,
1730
                t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out;
1731
assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i};
1732
 
1733
//
1734
// Group WB target 7 i/f inputs and outputs
1735
//
1736
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_cab_o, t7_wb_adr_o,
1737
                t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out;
1738
assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i};
1739
 
1740
//
1741
// Assign to WB target i/f outputs
1742
//
1743
// Either inputs from the initiator are assigned or zeros.
1744
//
1745
assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}};
1746
assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}};
1747
assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}};
1748
assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}};
1749
assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}};
1750
assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}};
1751
assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}};
1752
assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}};
1753
 
1754
//
1755
// Assign to WB initiator i/f outputs
1756
//
1757
// Assign inputs from target to initiator outputs according to
1758
// which target is accessed. If there is no request for a target,
1759
// assign zeros.
1760
//
1761
assign i0_out = req_t[0] ? t0_in :
1762
                req_t[1] ? t1_in :
1763
                req_t[2] ? t2_in :
1764
                req_t[3] ? t3_in :
1765
                req_t[4] ? t4_in :
1766
                req_t[5] ? t5_in :
1767
                req_t[6] ? t6_in :
1768
                req_t[7] ? t7_in : {`TC_TIN_W{1'b0}};
1769
 
1770
//
1771
// Determine which target is being accessed.
1772
//
1773
assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr);
1774
assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr);
1775
assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr);
1776
assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr);
1777
assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr);
1778
assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr);
1779
assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr);
1780
assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr);
1781
 
1782
endmodule

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