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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_tc_top.v] - Blame information for rev 7

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1 2 rfajardo
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Xess Traffic Cop                                            ////
4
////                                                              ////
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////  This file is part of the OR1K test application              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
9
////  This block connectes the RISC and peripheral controller     ////
10
////  cores together.                                             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - nothing really                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2002 OpenCores                                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: tc_top.v,v $
48
// Revision 1.4  2004/04/05 08:44:34  lampret
49
// Merged branch_qmem into main tree.
50
//
51
// Revision 1.2  2002/03/29 20:57:30  lampret
52
// Removed unused ports wb_clki and wb_rst_i
53
//
54
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
55
// First import of the "new" XESS XSV environment.
56
//
57
//
58
//
59
 
60
// synopsys translate_off
61
`include "timescale.v"
62
// synopsys translate_on
63
 
64
//
65
// Width of address bus
66
//
67
`define TC_AW           32
68
 
69
//
70
// Width of data bus
71
//
72
`define TC_DW           32
73
 
74
//
75
// Width of byte select bus
76
//
77
`define TC_BSW          4
78
 
79
//
80
// Width of WB target inputs (coming from WB slave)
81
//
82
// data bus width + ack + err
83
//
84
`define TC_TIN_W        `TC_DW+1+1
85
 
86
//
87
// Width of WB initiator inputs (coming from WB masters)
88
//
89 7 rfajardo
// cyc + stb + address bus width +
90 2 rfajardo
// byte select bus width + we + data bus width
91
//
92
`define TC_IIN_W        1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
93
 
94
//
95
// Traffic Cop Top
96
//
97
module minsoc_tc_top (
98
        wb_clk_i,
99
        wb_rst_i,
100
 
101
        i0_wb_cyc_i,
102
        i0_wb_stb_i,
103
        i0_wb_adr_i,
104
        i0_wb_sel_i,
105
        i0_wb_we_i,
106
        i0_wb_dat_i,
107
        i0_wb_dat_o,
108
        i0_wb_ack_o,
109
        i0_wb_err_o,
110
 
111
        i1_wb_cyc_i,
112
        i1_wb_stb_i,
113
        i1_wb_adr_i,
114
        i1_wb_sel_i,
115
        i1_wb_we_i,
116
        i1_wb_dat_i,
117
        i1_wb_dat_o,
118
        i1_wb_ack_o,
119
        i1_wb_err_o,
120
 
121
        i2_wb_cyc_i,
122
        i2_wb_stb_i,
123
        i2_wb_adr_i,
124
        i2_wb_sel_i,
125
        i2_wb_we_i,
126
        i2_wb_dat_i,
127
        i2_wb_dat_o,
128
        i2_wb_ack_o,
129
        i2_wb_err_o,
130
 
131
        i3_wb_cyc_i,
132
        i3_wb_stb_i,
133
        i3_wb_adr_i,
134
        i3_wb_sel_i,
135
        i3_wb_we_i,
136
        i3_wb_dat_i,
137
        i3_wb_dat_o,
138
        i3_wb_ack_o,
139
        i3_wb_err_o,
140
 
141
        i4_wb_cyc_i,
142
        i4_wb_stb_i,
143
        i4_wb_adr_i,
144
        i4_wb_sel_i,
145
        i4_wb_we_i,
146
        i4_wb_dat_i,
147
        i4_wb_dat_o,
148
        i4_wb_ack_o,
149
        i4_wb_err_o,
150
 
151
        i5_wb_cyc_i,
152
        i5_wb_stb_i,
153
        i5_wb_adr_i,
154
        i5_wb_sel_i,
155
        i5_wb_we_i,
156
        i5_wb_dat_i,
157
        i5_wb_dat_o,
158
        i5_wb_ack_o,
159
        i5_wb_err_o,
160
 
161
        i6_wb_cyc_i,
162
        i6_wb_stb_i,
163
        i6_wb_adr_i,
164
        i6_wb_sel_i,
165
        i6_wb_we_i,
166
        i6_wb_dat_i,
167
        i6_wb_dat_o,
168
        i6_wb_ack_o,
169
        i6_wb_err_o,
170
 
171
        i7_wb_cyc_i,
172
        i7_wb_stb_i,
173
        i7_wb_adr_i,
174
        i7_wb_sel_i,
175
        i7_wb_we_i,
176
        i7_wb_dat_i,
177
        i7_wb_dat_o,
178
        i7_wb_ack_o,
179
        i7_wb_err_o,
180
 
181
        t0_wb_cyc_o,
182
        t0_wb_stb_o,
183
        t0_wb_adr_o,
184
        t0_wb_sel_o,
185
        t0_wb_we_o,
186
        t0_wb_dat_o,
187
        t0_wb_dat_i,
188
        t0_wb_ack_i,
189
        t0_wb_err_i,
190
 
191
        t1_wb_cyc_o,
192
        t1_wb_stb_o,
193
        t1_wb_adr_o,
194
        t1_wb_sel_o,
195
        t1_wb_we_o,
196
        t1_wb_dat_o,
197
        t1_wb_dat_i,
198
        t1_wb_ack_i,
199
        t1_wb_err_i,
200
 
201
        t2_wb_cyc_o,
202
        t2_wb_stb_o,
203
        t2_wb_adr_o,
204
        t2_wb_sel_o,
205
        t2_wb_we_o,
206
        t2_wb_dat_o,
207
        t2_wb_dat_i,
208
        t2_wb_ack_i,
209
        t2_wb_err_i,
210
 
211
        t3_wb_cyc_o,
212
        t3_wb_stb_o,
213
        t3_wb_adr_o,
214
        t3_wb_sel_o,
215
        t3_wb_we_o,
216
        t3_wb_dat_o,
217
        t3_wb_dat_i,
218
        t3_wb_ack_i,
219
        t3_wb_err_i,
220
 
221
        t4_wb_cyc_o,
222
        t4_wb_stb_o,
223
        t4_wb_adr_o,
224
        t4_wb_sel_o,
225
        t4_wb_we_o,
226
        t4_wb_dat_o,
227
        t4_wb_dat_i,
228
        t4_wb_ack_i,
229
        t4_wb_err_i,
230
 
231
        t5_wb_cyc_o,
232
        t5_wb_stb_o,
233
        t5_wb_adr_o,
234
        t5_wb_sel_o,
235
        t5_wb_we_o,
236
        t5_wb_dat_o,
237
        t5_wb_dat_i,
238
        t5_wb_ack_i,
239
        t5_wb_err_i,
240
 
241
        t6_wb_cyc_o,
242
        t6_wb_stb_o,
243
        t6_wb_adr_o,
244
        t6_wb_sel_o,
245
        t6_wb_we_o,
246
        t6_wb_dat_o,
247
        t6_wb_dat_i,
248
        t6_wb_ack_i,
249
        t6_wb_err_i,
250
 
251
        t7_wb_cyc_o,
252
        t7_wb_stb_o,
253
        t7_wb_adr_o,
254
        t7_wb_sel_o,
255
        t7_wb_we_o,
256
        t7_wb_dat_o,
257
        t7_wb_dat_i,
258
        t7_wb_ack_i,
259
        t7_wb_err_i,
260
 
261
        t8_wb_cyc_o,
262
        t8_wb_stb_o,
263
        t8_wb_adr_o,
264
        t8_wb_sel_o,
265
        t8_wb_we_o,
266
        t8_wb_dat_o,
267
        t8_wb_dat_i,
268
        t8_wb_ack_i,
269
        t8_wb_err_i
270
 
271
);
272
 
273
//
274
// Parameters
275
//
276
parameter               t0_addr_w = 4;
277
parameter               t0_addr = 4'd8;
278
parameter               t1_addr_w = 4;
279
parameter               t1_addr = 4'd0;
280
parameter               t28c_addr_w = 4;
281
parameter               t28_addr = 4'd0;
282
parameter               t28i_addr_w = 4;
283
parameter               t2_addr = 4'd1;
284
parameter               t3_addr = 4'd2;
285
parameter               t4_addr = 4'd3;
286
parameter               t5_addr = 4'd4;
287
parameter               t6_addr = 4'd5;
288
parameter               t7_addr = 4'd6;
289
parameter               t8_addr = 4'd7;
290
 
291
//
292
// I/O Ports
293
//
294
input                   wb_clk_i;
295
input                   wb_rst_i;
296
 
297
//
298
// WB slave i/f connecting initiator 0
299
//
300
input                   i0_wb_cyc_i;
301
input                   i0_wb_stb_i;
302
input   [`TC_AW-1:0]     i0_wb_adr_i;
303
input   [`TC_BSW-1:0]    i0_wb_sel_i;
304
input                   i0_wb_we_i;
305
input   [`TC_DW-1:0]     i0_wb_dat_i;
306
output  [`TC_DW-1:0]     i0_wb_dat_o;
307
output                  i0_wb_ack_o;
308
output                  i0_wb_err_o;
309
 
310
//
311
// WB slave i/f connecting initiator 1
312
//
313
input                   i1_wb_cyc_i;
314
input                   i1_wb_stb_i;
315
input   [`TC_AW-1:0]     i1_wb_adr_i;
316
input   [`TC_BSW-1:0]    i1_wb_sel_i;
317
input                   i1_wb_we_i;
318
input   [`TC_DW-1:0]     i1_wb_dat_i;
319
output  [`TC_DW-1:0]     i1_wb_dat_o;
320
output                  i1_wb_ack_o;
321
output                  i1_wb_err_o;
322
 
323
//
324
// WB slave i/f connecting initiator 2
325
//
326
input                   i2_wb_cyc_i;
327
input                   i2_wb_stb_i;
328
input   [`TC_AW-1:0]     i2_wb_adr_i;
329
input   [`TC_BSW-1:0]    i2_wb_sel_i;
330
input                   i2_wb_we_i;
331
input   [`TC_DW-1:0]     i2_wb_dat_i;
332
output  [`TC_DW-1:0]     i2_wb_dat_o;
333
output                  i2_wb_ack_o;
334
output                  i2_wb_err_o;
335
 
336
//
337
// WB slave i/f connecting initiator 3
338
//
339
input                   i3_wb_cyc_i;
340
input                   i3_wb_stb_i;
341
input   [`TC_AW-1:0]     i3_wb_adr_i;
342
input   [`TC_BSW-1:0]    i3_wb_sel_i;
343
input                   i3_wb_we_i;
344
input   [`TC_DW-1:0]     i3_wb_dat_i;
345
output  [`TC_DW-1:0]     i3_wb_dat_o;
346
output                  i3_wb_ack_o;
347
output                  i3_wb_err_o;
348
 
349
//
350
// WB slave i/f connecting initiator 4
351
//
352
input                   i4_wb_cyc_i;
353
input                   i4_wb_stb_i;
354
input   [`TC_AW-1:0]     i4_wb_adr_i;
355
input   [`TC_BSW-1:0]    i4_wb_sel_i;
356
input                   i4_wb_we_i;
357
input   [`TC_DW-1:0]     i4_wb_dat_i;
358
output  [`TC_DW-1:0]     i4_wb_dat_o;
359
output                  i4_wb_ack_o;
360
output                  i4_wb_err_o;
361
 
362
//
363
// WB slave i/f connecting initiator 5
364
//
365
input                   i5_wb_cyc_i;
366
input                   i5_wb_stb_i;
367
input   [`TC_AW-1:0]     i5_wb_adr_i;
368
input   [`TC_BSW-1:0]    i5_wb_sel_i;
369
input                   i5_wb_we_i;
370
input   [`TC_DW-1:0]     i5_wb_dat_i;
371
output  [`TC_DW-1:0]     i5_wb_dat_o;
372
output                  i5_wb_ack_o;
373
output                  i5_wb_err_o;
374
 
375
//
376
// WB slave i/f connecting initiator 6
377
//
378
input                   i6_wb_cyc_i;
379
input                   i6_wb_stb_i;
380
input   [`TC_AW-1:0]     i6_wb_adr_i;
381
input   [`TC_BSW-1:0]    i6_wb_sel_i;
382
input                   i6_wb_we_i;
383
input   [`TC_DW-1:0]     i6_wb_dat_i;
384
output  [`TC_DW-1:0]     i6_wb_dat_o;
385
output                  i6_wb_ack_o;
386
output                  i6_wb_err_o;
387
 
388
//
389
// WB slave i/f connecting initiator 7
390
//
391
input                   i7_wb_cyc_i;
392
input                   i7_wb_stb_i;
393
input   [`TC_AW-1:0]     i7_wb_adr_i;
394
input   [`TC_BSW-1:0]    i7_wb_sel_i;
395
input                   i7_wb_we_i;
396
input   [`TC_DW-1:0]     i7_wb_dat_i;
397
output  [`TC_DW-1:0]     i7_wb_dat_o;
398
output                  i7_wb_ack_o;
399
output                  i7_wb_err_o;
400
 
401
//
402
// WB master i/f connecting target 0
403
//
404
output                  t0_wb_cyc_o;
405
output                  t0_wb_stb_o;
406
output  [`TC_AW-1:0]     t0_wb_adr_o;
407
output  [`TC_BSW-1:0]    t0_wb_sel_o;
408
output                  t0_wb_we_o;
409
output  [`TC_DW-1:0]     t0_wb_dat_o;
410
input   [`TC_DW-1:0]     t0_wb_dat_i;
411
input                   t0_wb_ack_i;
412
input                   t0_wb_err_i;
413
 
414
//
415
// WB master i/f connecting target 1
416
//
417
output                  t1_wb_cyc_o;
418
output                  t1_wb_stb_o;
419
output  [`TC_AW-1:0]     t1_wb_adr_o;
420
output  [`TC_BSW-1:0]    t1_wb_sel_o;
421
output                  t1_wb_we_o;
422
output  [`TC_DW-1:0]     t1_wb_dat_o;
423
input   [`TC_DW-1:0]     t1_wb_dat_i;
424
input                   t1_wb_ack_i;
425
input                   t1_wb_err_i;
426
 
427
//
428
// WB master i/f connecting target 2
429
//
430
output                  t2_wb_cyc_o;
431
output                  t2_wb_stb_o;
432
output  [`TC_AW-1:0]     t2_wb_adr_o;
433
output  [`TC_BSW-1:0]    t2_wb_sel_o;
434
output                  t2_wb_we_o;
435
output  [`TC_DW-1:0]     t2_wb_dat_o;
436
input   [`TC_DW-1:0]     t2_wb_dat_i;
437
input                   t2_wb_ack_i;
438
input                   t2_wb_err_i;
439
 
440
//
441
// WB master i/f connecting target 3
442
//
443
output                  t3_wb_cyc_o;
444
output                  t3_wb_stb_o;
445
output  [`TC_AW-1:0]     t3_wb_adr_o;
446
output  [`TC_BSW-1:0]    t3_wb_sel_o;
447
output                  t3_wb_we_o;
448
output  [`TC_DW-1:0]     t3_wb_dat_o;
449
input   [`TC_DW-1:0]     t3_wb_dat_i;
450
input                   t3_wb_ack_i;
451
input                   t3_wb_err_i;
452
 
453
//
454
// WB master i/f connecting target 4
455
//
456
output                  t4_wb_cyc_o;
457
output                  t4_wb_stb_o;
458
output  [`TC_AW-1:0]     t4_wb_adr_o;
459
output  [`TC_BSW-1:0]    t4_wb_sel_o;
460
output                  t4_wb_we_o;
461
output  [`TC_DW-1:0]     t4_wb_dat_o;
462
input   [`TC_DW-1:0]     t4_wb_dat_i;
463
input                   t4_wb_ack_i;
464
input                   t4_wb_err_i;
465
 
466
//
467
// WB master i/f connecting target 5
468
//
469
output                  t5_wb_cyc_o;
470
output                  t5_wb_stb_o;
471
output  [`TC_AW-1:0]     t5_wb_adr_o;
472
output  [`TC_BSW-1:0]    t5_wb_sel_o;
473
output                  t5_wb_we_o;
474
output  [`TC_DW-1:0]     t5_wb_dat_o;
475
input   [`TC_DW-1:0]     t5_wb_dat_i;
476
input                   t5_wb_ack_i;
477
input                   t5_wb_err_i;
478
 
479
//
480
// WB master i/f connecting target 6
481
//
482
output                  t6_wb_cyc_o;
483
output                  t6_wb_stb_o;
484
output  [`TC_AW-1:0]     t6_wb_adr_o;
485
output  [`TC_BSW-1:0]    t6_wb_sel_o;
486
output                  t6_wb_we_o;
487
output  [`TC_DW-1:0]     t6_wb_dat_o;
488
input   [`TC_DW-1:0]     t6_wb_dat_i;
489
input                   t6_wb_ack_i;
490
input                   t6_wb_err_i;
491
 
492
//
493
// WB master i/f connecting target 7
494
//
495
output                  t7_wb_cyc_o;
496
output                  t7_wb_stb_o;
497
output  [`TC_AW-1:0]     t7_wb_adr_o;
498
output  [`TC_BSW-1:0]    t7_wb_sel_o;
499
output                  t7_wb_we_o;
500
output  [`TC_DW-1:0]     t7_wb_dat_o;
501
input   [`TC_DW-1:0]     t7_wb_dat_i;
502
input                   t7_wb_ack_i;
503
input                   t7_wb_err_i;
504
 
505
//
506
// WB master i/f connecting target 8
507
//
508
output                  t8_wb_cyc_o;
509
output                  t8_wb_stb_o;
510
output  [`TC_AW-1:0]     t8_wb_adr_o;
511
output  [`TC_BSW-1:0]    t8_wb_sel_o;
512
output                  t8_wb_we_o;
513
output  [`TC_DW-1:0]     t8_wb_dat_o;
514
input   [`TC_DW-1:0]     t8_wb_dat_i;
515
input                   t8_wb_ack_i;
516
input                   t8_wb_err_i;
517
 
518
//
519
// Internal wires & registers
520
//
521
 
522
//
523
// Outputs for initiators from both mi_to_st blocks
524
//
525
wire    [`TC_DW-1:0]     xi0_wb_dat_o;
526
wire                    xi0_wb_ack_o;
527
wire                    xi0_wb_err_o;
528
wire    [`TC_DW-1:0]     xi1_wb_dat_o;
529
wire                    xi1_wb_ack_o;
530
wire                    xi1_wb_err_o;
531
wire    [`TC_DW-1:0]     xi2_wb_dat_o;
532
wire                    xi2_wb_ack_o;
533
wire                    xi2_wb_err_o;
534
wire    [`TC_DW-1:0]     xi3_wb_dat_o;
535
wire                    xi3_wb_ack_o;
536
wire                    xi3_wb_err_o;
537
wire    [`TC_DW-1:0]     xi4_wb_dat_o;
538
wire                    xi4_wb_ack_o;
539
wire                    xi4_wb_err_o;
540
wire    [`TC_DW-1:0]     xi5_wb_dat_o;
541
wire                    xi5_wb_ack_o;
542
wire                    xi5_wb_err_o;
543
wire    [`TC_DW-1:0]     xi6_wb_dat_o;
544
wire                    xi6_wb_ack_o;
545
wire                    xi6_wb_err_o;
546
wire    [`TC_DW-1:0]     xi7_wb_dat_o;
547
wire                    xi7_wb_ack_o;
548
wire                    xi7_wb_err_o;
549
wire    [`TC_DW-1:0]     yi0_wb_dat_o;
550
wire                    yi0_wb_ack_o;
551
wire                    yi0_wb_err_o;
552
wire    [`TC_DW-1:0]     yi1_wb_dat_o;
553
wire                    yi1_wb_ack_o;
554
wire                    yi1_wb_err_o;
555
wire    [`TC_DW-1:0]     yi2_wb_dat_o;
556
wire                    yi2_wb_ack_o;
557
wire                    yi2_wb_err_o;
558
wire    [`TC_DW-1:0]     yi3_wb_dat_o;
559
wire                    yi3_wb_ack_o;
560
wire                    yi3_wb_err_o;
561
wire    [`TC_DW-1:0]     yi4_wb_dat_o;
562
wire                    yi4_wb_ack_o;
563
wire                    yi4_wb_err_o;
564
wire    [`TC_DW-1:0]     yi5_wb_dat_o;
565
wire                    yi5_wb_ack_o;
566
wire                    yi5_wb_err_o;
567
wire    [`TC_DW-1:0]     yi6_wb_dat_o;
568
wire                    yi6_wb_ack_o;
569
wire                    yi6_wb_err_o;
570
wire    [`TC_DW-1:0]     yi7_wb_dat_o;
571
wire                    yi7_wb_ack_o;
572
wire                    yi7_wb_err_o;
573
 
574
//
575
// Intermediate signals connecting peripheral channel's
576
// mi_to_st and si_to_mt blocks.
577
//
578
wire                    z_wb_cyc_i;
579
wire                    z_wb_stb_i;
580
wire    [`TC_AW-1:0]     z_wb_adr_i;
581
wire    [`TC_BSW-1:0]    z_wb_sel_i;
582
wire                    z_wb_we_i;
583
wire    [`TC_DW-1:0]     z_wb_dat_i;
584
wire    [`TC_DW-1:0]     z_wb_dat_t;
585
wire                    z_wb_ack_t;
586
wire                    z_wb_err_t;
587
 
588
//
589
// Outputs for initiators are ORed from both mi_to_st blocks
590
//
591
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
592
assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
593
assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o;
594
assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o;
595
assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o;
596
assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o;
597
assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o;
598
assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o;
599
assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o;
600
assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o;
601
assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o;
602
assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o;
603
assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o;
604
assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o;
605
assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o;
606
assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o;
607
assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o;
608
assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o;
609
assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o;
610
assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o;
611
assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o;
612
assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o;
613
assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o;
614
assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o;
615
 
616
//
617
// From initiators to target 0
618
//
619
tc_mi_to_st #(t0_addr_w, t0_addr,
620
        0, t0_addr_w, t0_addr) t0_ch(
621
        .wb_clk_i(wb_clk_i),
622
        .wb_rst_i(wb_rst_i),
623
 
624
        .i0_wb_cyc_i(i0_wb_cyc_i),
625
        .i0_wb_stb_i(i0_wb_stb_i),
626
        .i0_wb_adr_i(i0_wb_adr_i),
627
        .i0_wb_sel_i(i0_wb_sel_i),
628
        .i0_wb_we_i(i0_wb_we_i),
629
        .i0_wb_dat_i(i0_wb_dat_i),
630
        .i0_wb_dat_o(xi0_wb_dat_o),
631
        .i0_wb_ack_o(xi0_wb_ack_o),
632
        .i0_wb_err_o(xi0_wb_err_o),
633
 
634
        .i1_wb_cyc_i(i1_wb_cyc_i),
635
        .i1_wb_stb_i(i1_wb_stb_i),
636
        .i1_wb_adr_i(i1_wb_adr_i),
637
        .i1_wb_sel_i(i1_wb_sel_i),
638
        .i1_wb_we_i(i1_wb_we_i),
639
        .i1_wb_dat_i(i1_wb_dat_i),
640
        .i1_wb_dat_o(xi1_wb_dat_o),
641
        .i1_wb_ack_o(xi1_wb_ack_o),
642
        .i1_wb_err_o(xi1_wb_err_o),
643
 
644
        .i2_wb_cyc_i(i2_wb_cyc_i),
645
        .i2_wb_stb_i(i2_wb_stb_i),
646
        .i2_wb_adr_i(i2_wb_adr_i),
647
        .i2_wb_sel_i(i2_wb_sel_i),
648
        .i2_wb_we_i(i2_wb_we_i),
649
        .i2_wb_dat_i(i2_wb_dat_i),
650
        .i2_wb_dat_o(xi2_wb_dat_o),
651
        .i2_wb_ack_o(xi2_wb_ack_o),
652
        .i2_wb_err_o(xi2_wb_err_o),
653
 
654
        .i3_wb_cyc_i(i3_wb_cyc_i),
655
        .i3_wb_stb_i(i3_wb_stb_i),
656
        .i3_wb_adr_i(i3_wb_adr_i),
657
        .i3_wb_sel_i(i3_wb_sel_i),
658
        .i3_wb_we_i(i3_wb_we_i),
659
        .i3_wb_dat_i(i3_wb_dat_i),
660
        .i3_wb_dat_o(xi3_wb_dat_o),
661
        .i3_wb_ack_o(xi3_wb_ack_o),
662
        .i3_wb_err_o(xi3_wb_err_o),
663
 
664
        .i4_wb_cyc_i(i4_wb_cyc_i),
665
        .i4_wb_stb_i(i4_wb_stb_i),
666
        .i4_wb_adr_i(i4_wb_adr_i),
667
        .i4_wb_sel_i(i4_wb_sel_i),
668
        .i4_wb_we_i(i4_wb_we_i),
669
        .i4_wb_dat_i(i4_wb_dat_i),
670
        .i4_wb_dat_o(xi4_wb_dat_o),
671
        .i4_wb_ack_o(xi4_wb_ack_o),
672
        .i4_wb_err_o(xi4_wb_err_o),
673
 
674
        .i5_wb_cyc_i(i5_wb_cyc_i),
675
        .i5_wb_stb_i(i5_wb_stb_i),
676
        .i5_wb_adr_i(i5_wb_adr_i),
677
        .i5_wb_sel_i(i5_wb_sel_i),
678
        .i5_wb_we_i(i5_wb_we_i),
679
        .i5_wb_dat_i(i5_wb_dat_i),
680
        .i5_wb_dat_o(xi5_wb_dat_o),
681
        .i5_wb_ack_o(xi5_wb_ack_o),
682
        .i5_wb_err_o(xi5_wb_err_o),
683
 
684
        .i6_wb_cyc_i(i6_wb_cyc_i),
685
        .i6_wb_stb_i(i6_wb_stb_i),
686
        .i6_wb_adr_i(i6_wb_adr_i),
687
        .i6_wb_sel_i(i6_wb_sel_i),
688
        .i6_wb_we_i(i6_wb_we_i),
689
        .i6_wb_dat_i(i6_wb_dat_i),
690
        .i6_wb_dat_o(xi6_wb_dat_o),
691
        .i6_wb_ack_o(xi6_wb_ack_o),
692
        .i6_wb_err_o(xi6_wb_err_o),
693
 
694
        .i7_wb_cyc_i(i7_wb_cyc_i),
695
        .i7_wb_stb_i(i7_wb_stb_i),
696
        .i7_wb_adr_i(i7_wb_adr_i),
697
        .i7_wb_sel_i(i7_wb_sel_i),
698
        .i7_wb_we_i(i7_wb_we_i),
699
        .i7_wb_dat_i(i7_wb_dat_i),
700
        .i7_wb_dat_o(xi7_wb_dat_o),
701
        .i7_wb_ack_o(xi7_wb_ack_o),
702
        .i7_wb_err_o(xi7_wb_err_o),
703
 
704
        .t0_wb_cyc_o(t0_wb_cyc_o),
705
        .t0_wb_stb_o(t0_wb_stb_o),
706
        .t0_wb_adr_o(t0_wb_adr_o),
707
        .t0_wb_sel_o(t0_wb_sel_o),
708
        .t0_wb_we_o(t0_wb_we_o),
709
        .t0_wb_dat_o(t0_wb_dat_o),
710
        .t0_wb_dat_i(t0_wb_dat_i),
711
        .t0_wb_ack_i(t0_wb_ack_i),
712
        .t0_wb_err_i(t0_wb_err_i)
713
 
714
);
715
 
716
//
717
// From initiators to targets 1-8 (upper part)
718
//
719
tc_mi_to_st #(t1_addr_w, t1_addr,
720
        1, t28c_addr_w, t28_addr) t18_ch_upper(
721
        .wb_clk_i(wb_clk_i),
722
        .wb_rst_i(wb_rst_i),
723
 
724
        .i0_wb_cyc_i(i0_wb_cyc_i),
725
        .i0_wb_stb_i(i0_wb_stb_i),
726
        .i0_wb_adr_i(i0_wb_adr_i),
727
        .i0_wb_sel_i(i0_wb_sel_i),
728
        .i0_wb_we_i(i0_wb_we_i),
729
        .i0_wb_dat_i(i0_wb_dat_i),
730
        .i0_wb_dat_o(yi0_wb_dat_o),
731
        .i0_wb_ack_o(yi0_wb_ack_o),
732
        .i0_wb_err_o(yi0_wb_err_o),
733
 
734
        .i1_wb_cyc_i(i1_wb_cyc_i),
735
        .i1_wb_stb_i(i1_wb_stb_i),
736
        .i1_wb_adr_i(i1_wb_adr_i),
737
        .i1_wb_sel_i(i1_wb_sel_i),
738
        .i1_wb_we_i(i1_wb_we_i),
739
        .i1_wb_dat_i(i1_wb_dat_i),
740
        .i1_wb_dat_o(yi1_wb_dat_o),
741
        .i1_wb_ack_o(yi1_wb_ack_o),
742
        .i1_wb_err_o(yi1_wb_err_o),
743
 
744
        .i2_wb_cyc_i(i2_wb_cyc_i),
745
        .i2_wb_stb_i(i2_wb_stb_i),
746
        .i2_wb_adr_i(i2_wb_adr_i),
747
        .i2_wb_sel_i(i2_wb_sel_i),
748
        .i2_wb_we_i(i2_wb_we_i),
749
        .i2_wb_dat_i(i2_wb_dat_i),
750
        .i2_wb_dat_o(yi2_wb_dat_o),
751
        .i2_wb_ack_o(yi2_wb_ack_o),
752
        .i2_wb_err_o(yi2_wb_err_o),
753
 
754
        .i3_wb_cyc_i(i3_wb_cyc_i),
755
        .i3_wb_stb_i(i3_wb_stb_i),
756
        .i3_wb_adr_i(i3_wb_adr_i),
757
        .i3_wb_sel_i(i3_wb_sel_i),
758
        .i3_wb_we_i(i3_wb_we_i),
759
        .i3_wb_dat_i(i3_wb_dat_i),
760
        .i3_wb_dat_o(yi3_wb_dat_o),
761
        .i3_wb_ack_o(yi3_wb_ack_o),
762
        .i3_wb_err_o(yi3_wb_err_o),
763
 
764
        .i4_wb_cyc_i(i4_wb_cyc_i),
765
        .i4_wb_stb_i(i4_wb_stb_i),
766
        .i4_wb_adr_i(i4_wb_adr_i),
767
        .i4_wb_sel_i(i4_wb_sel_i),
768
        .i4_wb_we_i(i4_wb_we_i),
769
        .i4_wb_dat_i(i4_wb_dat_i),
770
        .i4_wb_dat_o(yi4_wb_dat_o),
771
        .i4_wb_ack_o(yi4_wb_ack_o),
772
        .i4_wb_err_o(yi4_wb_err_o),
773
 
774
        .i5_wb_cyc_i(i5_wb_cyc_i),
775
        .i5_wb_stb_i(i5_wb_stb_i),
776
        .i5_wb_adr_i(i5_wb_adr_i),
777
        .i5_wb_sel_i(i5_wb_sel_i),
778
        .i5_wb_we_i(i5_wb_we_i),
779
        .i5_wb_dat_i(i5_wb_dat_i),
780
        .i5_wb_dat_o(yi5_wb_dat_o),
781
        .i5_wb_ack_o(yi5_wb_ack_o),
782
        .i5_wb_err_o(yi5_wb_err_o),
783
 
784
        .i6_wb_cyc_i(i6_wb_cyc_i),
785
        .i6_wb_stb_i(i6_wb_stb_i),
786
        .i6_wb_adr_i(i6_wb_adr_i),
787
        .i6_wb_sel_i(i6_wb_sel_i),
788
        .i6_wb_we_i(i6_wb_we_i),
789
        .i6_wb_dat_i(i6_wb_dat_i),
790
        .i6_wb_dat_o(yi6_wb_dat_o),
791
        .i6_wb_ack_o(yi6_wb_ack_o),
792
        .i6_wb_err_o(yi6_wb_err_o),
793
 
794
        .i7_wb_cyc_i(i7_wb_cyc_i),
795
        .i7_wb_stb_i(i7_wb_stb_i),
796
        .i7_wb_adr_i(i7_wb_adr_i),
797
        .i7_wb_sel_i(i7_wb_sel_i),
798
        .i7_wb_we_i(i7_wb_we_i),
799
        .i7_wb_dat_i(i7_wb_dat_i),
800
        .i7_wb_dat_o(yi7_wb_dat_o),
801
        .i7_wb_ack_o(yi7_wb_ack_o),
802
        .i7_wb_err_o(yi7_wb_err_o),
803
 
804
        .t0_wb_cyc_o(z_wb_cyc_i),
805
        .t0_wb_stb_o(z_wb_stb_i),
806
        .t0_wb_adr_o(z_wb_adr_i),
807
        .t0_wb_sel_o(z_wb_sel_i),
808
        .t0_wb_we_o(z_wb_we_i),
809
        .t0_wb_dat_o(z_wb_dat_i),
810
        .t0_wb_dat_i(z_wb_dat_t),
811
        .t0_wb_ack_i(z_wb_ack_t),
812
        .t0_wb_err_i(z_wb_err_t)
813
 
814
);
815
 
816
//
817
// From initiators to targets 1-8 (lower part)
818
//
819
tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,
820
        t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(
821
 
822
        .i0_wb_cyc_i(z_wb_cyc_i),
823
        .i0_wb_stb_i(z_wb_stb_i),
824
        .i0_wb_adr_i(z_wb_adr_i),
825
        .i0_wb_sel_i(z_wb_sel_i),
826
        .i0_wb_we_i(z_wb_we_i),
827
        .i0_wb_dat_i(z_wb_dat_i),
828
        .i0_wb_dat_o(z_wb_dat_t),
829
        .i0_wb_ack_o(z_wb_ack_t),
830
        .i0_wb_err_o(z_wb_err_t),
831
 
832
        .t0_wb_cyc_o(t1_wb_cyc_o),
833
        .t0_wb_stb_o(t1_wb_stb_o),
834
        .t0_wb_adr_o(t1_wb_adr_o),
835
        .t0_wb_sel_o(t1_wb_sel_o),
836
        .t0_wb_we_o(t1_wb_we_o),
837
        .t0_wb_dat_o(t1_wb_dat_o),
838
        .t0_wb_dat_i(t1_wb_dat_i),
839
        .t0_wb_ack_i(t1_wb_ack_i),
840
        .t0_wb_err_i(t1_wb_err_i),
841
 
842
        .t1_wb_cyc_o(t2_wb_cyc_o),
843
        .t1_wb_stb_o(t2_wb_stb_o),
844
        .t1_wb_adr_o(t2_wb_adr_o),
845
        .t1_wb_sel_o(t2_wb_sel_o),
846
        .t1_wb_we_o(t2_wb_we_o),
847
        .t1_wb_dat_o(t2_wb_dat_o),
848
        .t1_wb_dat_i(t2_wb_dat_i),
849
        .t1_wb_ack_i(t2_wb_ack_i),
850
        .t1_wb_err_i(t2_wb_err_i),
851
 
852
        .t2_wb_cyc_o(t3_wb_cyc_o),
853
        .t2_wb_stb_o(t3_wb_stb_o),
854
        .t2_wb_adr_o(t3_wb_adr_o),
855
        .t2_wb_sel_o(t3_wb_sel_o),
856
        .t2_wb_we_o(t3_wb_we_o),
857
        .t2_wb_dat_o(t3_wb_dat_o),
858
        .t2_wb_dat_i(t3_wb_dat_i),
859
        .t2_wb_ack_i(t3_wb_ack_i),
860
        .t2_wb_err_i(t3_wb_err_i),
861
 
862
        .t3_wb_cyc_o(t4_wb_cyc_o),
863
        .t3_wb_stb_o(t4_wb_stb_o),
864
        .t3_wb_adr_o(t4_wb_adr_o),
865
        .t3_wb_sel_o(t4_wb_sel_o),
866
        .t3_wb_we_o(t4_wb_we_o),
867
        .t3_wb_dat_o(t4_wb_dat_o),
868
        .t3_wb_dat_i(t4_wb_dat_i),
869
        .t3_wb_ack_i(t4_wb_ack_i),
870
        .t3_wb_err_i(t4_wb_err_i),
871
 
872
        .t4_wb_cyc_o(t5_wb_cyc_o),
873
        .t4_wb_stb_o(t5_wb_stb_o),
874
        .t4_wb_adr_o(t5_wb_adr_o),
875
        .t4_wb_sel_o(t5_wb_sel_o),
876
        .t4_wb_we_o(t5_wb_we_o),
877
        .t4_wb_dat_o(t5_wb_dat_o),
878
        .t4_wb_dat_i(t5_wb_dat_i),
879
        .t4_wb_ack_i(t5_wb_ack_i),
880
        .t4_wb_err_i(t5_wb_err_i),
881
 
882
        .t5_wb_cyc_o(t6_wb_cyc_o),
883
        .t5_wb_stb_o(t6_wb_stb_o),
884
        .t5_wb_adr_o(t6_wb_adr_o),
885
        .t5_wb_sel_o(t6_wb_sel_o),
886
        .t5_wb_we_o(t6_wb_we_o),
887
        .t5_wb_dat_o(t6_wb_dat_o),
888
        .t5_wb_dat_i(t6_wb_dat_i),
889
        .t5_wb_ack_i(t6_wb_ack_i),
890
        .t5_wb_err_i(t6_wb_err_i),
891
 
892
        .t6_wb_cyc_o(t7_wb_cyc_o),
893
        .t6_wb_stb_o(t7_wb_stb_o),
894
        .t6_wb_adr_o(t7_wb_adr_o),
895
        .t6_wb_sel_o(t7_wb_sel_o),
896
        .t6_wb_we_o(t7_wb_we_o),
897
        .t6_wb_dat_o(t7_wb_dat_o),
898
        .t6_wb_dat_i(t7_wb_dat_i),
899
        .t6_wb_ack_i(t7_wb_ack_i),
900
        .t6_wb_err_i(t7_wb_err_i),
901
 
902
        .t7_wb_cyc_o(t8_wb_cyc_o),
903
        .t7_wb_stb_o(t8_wb_stb_o),
904
        .t7_wb_adr_o(t8_wb_adr_o),
905
        .t7_wb_sel_o(t8_wb_sel_o),
906
        .t7_wb_we_o(t8_wb_we_o),
907
        .t7_wb_dat_o(t8_wb_dat_o),
908
        .t7_wb_dat_i(t8_wb_dat_i),
909
        .t7_wb_ack_i(t8_wb_ack_i),
910
        .t7_wb_err_i(t8_wb_err_i)
911
 
912
);
913
 
914
endmodule
915
 
916
//
917
// Multiple initiator to single target
918
//
919
module tc_mi_to_st (
920
        wb_clk_i,
921
        wb_rst_i,
922
 
923
        i0_wb_cyc_i,
924
        i0_wb_stb_i,
925
        i0_wb_adr_i,
926
        i0_wb_sel_i,
927
        i0_wb_we_i,
928
        i0_wb_dat_i,
929
        i0_wb_dat_o,
930
        i0_wb_ack_o,
931
        i0_wb_err_o,
932
 
933
        i1_wb_cyc_i,
934
        i1_wb_stb_i,
935
        i1_wb_adr_i,
936
        i1_wb_sel_i,
937
        i1_wb_we_i,
938
        i1_wb_dat_i,
939
        i1_wb_dat_o,
940
        i1_wb_ack_o,
941
        i1_wb_err_o,
942
 
943
        i2_wb_cyc_i,
944
        i2_wb_stb_i,
945
        i2_wb_adr_i,
946
        i2_wb_sel_i,
947
        i2_wb_we_i,
948
        i2_wb_dat_i,
949
        i2_wb_dat_o,
950
        i2_wb_ack_o,
951
        i2_wb_err_o,
952
 
953
        i3_wb_cyc_i,
954
        i3_wb_stb_i,
955
        i3_wb_adr_i,
956
        i3_wb_sel_i,
957
        i3_wb_we_i,
958
        i3_wb_dat_i,
959
        i3_wb_dat_o,
960
        i3_wb_ack_o,
961
        i3_wb_err_o,
962
 
963
        i4_wb_cyc_i,
964
        i4_wb_stb_i,
965
        i4_wb_adr_i,
966
        i4_wb_sel_i,
967
        i4_wb_we_i,
968
        i4_wb_dat_i,
969
        i4_wb_dat_o,
970
        i4_wb_ack_o,
971
        i4_wb_err_o,
972
 
973
        i5_wb_cyc_i,
974
        i5_wb_stb_i,
975
        i5_wb_adr_i,
976
        i5_wb_sel_i,
977
        i5_wb_we_i,
978
        i5_wb_dat_i,
979
        i5_wb_dat_o,
980
        i5_wb_ack_o,
981
        i5_wb_err_o,
982
 
983
        i6_wb_cyc_i,
984
        i6_wb_stb_i,
985
        i6_wb_adr_i,
986
        i6_wb_sel_i,
987
        i6_wb_we_i,
988
        i6_wb_dat_i,
989
        i6_wb_dat_o,
990
        i6_wb_ack_o,
991
        i6_wb_err_o,
992
 
993
        i7_wb_cyc_i,
994
        i7_wb_stb_i,
995
        i7_wb_adr_i,
996
        i7_wb_sel_i,
997
        i7_wb_we_i,
998
        i7_wb_dat_i,
999
        i7_wb_dat_o,
1000
        i7_wb_ack_o,
1001
        i7_wb_err_o,
1002
 
1003
        t0_wb_cyc_o,
1004
        t0_wb_stb_o,
1005
        t0_wb_adr_o,
1006
        t0_wb_sel_o,
1007
        t0_wb_we_o,
1008
        t0_wb_dat_o,
1009
        t0_wb_dat_i,
1010
        t0_wb_ack_i,
1011
        t0_wb_err_i
1012
 
1013
);
1014
 
1015
//
1016
// Parameters
1017
//
1018
parameter               t0_addr_w = 2;
1019
parameter               t0_addr = 2'b00;
1020
parameter               multitarg = 1'b0;
1021
parameter               t17_addr_w = 2;
1022
parameter               t17_addr = 2'b00;
1023
 
1024
//
1025
// I/O Ports
1026
//
1027
input                   wb_clk_i;
1028
input                   wb_rst_i;
1029
 
1030
//
1031
// WB slave i/f connecting initiator 0
1032
//
1033
input                   i0_wb_cyc_i;
1034
input                   i0_wb_stb_i;
1035
input   [`TC_AW-1:0]     i0_wb_adr_i;
1036
input   [`TC_BSW-1:0]    i0_wb_sel_i;
1037
input                   i0_wb_we_i;
1038
input   [`TC_DW-1:0]     i0_wb_dat_i;
1039
output  [`TC_DW-1:0]     i0_wb_dat_o;
1040
output                  i0_wb_ack_o;
1041
output                  i0_wb_err_o;
1042
 
1043
//
1044
// WB slave i/f connecting initiator 1
1045
//
1046
input                   i1_wb_cyc_i;
1047
input                   i1_wb_stb_i;
1048
input   [`TC_AW-1:0]     i1_wb_adr_i;
1049
input   [`TC_BSW-1:0]    i1_wb_sel_i;
1050
input                   i1_wb_we_i;
1051
input   [`TC_DW-1:0]     i1_wb_dat_i;
1052
output  [`TC_DW-1:0]     i1_wb_dat_o;
1053
output                  i1_wb_ack_o;
1054
output                  i1_wb_err_o;
1055
 
1056
//
1057
// WB slave i/f connecting initiator 2
1058
//
1059
input                   i2_wb_cyc_i;
1060
input                   i2_wb_stb_i;
1061
input   [`TC_AW-1:0]     i2_wb_adr_i;
1062
input   [`TC_BSW-1:0]    i2_wb_sel_i;
1063
input                   i2_wb_we_i;
1064
input   [`TC_DW-1:0]     i2_wb_dat_i;
1065
output  [`TC_DW-1:0]     i2_wb_dat_o;
1066
output                  i2_wb_ack_o;
1067
output                  i2_wb_err_o;
1068
 
1069
//
1070
// WB slave i/f connecting initiator 3
1071
//
1072
input                   i3_wb_cyc_i;
1073
input                   i3_wb_stb_i;
1074
input   [`TC_AW-1:0]     i3_wb_adr_i;
1075
input   [`TC_BSW-1:0]    i3_wb_sel_i;
1076
input                   i3_wb_we_i;
1077
input   [`TC_DW-1:0]     i3_wb_dat_i;
1078
output  [`TC_DW-1:0]     i3_wb_dat_o;
1079
output                  i3_wb_ack_o;
1080
output                  i3_wb_err_o;
1081
 
1082
//
1083
// WB slave i/f connecting initiator 4
1084
//
1085
input                   i4_wb_cyc_i;
1086
input                   i4_wb_stb_i;
1087
input   [`TC_AW-1:0]     i4_wb_adr_i;
1088
input   [`TC_BSW-1:0]    i4_wb_sel_i;
1089
input                   i4_wb_we_i;
1090
input   [`TC_DW-1:0]     i4_wb_dat_i;
1091
output  [`TC_DW-1:0]     i4_wb_dat_o;
1092
output                  i4_wb_ack_o;
1093
output                  i4_wb_err_o;
1094
 
1095
//
1096
// WB slave i/f connecting initiator 5
1097
//
1098
input                   i5_wb_cyc_i;
1099
input                   i5_wb_stb_i;
1100
input   [`TC_AW-1:0]     i5_wb_adr_i;
1101
input   [`TC_BSW-1:0]    i5_wb_sel_i;
1102
input                   i5_wb_we_i;
1103
input   [`TC_DW-1:0]     i5_wb_dat_i;
1104
output  [`TC_DW-1:0]     i5_wb_dat_o;
1105
output                  i5_wb_ack_o;
1106
output                  i5_wb_err_o;
1107
 
1108
//
1109
// WB slave i/f connecting initiator 6
1110
//
1111
input                   i6_wb_cyc_i;
1112
input                   i6_wb_stb_i;
1113
input   [`TC_AW-1:0]     i6_wb_adr_i;
1114
input   [`TC_BSW-1:0]    i6_wb_sel_i;
1115
input                   i6_wb_we_i;
1116
input   [`TC_DW-1:0]     i6_wb_dat_i;
1117
output  [`TC_DW-1:0]     i6_wb_dat_o;
1118
output                  i6_wb_ack_o;
1119
output                  i6_wb_err_o;
1120
 
1121
//
1122
// WB slave i/f connecting initiator 7
1123
//
1124
input                   i7_wb_cyc_i;
1125
input                   i7_wb_stb_i;
1126
input   [`TC_AW-1:0]     i7_wb_adr_i;
1127
input   [`TC_BSW-1:0]    i7_wb_sel_i;
1128
input                   i7_wb_we_i;
1129
input   [`TC_DW-1:0]     i7_wb_dat_i;
1130
output  [`TC_DW-1:0]     i7_wb_dat_o;
1131
output                  i7_wb_ack_o;
1132
output                  i7_wb_err_o;
1133
 
1134
//
1135
// WB master i/f connecting target
1136
//
1137
output                  t0_wb_cyc_o;
1138
output                  t0_wb_stb_o;
1139
output  [`TC_AW-1:0]     t0_wb_adr_o;
1140
output  [`TC_BSW-1:0]    t0_wb_sel_o;
1141
output                  t0_wb_we_o;
1142
output  [`TC_DW-1:0]     t0_wb_dat_o;
1143
input   [`TC_DW-1:0]     t0_wb_dat_i;
1144
input                   t0_wb_ack_i;
1145
input                   t0_wb_err_i;
1146
 
1147
//
1148
// Internal wires & registers
1149
//
1150
wire    [`TC_IIN_W-1:0]  i0_in, i1_in,
1151
                        i2_in, i3_in,
1152
                        i4_in, i5_in,
1153
                        i6_in, i7_in;
1154
wire    [`TC_TIN_W-1:0]  i0_out, i1_out,
1155
                        i2_out, i3_out,
1156
                        i4_out, i5_out,
1157
                        i6_out, i7_out;
1158
wire    [`TC_IIN_W-1:0]  t0_out;
1159
wire    [`TC_TIN_W-1:0]  t0_in;
1160
wire    [7:0]            req_i;
1161
wire    [2:0]            req_won;
1162
reg                     req_cont;
1163
reg     [2:0]            req_r;
1164
 
1165
//
1166
// Group WB initiator 0 i/f inputs and outputs
1167
//
1168 7 rfajardo
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
1169 2 rfajardo
                i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i};
1170
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
1171
 
1172
//
1173
// Group WB initiator 1 i/f inputs and outputs
1174
//
1175 7 rfajardo
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i,
1176 2 rfajardo
                i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i};
1177
assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out;
1178
 
1179
//
1180
// Group WB initiator 2 i/f inputs and outputs
1181
//
1182 7 rfajardo
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i,
1183 2 rfajardo
                i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i};
1184
assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out;
1185
 
1186
//
1187
// Group WB initiator 3 i/f inputs and outputs
1188
//
1189 7 rfajardo
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i,
1190 2 rfajardo
                i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i};
1191
assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out;
1192
 
1193
//
1194
// Group WB initiator 4 i/f inputs and outputs
1195
//
1196 7 rfajardo
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i,
1197 2 rfajardo
                i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i};
1198
assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out;
1199
 
1200
//
1201
// Group WB initiator 5 i/f inputs and outputs
1202
//
1203 7 rfajardo
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i,
1204 2 rfajardo
                i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i};
1205
assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out;
1206
 
1207
//
1208
// Group WB initiator 6 i/f inputs and outputs
1209
//
1210 7 rfajardo
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i,
1211 2 rfajardo
                i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i};
1212
assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out;
1213
 
1214
//
1215
// Group WB initiator 7 i/f inputs and outputs
1216
//
1217 7 rfajardo
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i,
1218 2 rfajardo
                i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i};
1219
assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out;
1220
 
1221
//
1222
// Group WB target 0 i/f inputs and outputs
1223
//
1224 7 rfajardo
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
1225 2 rfajardo
                t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out;
1226
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
1227
 
1228
//
1229
// Assign to WB initiator i/f outputs
1230
//
1231
// Either inputs from the target are assigned or zeros.
1232
//
1233
assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}};
1234
assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}};
1235
assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}};
1236
assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}};
1237
assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}};
1238
assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}};
1239
assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}};
1240
assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}};
1241
 
1242
//
1243
// Assign to WB target i/f outputs
1244
//
1245
// Assign inputs from initiator to target outputs according to
1246
// which initiator has won. If there is no request for the target,
1247
// assign zeros.
1248
//
1249
assign t0_out = (req_won == 3'd0) ? i0_in :
1250
                (req_won == 3'd1) ? i1_in :
1251
                (req_won == 3'd2) ? i2_in :
1252
                (req_won == 3'd3) ? i3_in :
1253
                (req_won == 3'd4) ? i4_in :
1254
                (req_won == 3'd5) ? i5_in :
1255
                (req_won == 3'd6) ? i6_in :
1256
                (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}};
1257
 
1258
//
1259
// Determine if an initiator has address of the target.
1260
//
1261
assign req_i[0] = i0_wb_cyc_i &
1262
        ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1263
         multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1264
assign req_i[1] = i1_wb_cyc_i &
1265
        ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1266
         multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1267
assign req_i[2] = i2_wb_cyc_i &
1268
        ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1269
         multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1270
assign req_i[3] = i3_wb_cyc_i &
1271
        ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1272
         multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1273
assign req_i[4] = i4_wb_cyc_i &
1274
        ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1275
         multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1276
assign req_i[5] = i5_wb_cyc_i &
1277
        ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1278
         multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1279
assign req_i[6] = i6_wb_cyc_i &
1280
        ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1281
         multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1282
assign req_i[7] = i7_wb_cyc_i &
1283
        ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1284
         multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1285
 
1286
//
1287
// Determine who gets current access to the target.
1288
//
1289
// If current initiator still asserts request, do nothing
1290
// (keep current initiator).
1291
// Otherwise check each initiator's request, starting from initiator 0
1292
// (highest priority).
1293
// If there is no requests from initiators, park initiator 0.
1294
//
1295
assign req_won = req_cont ? req_r :
1296
                 req_i[0] ? 3'd0 :
1297
                 req_i[1] ? 3'd1 :
1298
                 req_i[2] ? 3'd2 :
1299
                 req_i[3] ? 3'd3 :
1300
                 req_i[4] ? 3'd4 :
1301
                 req_i[5] ? 3'd5 :
1302
                 req_i[6] ? 3'd6 :
1303
                 req_i[7] ? 3'd7 : 3'd0;
1304
 
1305
//
1306
// Check if current initiator still wants access to the target and if
1307
// it does, assert req_cont.
1308
//
1309
always @(req_r or req_i)
1310
        case (req_r)    // synopsys parallel_case
1311
                3'd0: req_cont = req_i[0];
1312
                3'd1: req_cont = req_i[1];
1313
                3'd2: req_cont = req_i[2];
1314
                3'd3: req_cont = req_i[3];
1315
                3'd4: req_cont = req_i[4];
1316
                3'd5: req_cont = req_i[5];
1317
                3'd6: req_cont = req_i[6];
1318
                3'd7: req_cont = req_i[7];
1319
        endcase
1320
 
1321
//
1322
// Register who has current access to the target.
1323
//
1324
always @(posedge wb_clk_i or posedge wb_rst_i)
1325
        if (wb_rst_i)
1326
                req_r <= #1 3'd0;
1327
        else
1328
                req_r <= #1 req_won;
1329
 
1330
endmodule
1331
 
1332
//
1333
// Single initiator to multiple targets
1334
//
1335
module tc_si_to_mt (
1336
 
1337
        i0_wb_cyc_i,
1338
        i0_wb_stb_i,
1339
        i0_wb_adr_i,
1340
        i0_wb_sel_i,
1341
        i0_wb_we_i,
1342
        i0_wb_dat_i,
1343
        i0_wb_dat_o,
1344
        i0_wb_ack_o,
1345
        i0_wb_err_o,
1346
 
1347
        t0_wb_cyc_o,
1348
        t0_wb_stb_o,
1349
        t0_wb_adr_o,
1350
        t0_wb_sel_o,
1351
        t0_wb_we_o,
1352
        t0_wb_dat_o,
1353
        t0_wb_dat_i,
1354
        t0_wb_ack_i,
1355
        t0_wb_err_i,
1356
 
1357
        t1_wb_cyc_o,
1358
        t1_wb_stb_o,
1359
        t1_wb_adr_o,
1360
        t1_wb_sel_o,
1361
        t1_wb_we_o,
1362
        t1_wb_dat_o,
1363
        t1_wb_dat_i,
1364
        t1_wb_ack_i,
1365
        t1_wb_err_i,
1366
 
1367
        t2_wb_cyc_o,
1368
        t2_wb_stb_o,
1369
        t2_wb_adr_o,
1370
        t2_wb_sel_o,
1371
        t2_wb_we_o,
1372
        t2_wb_dat_o,
1373
        t2_wb_dat_i,
1374
        t2_wb_ack_i,
1375
        t2_wb_err_i,
1376
 
1377
        t3_wb_cyc_o,
1378
        t3_wb_stb_o,
1379
        t3_wb_adr_o,
1380
        t3_wb_sel_o,
1381
        t3_wb_we_o,
1382
        t3_wb_dat_o,
1383
        t3_wb_dat_i,
1384
        t3_wb_ack_i,
1385
        t3_wb_err_i,
1386
 
1387
        t4_wb_cyc_o,
1388
        t4_wb_stb_o,
1389
        t4_wb_adr_o,
1390
        t4_wb_sel_o,
1391
        t4_wb_we_o,
1392
        t4_wb_dat_o,
1393
        t4_wb_dat_i,
1394
        t4_wb_ack_i,
1395
        t4_wb_err_i,
1396
 
1397
        t5_wb_cyc_o,
1398
        t5_wb_stb_o,
1399
        t5_wb_adr_o,
1400
        t5_wb_sel_o,
1401
        t5_wb_we_o,
1402
        t5_wb_dat_o,
1403
        t5_wb_dat_i,
1404
        t5_wb_ack_i,
1405
        t5_wb_err_i,
1406
 
1407
        t6_wb_cyc_o,
1408
        t6_wb_stb_o,
1409
        t6_wb_adr_o,
1410
        t6_wb_sel_o,
1411
        t6_wb_we_o,
1412
        t6_wb_dat_o,
1413
        t6_wb_dat_i,
1414
        t6_wb_ack_i,
1415
        t6_wb_err_i,
1416
 
1417
        t7_wb_cyc_o,
1418
        t7_wb_stb_o,
1419
        t7_wb_adr_o,
1420
        t7_wb_sel_o,
1421
        t7_wb_we_o,
1422
        t7_wb_dat_o,
1423
        t7_wb_dat_i,
1424
        t7_wb_ack_i,
1425
        t7_wb_err_i
1426
 
1427
);
1428
 
1429
//
1430
// Parameters
1431
//
1432
parameter               t0_addr_w = 3;
1433
parameter               t0_addr = 3'd0;
1434
parameter               t17_addr_w = 3;
1435
parameter               t1_addr = 3'd1;
1436
parameter               t2_addr = 3'd2;
1437
parameter               t3_addr = 3'd3;
1438
parameter               t4_addr = 3'd4;
1439
parameter               t5_addr = 3'd5;
1440
parameter               t6_addr = 3'd6;
1441
parameter               t7_addr = 3'd7;
1442
 
1443
//
1444
// I/O Ports
1445
//
1446
 
1447
//
1448
// WB slave i/f connecting initiator 0
1449
//
1450
input                   i0_wb_cyc_i;
1451
input                   i0_wb_stb_i;
1452
input   [`TC_AW-1:0]     i0_wb_adr_i;
1453
input   [`TC_BSW-1:0]    i0_wb_sel_i;
1454
input                   i0_wb_we_i;
1455
input   [`TC_DW-1:0]     i0_wb_dat_i;
1456
output  [`TC_DW-1:0]     i0_wb_dat_o;
1457
output                  i0_wb_ack_o;
1458
output                  i0_wb_err_o;
1459
 
1460
//
1461
// WB master i/f connecting target 0
1462
//
1463
output                  t0_wb_cyc_o;
1464
output                  t0_wb_stb_o;
1465
output  [`TC_AW-1:0]     t0_wb_adr_o;
1466
output  [`TC_BSW-1:0]    t0_wb_sel_o;
1467
output                  t0_wb_we_o;
1468
output  [`TC_DW-1:0]     t0_wb_dat_o;
1469
input   [`TC_DW-1:0]     t0_wb_dat_i;
1470
input                   t0_wb_ack_i;
1471
input                   t0_wb_err_i;
1472
 
1473
//
1474
// WB master i/f connecting target 1
1475
//
1476
output                  t1_wb_cyc_o;
1477
output                  t1_wb_stb_o;
1478
output  [`TC_AW-1:0]     t1_wb_adr_o;
1479
output  [`TC_BSW-1:0]    t1_wb_sel_o;
1480
output                  t1_wb_we_o;
1481
output  [`TC_DW-1:0]     t1_wb_dat_o;
1482
input   [`TC_DW-1:0]     t1_wb_dat_i;
1483
input                   t1_wb_ack_i;
1484
input                   t1_wb_err_i;
1485
 
1486
//
1487
// WB master i/f connecting target 2
1488
//
1489
output                  t2_wb_cyc_o;
1490
output                  t2_wb_stb_o;
1491
output  [`TC_AW-1:0]     t2_wb_adr_o;
1492
output  [`TC_BSW-1:0]    t2_wb_sel_o;
1493
output                  t2_wb_we_o;
1494
output  [`TC_DW-1:0]     t2_wb_dat_o;
1495
input   [`TC_DW-1:0]     t2_wb_dat_i;
1496
input                   t2_wb_ack_i;
1497
input                   t2_wb_err_i;
1498
 
1499
//
1500
// WB master i/f connecting target 3
1501
//
1502
output                  t3_wb_cyc_o;
1503
output                  t3_wb_stb_o;
1504
output  [`TC_AW-1:0]     t3_wb_adr_o;
1505
output  [`TC_BSW-1:0]    t3_wb_sel_o;
1506
output                  t3_wb_we_o;
1507
output  [`TC_DW-1:0]     t3_wb_dat_o;
1508
input   [`TC_DW-1:0]     t3_wb_dat_i;
1509
input                   t3_wb_ack_i;
1510
input                   t3_wb_err_i;
1511
 
1512
//
1513
// WB master i/f connecting target 4
1514
//
1515
output                  t4_wb_cyc_o;
1516
output                  t4_wb_stb_o;
1517
output  [`TC_AW-1:0]     t4_wb_adr_o;
1518
output  [`TC_BSW-1:0]    t4_wb_sel_o;
1519
output                  t4_wb_we_o;
1520
output  [`TC_DW-1:0]     t4_wb_dat_o;
1521
input   [`TC_DW-1:0]     t4_wb_dat_i;
1522
input                   t4_wb_ack_i;
1523
input                   t4_wb_err_i;
1524
 
1525
//
1526
// WB master i/f connecting target 5
1527
//
1528
output                  t5_wb_cyc_o;
1529
output                  t5_wb_stb_o;
1530
output  [`TC_AW-1:0]     t5_wb_adr_o;
1531
output  [`TC_BSW-1:0]    t5_wb_sel_o;
1532
output                  t5_wb_we_o;
1533
output  [`TC_DW-1:0]     t5_wb_dat_o;
1534
input   [`TC_DW-1:0]     t5_wb_dat_i;
1535
input                   t5_wb_ack_i;
1536
input                   t5_wb_err_i;
1537
 
1538
//
1539
// WB master i/f connecting target 6
1540
//
1541
output                  t6_wb_cyc_o;
1542
output                  t6_wb_stb_o;
1543
output  [`TC_AW-1:0]     t6_wb_adr_o;
1544
output  [`TC_BSW-1:0]    t6_wb_sel_o;
1545
output                  t6_wb_we_o;
1546
output  [`TC_DW-1:0]     t6_wb_dat_o;
1547
input   [`TC_DW-1:0]     t6_wb_dat_i;
1548
input                   t6_wb_ack_i;
1549
input                   t6_wb_err_i;
1550
 
1551
//
1552
// WB master i/f connecting target 7
1553
//
1554
output                  t7_wb_cyc_o;
1555
output                  t7_wb_stb_o;
1556
output  [`TC_AW-1:0]     t7_wb_adr_o;
1557
output  [`TC_BSW-1:0]    t7_wb_sel_o;
1558
output                  t7_wb_we_o;
1559
output  [`TC_DW-1:0]     t7_wb_dat_o;
1560
input   [`TC_DW-1:0]     t7_wb_dat_i;
1561
input                   t7_wb_ack_i;
1562
input                   t7_wb_err_i;
1563
 
1564
//
1565
// Internal wires & registers
1566
//
1567
wire    [`TC_IIN_W-1:0]  i0_in;
1568
wire    [`TC_TIN_W-1:0]  i0_out;
1569
wire    [`TC_IIN_W-1:0]  t0_out, t1_out,
1570
                        t2_out, t3_out,
1571
                        t4_out, t5_out,
1572
                        t6_out, t7_out;
1573
wire    [`TC_TIN_W-1:0]  t0_in, t1_in,
1574
                        t2_in, t3_in,
1575
                        t4_in, t5_in,
1576
                        t6_in, t7_in;
1577
wire    [7:0]            req_t;
1578
 
1579
//
1580
// Group WB initiator 0 i/f inputs and outputs
1581
//
1582 7 rfajardo
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
1583 2 rfajardo
                i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i};
1584
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
1585
 
1586
//
1587
// Group WB target 0 i/f inputs and outputs
1588
//
1589 7 rfajardo
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
1590 2 rfajardo
                t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o} = t0_out;
1591
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
1592
 
1593
//
1594
// Group WB target 1 i/f inputs and outputs
1595
//
1596 7 rfajardo
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o,
1597 2 rfajardo
                t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o} = t1_out;
1598
assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i};
1599
 
1600
//
1601
// Group WB target 2 i/f inputs and outputs
1602
//
1603 7 rfajardo
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o,
1604 2 rfajardo
                t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o} = t2_out;
1605
assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i};
1606
 
1607
//
1608
// Group WB target 3 i/f inputs and outputs
1609
//
1610 7 rfajardo
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o,
1611 2 rfajardo
                t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o} = t3_out;
1612
assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i};
1613
 
1614
//
1615
// Group WB target 4 i/f inputs and outputs
1616
//
1617 7 rfajardo
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o,
1618 2 rfajardo
                t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o} = t4_out;
1619
assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i};
1620
 
1621
//
1622
// Group WB target 5 i/f inputs and outputs
1623
//
1624 7 rfajardo
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o,
1625 2 rfajardo
                t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o} = t5_out;
1626
assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i};
1627
 
1628
//
1629
// Group WB target 6 i/f inputs and outputs
1630
//
1631 7 rfajardo
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o,
1632 2 rfajardo
                t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o} = t6_out;
1633
assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i};
1634
 
1635
//
1636
// Group WB target 7 i/f inputs and outputs
1637
//
1638 7 rfajardo
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o,
1639 2 rfajardo
                t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o} = t7_out;
1640
assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i};
1641
 
1642
//
1643
// Assign to WB target i/f outputs
1644
//
1645
// Either inputs from the initiator are assigned or zeros.
1646
//
1647
assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}};
1648
assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}};
1649
assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}};
1650
assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}};
1651
assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}};
1652
assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}};
1653
assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}};
1654
assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}};
1655
 
1656
//
1657
// Assign to WB initiator i/f outputs
1658
//
1659
// Assign inputs from target to initiator outputs according to
1660
// which target is accessed. If there is no request for a target,
1661
// assign zeros.
1662
//
1663
assign i0_out = req_t[0] ? t0_in :
1664
                req_t[1] ? t1_in :
1665
                req_t[2] ? t2_in :
1666
                req_t[3] ? t3_in :
1667
                req_t[4] ? t4_in :
1668
                req_t[5] ? t5_in :
1669
                req_t[6] ? t6_in :
1670
                req_t[7] ? t7_in : {`TC_TIN_W{1'b0}};
1671
 
1672
//
1673
// Determine which target is being accessed.
1674
//
1675
assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr);
1676
assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr);
1677
assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr);
1678
assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr);
1679
assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr);
1680
assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr);
1681
assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr);
1682
assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr);
1683
 
1684
endmodule

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