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1 2 rfajardo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1K test application for XESS XSV board, Top Level         ////
4
////                                                              ////
5
////  This file is part of the OR1K test application              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Top level instantiating all the blocks.                     ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - nothing really                                           ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2001 Authors                                   ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: xsv_fpga_top.v,v $
47
// Revision 1.10  2004/04/05 08:44:35  lampret
48
// Merged branch_qmem into main tree.
49
//
50
// Revision 1.8  2003/04/07 21:05:58  lampret
51
// WB = 1/2 RISC clock test code enabled.
52
//
53
// Revision 1.7  2003/04/07 01:28:17  lampret
54
// Adding OR1200_CLMODE_1TO2 test code.
55
//
56
// Revision 1.6  2002/08/12 05:35:12  lampret
57
// rty_i are unused - tied to zero.
58
//
59
// Revision 1.5  2002/03/29 20:58:51  lampret
60
// Changed hardcoded address for fake MC to use a define.
61
//
62
// Revision 1.4  2002/03/29 16:30:47  lampret
63
// Fixed port names that changed.
64
//
65
// Revision 1.3  2002/03/29 15:50:03  lampret
66
// Added response from memory controller (addr 0x60000000)
67
//
68
// Revision 1.2  2002/03/21 17:39:16  lampret
69
// Fixed some typos
70
//
71
//
72
 
73
`include "minsoc_defines.v"
74
`include "or1200_defines.v"
75
 
76
module minsoc_top (
77
   clk,reset
78
 
79
   //JTAG ports
80
`ifdef GENERIC_TAP
81
   , jtag_tdi,jtag_tms,jtag_tck,
82
   jtag_tdo,jtag_vref,jtag_gnd
83
`endif
84
 
85
   //SPI ports
86
`ifdef START_UP
87
   , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss
88
`endif
89
 
90
   //UART ports
91
`ifdef UART
92
   , uart_stx,uart_srx
93
`endif
94
 
95
        // Ethernet ports
96
`ifdef ETHERNET
97
        , eth_col, eth_crs, eth_trste, eth_tx_clk,
98
        eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk,
99
        eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint,
100
        eth_mdc, eth_mdio
101
`endif
102
);
103
 
104
//
105
// I/O Ports
106
//
107
 
108
   input         clk;
109
   input         reset;
110
 
111
//
112
// SPI controller external i/f wires
113
//
114
`ifdef START_UP
115
output spi_flash_mosi;
116
input spi_flash_miso;
117
output spi_flash_sclk;
118
output [1:0] spi_flash_ss;
119
`endif
120
 
121
//
122
// UART
123
//
124
`ifdef UART
125
   output        uart_stx;
126
   input         uart_srx;
127
`endif
128
 
129
//
130
// Ethernet
131
//
132
`ifdef ETHERNET
133
output                  eth_tx_er;
134
input                   eth_tx_clk;
135
output                  eth_tx_en;
136
output  [3:0]            eth_txd;
137
input                   eth_rx_er;
138
input                   eth_rx_clk;
139
input                   eth_rx_dv;
140
input   [3:0]            eth_rxd;
141
input                   eth_col;
142
input                   eth_crs;
143
output                  eth_trste;
144
input                   eth_fds_mdint;
145
inout                   eth_mdio;
146
output                  eth_mdc;
147
`endif
148
 
149
//
150
// JTAG
151
//
152
`ifdef GENERIC_TAP
153
   input         jtag_tdi;
154
   input         jtag_tms;
155
   input         jtag_tck;
156
   output        jtag_tdo;
157
   output        jtag_vref;
158
   output        jtag_gnd;
159
 
160
 
161
assign jtag_vref = 1'b1;
162
assign jtag_gnd = 1'b0;
163
`endif
164
 
165
wire rstn;
166
 
167
assign rstn = ~reset;
168
 
169
//
170
// Internal wires
171
//
172
 
173
//
174
// Debug core master i/f wires
175
//
176
wire    [31:0]           wb_dm_adr_o;
177
wire    [31:0]           wb_dm_dat_i;
178
wire    [31:0]           wb_dm_dat_o;
179
wire    [3:0]            wb_dm_sel_o;
180
wire                    wb_dm_we_o;
181
wire                    wb_dm_stb_o;
182
wire                    wb_dm_cyc_o;
183
wire                    wb_dm_cab_o;
184
wire                    wb_dm_ack_i;
185
wire                    wb_dm_err_i;
186
 
187
//
188
// Debug <-> RISC wires
189
//
190
wire    [3:0]            dbg_lss;
191
wire    [1:0]            dbg_is;
192
wire    [10:0]           dbg_wp;
193
wire                    dbg_bp;
194
wire    [31:0]           dbg_dat_dbg;
195
wire    [31:0]           dbg_dat_risc;
196
wire    [31:0]           dbg_adr;
197
wire                    dbg_ewt;
198
wire                    dbg_stall;
199
wire    [2:0]            dbg_op;     //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb  (didn't change for backward compatibility with DBG_IF_MODEL
200
wire                    dbg_ack;
201
 
202
//
203
// RISC instruction master i/f wires
204
//
205
wire    [31:0]           wb_rim_adr_o;
206
wire                    wb_rim_cyc_o;
207
wire    [31:0]           wb_rim_dat_i;
208
wire    [31:0]           wb_rim_dat_o;
209
wire    [3:0]            wb_rim_sel_o;
210
wire                    wb_rim_ack_i;
211
wire                    wb_rim_err_i;
212
wire                    wb_rim_rty_i = 1'b0;
213
wire                    wb_rim_we_o;
214
wire                    wb_rim_stb_o;
215
wire                    wb_rim_cab_o;
216
wire    [31:0]           wb_rif_dat_i;
217
wire                    wb_rif_ack_i;
218
 
219
//
220
// RISC data master i/f wires
221
//
222
wire    [31:0]           wb_rdm_adr_o;
223
wire                    wb_rdm_cyc_o;
224
wire    [31:0]           wb_rdm_dat_i;
225
wire    [31:0]           wb_rdm_dat_o;
226
wire    [3:0]            wb_rdm_sel_o;
227
wire                    wb_rdm_ack_i;
228
wire                    wb_rdm_err_i;
229
wire                    wb_rdm_rty_i = 1'b0;
230
wire                    wb_rdm_we_o;
231
wire                    wb_rdm_stb_o;
232
wire                    wb_rdm_cab_o;
233
 
234
//
235
// RISC misc
236
//
237
wire    [19:0]           pic_ints;
238
 
239
//
240
// Flash controller slave i/f wires
241
//
242
wire    [31:0]           wb_fs_dat_i;
243
wire    [31:0]           wb_fs_dat_o;
244
wire    [31:0]           wb_fs_adr_i;
245
wire    [3:0]            wb_fs_sel_i;
246
wire                    wb_fs_we_i;
247
wire                    wb_fs_cyc_i;
248
wire                    wb_fs_stb_i;
249
wire                    wb_fs_ack_o;
250
wire                    wb_fs_err_o;
251
 
252
//
253
// SPI controller slave i/f wires
254
//
255
wire    [31:0]           wb_sp_dat_i;
256
wire    [31:0]           wb_sp_dat_o;
257
wire    [31:0]           wb_sp_adr_i;
258
wire    [3:0]            wb_sp_sel_i;
259
wire                    wb_sp_we_i;
260
wire                    wb_sp_cyc_i;
261
wire                    wb_sp_stb_i;
262
wire                    wb_sp_ack_o;
263
wire                    wb_sp_err_o;
264
 
265
//
266
// SPI controller external i/f wires
267
//
268
wire spi_flash_mosi;
269
wire spi_flash_miso;
270
wire spi_flash_sclk;
271
wire [1:0] spi_flash_ss;
272
 
273
//
274
// SRAM controller slave i/f wires
275
//
276
wire    [31:0]           wb_ss_dat_i;
277
wire    [31:0]           wb_ss_dat_o;
278
wire    [31:0]           wb_ss_adr_i;
279
wire    [3:0]            wb_ss_sel_i;
280
wire                    wb_ss_we_i;
281
wire                    wb_ss_cyc_i;
282
wire                    wb_ss_stb_i;
283
wire                    wb_ss_ack_o;
284
wire                    wb_ss_err_o;
285
 
286
//
287
// Ethernet core master i/f wires
288
//
289
wire    [31:0]           wb_em_adr_o;
290
wire    [31:0]           wb_em_dat_i;
291
wire    [31:0]           wb_em_dat_o;
292
wire    [3:0]            wb_em_sel_o;
293
wire                    wb_em_we_o;
294
wire                    wb_em_stb_o;
295
wire                    wb_em_cyc_o;
296
wire                    wb_em_cab_o;
297
wire                    wb_em_ack_i;
298
wire                    wb_em_err_i;
299
 
300
//
301
// Ethernet core slave i/f wires
302
//
303
wire    [31:0]           wb_es_dat_i;
304
wire    [31:0]           wb_es_dat_o;
305
wire    [31:0]           wb_es_adr_i;
306
wire    [3:0]            wb_es_sel_i;
307
wire                    wb_es_we_i;
308
wire                    wb_es_cyc_i;
309
wire                    wb_es_stb_i;
310
wire                    wb_es_ack_o;
311
wire                    wb_es_err_o;
312
 
313
//
314
// Ethernet external i/f wires
315
//
316
wire                    eth_mdo;
317
wire                    eth_mdoe;
318
 
319
//
320
// UART16550 core slave i/f wires
321
//
322
wire    [31:0]           wb_us_dat_i;
323
wire    [31:0]           wb_us_dat_o;
324
wire    [31:0]           wb_us_adr_i;
325
wire    [3:0]            wb_us_sel_i;
326
wire                    wb_us_we_i;
327
wire                    wb_us_cyc_i;
328
wire                    wb_us_stb_i;
329
wire                    wb_us_ack_o;
330
wire                    wb_us_err_o;
331
 
332
//
333
// UART external i/f wires
334
//
335
wire                    uart_stx;
336
wire                    uart_srx;
337
 
338
//
339
// Reset debounce
340
//
341
reg                     rst_r;
342
reg                     wb_rst;
343
 
344
//
345
// Global clock
346
//
347
`ifdef OR1200_CLMODE_1TO2
348
reg                     wb_clk;
349
`else
350
wire                    wb_clk;
351
`endif
352
 
353
//
354
// Reset debounce
355
//
356
always @(posedge wb_clk or negedge rstn)
357
        if (~rstn)
358
                rst_r <= 1'b1;
359
        else
360
                rst_r <= #1 1'b0;
361
 
362
//
363
// Reset debounce
364
//
365
always @(posedge wb_clk)
366
        wb_rst <= #1 rst_r;
367
 
368
//
369
// This is purely for testing 1/2 WB clock
370
// This should never be used when implementing in
371
// an FPGA. It is used only for simulation regressions.
372
//
373
`ifdef OR1200_CLMODE_1TO2
374
initial wb_clk = 0;
375
always @(posedge clk)
376
        wb_clk = ~wb_clk;
377
`else
378
minsoc_clock_manager #
379
(
380
   .divisor(`CLOCK_DIVISOR)
381
)
382
clk_adjust (
383
        .clk_i(clk),
384
        .clk_o(wb_clk)
385
);
386
`endif // OR1200_CLMODE_1TO2
387
 
388
//
389
// Unused WISHBONE signals
390
//
391
assign wb_us_err_o = 1'b0;
392
assign wb_em_cab_o = 1'b0;
393
assign wb_fs_err_o = 1'b0;
394
assign wb_sp_err_o = 1'b0;
395
 
396
//
397
// Unused interrupts
398
//
399
assign pic_ints[`APP_INT_RES1] = 'b0;
400
assign pic_ints[`APP_INT_RES2] = 'b0;
401
assign pic_ints[`APP_INT_RES3] = 'b0;
402
assign pic_ints[`APP_INT_PS2] = 'b0;
403
 
404
//
405
// Ethernet tri-state
406
//
407
`ifdef ETHERNET
408
assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz;
409
assign eth_trste = `ETH_RESET;
410
`endif
411
 
412
 
413
//
414
// RISC Instruction address for Flash
415
//
416
// Until first access to real Flash area,
417
// CPU instruction is fixed to jump to the Flash area.
418
// After Flash area is accessed, CPU instructions 
419
// come from the tc_top (wishbone "switch").
420
//
421
`ifdef START_UP
422
reg jump_flash;
423
reg [3:0] rif_counter;
424
reg [31:0] rif_dat_int;
425
reg rif_ack_int;
426
 
427
always @(posedge wb_clk or negedge rstn)
428
begin
429
        if (!rstn) begin
430
                jump_flash <= #1 1'b1;
431
                rif_counter <= 4'h0;
432
                rif_ack_int <= 1'b0;
433
        end
434
        else begin
435
                rif_ack_int <= 1'b0;
436
 
437
                if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
438
                        jump_flash <= #1 1'b0;
439
 
440
                if ( jump_flash == 1'b1 ) begin
441
                        if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) begin
442
                                rif_counter <= rif_counter + 1'b1;
443
                                rif_ack_int <= 1'b1;
444
                        end
445
                end
446
        end
447
end
448
 
449
always @ (rif_counter)
450
begin
451
        case ( rif_counter )
452
                4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 };
453
                4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 };
454
                4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 };
455
                4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 };
456
                default: rif_dat_int = 32'h0000_0000;
457
        endcase
458
end
459
 
460
assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i;
461
 
462
assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i;
463
 
464
`else
465
assign wb_rif_dat_i = wb_rim_dat_i;
466
assign wb_rif_ack_i = wb_rim_ack_i;
467
`endif
468
 
469
 
470
//
471
// TAP<->dbg_interface
472
//      
473
wire jtag_tck;
474
wire debug_tdi;
475
wire debug_tdo;
476
wire capture_dr;
477
wire shift_dr;
478
wire pause_dr;
479
wire update_dr;
480
 
481
wire debug_select;
482
wire test_logic_reset;
483
 
484
//
485
// Instantiation of the development i/f
486
//
487
adbg_top dbg_top  (
488
 
489
        // JTAG pins
490
      .tck_i    ( jtag_tck ),
491
      .tdi_i    ( debug_tdi ),
492
      .tdo_o    ( debug_tdo ),
493
      .rst_i    ( test_logic_reset ),           //cable without rst
494
 
495
        // Boundary Scan signals
496
      .capture_dr_i ( capture_dr ),
497
      .shift_dr_i  ( shift_dr ),
498
      .pause_dr_i  ( pause_dr ),
499
      .update_dr_i ( update_dr ),
500
 
501
      .debug_select_i( debug_select ),
502
        // WISHBONE common
503
      .wb_clk_i   ( wb_clk ),
504
 
505
      // WISHBONE master interface
506
      .wb_adr_o  ( wb_dm_adr_o ),
507
      .wb_dat_i  ( wb_dm_dat_i ),
508
      .wb_dat_o  ( wb_dm_dat_o ),
509
      .wb_sel_o  ( wb_dm_sel_o ),
510
      .wb_we_o   ( wb_dm_we_o  ),
511
      .wb_stb_o  ( wb_dm_stb_o ),
512
      .wb_cyc_o  ( wb_dm_cyc_o ),
513
      .wb_cab_o  ( wb_dm_cab_o ),
514
      .wb_ack_i  ( wb_dm_ack_i ),
515
      .wb_err_i  ( wb_dm_err_i ),
516
      .wb_cti_o  ( ),
517
      .wb_bte_o  ( ),
518
 
519
      // RISC signals
520
      .cpu0_clk_i  ( wb_clk ),
521
      .cpu0_addr_o ( dbg_adr ),
522
      .cpu0_data_i ( dbg_dat_risc ),
523
      .cpu0_data_o ( dbg_dat_dbg ),
524
      .cpu0_bp_i   ( dbg_bp ),
525
      .cpu0_stall_o( dbg_stall ),
526
      .cpu0_stb_o  ( dbg_op[2] ),
527
      .cpu0_we_o   ( dbg_op[0] ),
528
      .cpu0_ack_i  ( dbg_ack ),
529
      .cpu0_rst_o  ( )
530
 
531
);
532
 
533
//
534
// JTAG TAP controller instantiation
535
//
536
`ifdef GENERIC_TAP
537
tap_top tap_top(
538
         // JTAG pads
539
         .tms_pad_i(jtag_tms),
540
         .tck_pad_i(jtag_tck),
541
         .trstn_pad_i(rstn),
542
         .tdi_pad_i(jtag_tdi),
543
         .tdo_pad_o(jtag_tdo),
544
         .tdo_padoe_o( ),
545
 
546
         // TAP states
547
         .test_logic_reset_o( test_logic_reset ),
548
         .run_test_idle_o(),
549
         .shift_dr_o(shift_dr),
550
         .pause_dr_o(pause_dr),
551
         .update_dr_o(update_dr),
552
         .capture_dr_o(capture_dr),
553
 
554
         // Select signals for boundary scan or mbist
555
         .extest_select_o(),
556
         .sample_preload_select_o(),
557
         .mbist_select_o(),
558
         .debug_select_o(debug_select),
559
 
560
         // TDO signal that is connected to TDI of sub-modules.
561
         .tdi_o(debug_tdi),
562
 
563
         // TDI signals from sub-modules
564
         .debug_tdo_i(debug_tdo),    // from debug module
565
         .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
566
         .mbist_tdo_i(1'b0)     // from Mbist Chain
567
);
568
`elsif FPGA_TAP
569
`ifdef ALTERA_FPGA
570
altera_virtual_jtag tap_top(
571
        .tck_o(jtag_tck),
572
        .debug_tdo_o(debug_tdo),
573
        .tdi_o(debug_tdi),
574
        .test_logic_reset_o(test_logic_reset),
575
        .run_test_idle_o(),
576
        .shift_dr_o(shift_dr),
577
        .capture_dr_o(capture_dr),
578
        .pause_dr_o(pause_dr),
579
        .update_dr_o(update_dr),
580
        .debug_select_o(debug_select)
581
);
582
`elsif XILINX_FPGA
583
minsoc_xilinx_internal_jtag tap_top(
584
        .tck_o( jtag_tck ),
585
        .debug_tdo_i( debug_tdo ),
586
        .tdi_o( debug_tdi ),
587
 
588
        .test_logic_reset_o( test_logic_reset ),
589
        .run_test_idle_o( ),
590
 
591
        .shift_dr_o( shift_dr ),
592
        .capture_dr_o( capture_dr ),
593
        .pause_dr_o( pause_dr ),
594
        .update_dr_o( update_dr ),
595
        .debug_select_o( debug_select )
596
);
597
`endif // !FPGA_TAP
598
 
599
`endif // !GENERIC_TAP
600
 
601
//
602
// Instantiation of the OR1200 RISC
603
//
604
or1200_top or1200_top (
605
 
606
        // Common
607
        .rst_i          ( wb_rst ),
608
        .clk_i          ( wb_clk ),
609
`ifdef OR1200_CLMODE_1TO2
610
        .clmode_i       ( 2'b01 ),
611
`else
612
`ifdef OR1200_CLMODE_1TO4
613
        .clmode_i       ( 2'b11 ),
614
`else
615
        .clmode_i       ( 2'b00 ),
616
`endif
617
`endif
618
 
619
        // WISHBONE Instruction Master
620
        .iwb_clk_i      ( wb_clk ),
621
        .iwb_rst_i      ( wb_rst ),
622
        .iwb_cyc_o      ( wb_rim_cyc_o ),
623
        .iwb_adr_o      ( wb_rim_adr_o ),
624
        .iwb_dat_i      ( wb_rif_dat_i ),
625
        .iwb_dat_o      ( wb_rim_dat_o ),
626
        .iwb_sel_o      ( wb_rim_sel_o ),
627
        .iwb_ack_i      ( wb_rif_ack_i ),
628
        .iwb_err_i      ( wb_rim_err_i ),
629
        .iwb_rty_i      ( wb_rim_rty_i ),
630
        .iwb_we_o       ( wb_rim_we_o  ),
631
        .iwb_stb_o      ( wb_rim_stb_o ),
632
        .iwb_cab_o      ( wb_rim_cab_o ),
633
 
634
        // WISHBONE Data Master
635
        .dwb_clk_i      ( wb_clk ),
636
        .dwb_rst_i      ( wb_rst ),
637
        .dwb_cyc_o      ( wb_rdm_cyc_o ),
638
        .dwb_adr_o      ( wb_rdm_adr_o ),
639
        .dwb_dat_i      ( wb_rdm_dat_i ),
640
        .dwb_dat_o      ( wb_rdm_dat_o ),
641
        .dwb_sel_o      ( wb_rdm_sel_o ),
642
        .dwb_ack_i      ( wb_rdm_ack_i ),
643
        .dwb_err_i      ( wb_rdm_err_i ),
644
        .dwb_rty_i      ( wb_rdm_rty_i ),
645
        .dwb_we_o       ( wb_rdm_we_o  ),
646
        .dwb_stb_o      ( wb_rdm_stb_o ),
647
        .dwb_cab_o      ( wb_rdm_cab_o ),
648
 
649
        // Debug
650
        .dbg_stall_i    ( dbg_stall ),
651
        .dbg_dat_i      ( dbg_dat_dbg ),
652
        .dbg_adr_i      ( dbg_adr ),
653
        .dbg_ewt_i      ( 1'b0 ),
654
        .dbg_lss_o      ( dbg_lss ),
655
        .dbg_is_o       ( dbg_is ),
656
        .dbg_wp_o       ( dbg_wp ),
657
        .dbg_bp_o       ( dbg_bp ),
658
        .dbg_dat_o      ( dbg_dat_risc ),
659
        .dbg_ack_o      ( dbg_ack ),
660
        .dbg_stb_i      ( dbg_op[2] ),
661
        .dbg_we_i       ( dbg_op[0] ),
662
 
663
        // Power Management
664
        .pm_clksd_o     ( ),
665
        .pm_cpustall_i  ( 1'b0 ),
666
        .pm_dc_gate_o   ( ),
667
        .pm_ic_gate_o   ( ),
668
        .pm_dmmu_gate_o ( ),
669
        .pm_immu_gate_o ( ),
670
        .pm_tt_gate_o   ( ),
671
        .pm_cpu_gate_o  ( ),
672
        .pm_wakeup_o    ( ),
673
        .pm_lvolt_o     ( ),
674
 
675
        // Interrupts
676
        .pic_ints_i     ( pic_ints )
677
);
678
 
679
//
680
// Startup OR1k
681
//
682
`ifdef START_UP
683
OR1K_startup OR1K_startup0
684
(
685
    .wb_adr_i(wb_fs_adr_i[6:2]),
686
    .wb_stb_i(wb_fs_stb_i),
687
    .wb_cyc_i(wb_fs_cyc_i),
688
    .wb_dat_o(wb_fs_dat_o),
689
    .wb_ack_o(wb_fs_ack_o),
690
    .wb_clk(wb_clk),
691
    .wb_rst(wb_rst)
692
);
693
 
694
spi_flash_top #
695
(
696
   .divider(0),
697
   .divider_len(2)
698
)
699
spi_flash_top0
700
(
701
   .wb_clk_i(wb_clk),
702
   .wb_rst_i(wb_rst),
703
   .wb_adr_i(wb_sp_adr_i[4:2]),
704
   .wb_dat_i(wb_sp_dat_i),
705
   .wb_dat_o(wb_sp_dat_o),
706
   .wb_sel_i(wb_sp_sel_i),
707
   .wb_we_i(wb_sp_we_i),
708
   .wb_stb_i(wb_sp_stb_i),
709
   .wb_cyc_i(wb_sp_cyc_i),
710
   .wb_ack_o(wb_sp_ack_o),
711
 
712
   .mosi_pad_o(spi_flash_mosi),
713
   .miso_pad_i(spi_flash_miso),
714
   .sclk_pad_o(spi_flash_sclk),
715
   .ss_pad_o(spi_flash_ss)
716
);
717
`else
718
assign wb_fs_dat_o = 32'h0000_0000;
719
assign wb_fs_ack_o = 1'b0;
720
assign wb_sp_dat_o = 32'h0000_0000;
721
assign wb_sp_ack_o = 1'b0;
722
`endif
723
 
724
//
725
// Instantiation of the SRAM controller
726
//
727
minsoc_onchip_ram_top #
728
(
729
    .adr_width(`MEMORY_ADR_WIDTH)     //16 blocks of 2048 bytes memory 32768
730
)
731
onchip_ram_top (
732
 
733
        // WISHBONE common
734
        .wb_clk_i       ( wb_clk ),
735
        .wb_rst_i       ( wb_rst ),
736
 
737
        // WISHBONE slave
738
        .wb_dat_i       ( wb_ss_dat_i ),
739
        .wb_dat_o       ( wb_ss_dat_o ),
740
        .wb_adr_i       ( wb_ss_adr_i ),
741
        .wb_sel_i       ( wb_ss_sel_i ),
742
        .wb_we_i        ( wb_ss_we_i  ),
743
        .wb_cyc_i       ( wb_ss_cyc_i ),
744
        .wb_stb_i       ( wb_ss_stb_i ),
745
        .wb_ack_o       ( wb_ss_ack_o ),
746
        .wb_err_o       ( wb_ss_err_o )
747
);
748
 
749
//
750
// Instantiation of the UART16550
751
//
752
`ifdef UART
753
uart_top uart_top (
754
 
755
        // WISHBONE common
756
        .wb_clk_i       ( wb_clk ),
757
        .wb_rst_i       ( wb_rst ),
758
 
759
        // WISHBONE slave
760
        .wb_adr_i       ( wb_us_adr_i[4:0] ),
761
        .wb_dat_i       ( wb_us_dat_i ),
762
        .wb_dat_o       ( wb_us_dat_o ),
763
        .wb_we_i        ( wb_us_we_i  ),
764
        .wb_stb_i       ( wb_us_stb_i ),
765
        .wb_cyc_i       ( wb_us_cyc_i ),
766
        .wb_ack_o       ( wb_us_ack_o ),
767
        .wb_sel_i       ( wb_us_sel_i ),
768
 
769
        // Interrupt request
770
        .int_o          ( pic_ints[`APP_INT_UART] ),
771
 
772
        // UART signals
773
        // serial input/output
774
        .stx_pad_o      ( uart_stx ),
775
        .srx_pad_i      ( uart_srx ),
776
 
777
        // modem signals
778
        .rts_pad_o      ( ),
779
        .cts_pad_i      ( 1'b0 ),
780
        .dtr_pad_o      ( ),
781
        .dsr_pad_i      ( 1'b0 ),
782
        .ri_pad_i       ( 1'b0 ),
783
        .dcd_pad_i      ( 1'b0 )
784
);
785
`else
786
assign wb_us_dat_o = 32'h0000_0000;
787
assign wb_us_ack_o = 1'b0;
788
`endif
789
 
790
//
791
// Instantiation of the Ethernet 10/100 MAC
792
//
793
`ifdef ETHERNET
794
eth_top eth_top (
795
 
796
        // WISHBONE common
797
        .wb_clk_i       ( wb_clk ),
798
        .wb_rst_i       ( wb_rst ),
799
 
800
        // WISHBONE slave
801
        .wb_dat_i       ( wb_es_dat_i ),
802
        .wb_dat_o       ( wb_es_dat_o ),
803
        .wb_adr_i       ( wb_es_adr_i[11:2] ),
804
        .wb_sel_i       ( wb_es_sel_i ),
805
        .wb_we_i        ( wb_es_we_i  ),
806
        .wb_cyc_i       ( wb_es_cyc_i ),
807
        .wb_stb_i       ( wb_es_stb_i ),
808
        .wb_ack_o       ( wb_es_ack_o ),
809
        .wb_err_o       ( wb_es_err_o ),
810
 
811
        // WISHBONE master
812
        .m_wb_adr_o     ( wb_em_adr_o ),
813
        .m_wb_sel_o     ( wb_em_sel_o ),
814
        .m_wb_we_o      ( wb_em_we_o  ),
815
        .m_wb_dat_o     ( wb_em_dat_o ),
816
        .m_wb_dat_i     ( wb_em_dat_i ),
817
        .m_wb_cyc_o     ( wb_em_cyc_o ),
818
        .m_wb_stb_o     ( wb_em_stb_o ),
819
        .m_wb_ack_i     ( wb_em_ack_i ),
820
        .m_wb_err_i     ( wb_em_err_i ),
821
 
822
        // TX
823
        .mtx_clk_pad_i  ( eth_tx_clk ),
824
        .mtxd_pad_o     ( eth_txd ),
825
        .mtxen_pad_o    ( eth_tx_en ),
826
        .mtxerr_pad_o   ( eth_tx_er ),
827
 
828
        // RX
829
        .mrx_clk_pad_i  ( eth_rx_clk ),
830
        .mrxd_pad_i     ( eth_rxd ),
831
        .mrxdv_pad_i    ( eth_rx_dv ),
832
        .mrxerr_pad_i   ( eth_rx_er ),
833
        .mcoll_pad_i    ( eth_col ),
834
        .mcrs_pad_i     ( eth_crs ),
835
 
836
        // MIIM
837
        .mdc_pad_o      ( eth_mdc ),
838
        .md_pad_i       ( eth_mdio ),
839
        .md_pad_o       ( eth_mdo ),
840
        .md_padoe_o     ( eth_mdoe ),
841
 
842
        // Interrupt
843
        .int_o          ( pic_ints[`APP_INT_ETH] )
844
);
845
`else
846
assign wb_es_dat_o = 32'h0000_0000;
847
assign wb_es_ack_o = 1'b0;
848
 
849
assign wb_em_adr_o = 32'h0000_0000;
850
assign wb_em_sel_o = 4'h0;
851
assign wb_em_we_o = 1'b0;
852
assign wb_em_dat_o = 32'h0000_0000;
853
assign wb_em_cyc_o = 1'b0;
854
assign wb_em_stb_o = 1'b0;
855
`endif
856
 
857
//
858
// Instantiation of the Traffic COP
859
//
860
minsoc_tc_top #(`APP_ADDR_DEC_W,
861
         `APP_ADDR_SRAM,
862
         `APP_ADDR_DEC_W,
863
         `APP_ADDR_FLASH,
864
         `APP_ADDR_DECP_W,
865
         `APP_ADDR_PERIP,
866
         `APP_ADDR_DEC_W,
867
         `APP_ADDR_SPI,
868
         `APP_ADDR_ETH,
869
         `APP_ADDR_AUDIO,
870
         `APP_ADDR_UART,
871
         `APP_ADDR_PS2,
872
         `APP_ADDR_RES1,
873
         `APP_ADDR_RES2
874
        ) tc_top (
875
 
876
        // WISHBONE common
877
        .wb_clk_i       ( wb_clk ),
878
        .wb_rst_i       ( wb_rst ),
879
 
880
        // WISHBONE Initiator 0
881
        .i0_wb_cyc_i    ( 1'b0 ),
882
        .i0_wb_stb_i    ( 1'b0 ),
883
        .i0_wb_cab_i    ( 1'b0 ),
884
        .i0_wb_adr_i    ( 32'h0000_0000 ),
885
        .i0_wb_sel_i    ( 4'b0000 ),
886
        .i0_wb_we_i     ( 1'b0 ),
887
        .i0_wb_dat_i    ( 32'h0000_0000 ),
888
        .i0_wb_dat_o    ( ),
889
        .i0_wb_ack_o    ( ),
890
        .i0_wb_err_o    ( ),
891
 
892
        // WISHBONE Initiator 1
893
        .i1_wb_cyc_i    ( wb_em_cyc_o ),
894
        .i1_wb_stb_i    ( wb_em_stb_o ),
895
        .i1_wb_cab_i    ( wb_em_cab_o ),
896
        .i1_wb_adr_i    ( wb_em_adr_o ),
897
        .i1_wb_sel_i    ( wb_em_sel_o ),
898
        .i1_wb_we_i     ( wb_em_we_o  ),
899
        .i1_wb_dat_i    ( wb_em_dat_o ),
900
        .i1_wb_dat_o    ( wb_em_dat_i ),
901
        .i1_wb_ack_o    ( wb_em_ack_i ),
902
        .i1_wb_err_o    ( wb_em_err_i ),
903
 
904
        // WISHBONE Initiator 2
905
        .i2_wb_cyc_i    ( 1'b0 ),
906
        .i2_wb_stb_i    ( 1'b0 ),
907
        .i2_wb_cab_i    ( 1'b0 ),
908
        .i2_wb_adr_i    ( 32'h0000_0000 ),
909
        .i2_wb_sel_i    ( 4'b0000 ),
910
        .i2_wb_we_i     ( 1'b0 ),
911
        .i2_wb_dat_i    ( 32'h0000_0000 ),
912
        .i2_wb_dat_o    ( ),
913
        .i2_wb_ack_o    ( ),
914
        .i2_wb_err_o    ( ),
915
 
916
        // WISHBONE Initiator 3
917
        .i3_wb_cyc_i    ( wb_dm_cyc_o ),
918
        .i3_wb_stb_i    ( wb_dm_stb_o ),
919
        .i3_wb_cab_i    ( wb_dm_cab_o ),
920
        .i3_wb_adr_i    ( wb_dm_adr_o ),
921
        .i3_wb_sel_i    ( wb_dm_sel_o ),
922
        .i3_wb_we_i     ( wb_dm_we_o  ),
923
        .i3_wb_dat_i    ( wb_dm_dat_o ),
924
        .i3_wb_dat_o    ( wb_dm_dat_i ),
925
        .i3_wb_ack_o    ( wb_dm_ack_i ),
926
        .i3_wb_err_o    ( wb_dm_err_i ),
927
 
928
        // WISHBONE Initiator 4
929
        .i4_wb_cyc_i    ( wb_rdm_cyc_o ),
930
        .i4_wb_stb_i    ( wb_rdm_stb_o ),
931
        .i4_wb_cab_i    ( wb_rdm_cab_o ),
932
        .i4_wb_adr_i    ( wb_rdm_adr_o ),
933
        .i4_wb_sel_i    ( wb_rdm_sel_o ),
934
        .i4_wb_we_i     ( wb_rdm_we_o  ),
935
        .i4_wb_dat_i    ( wb_rdm_dat_o ),
936
        .i4_wb_dat_o    ( wb_rdm_dat_i ),
937
        .i4_wb_ack_o    ( wb_rdm_ack_i ),
938
        .i4_wb_err_o    ( wb_rdm_err_i ),
939
 
940
        // WISHBONE Initiator 5
941
        .i5_wb_cyc_i    ( wb_rim_cyc_o ),
942
        .i5_wb_stb_i    ( wb_rim_stb_o ),
943
        .i5_wb_cab_i    ( wb_rim_cab_o ),
944
        .i5_wb_adr_i    ( wb_rim_adr_o ),
945
        .i5_wb_sel_i    ( wb_rim_sel_o ),
946
        .i5_wb_we_i     ( wb_rim_we_o  ),
947
        .i5_wb_dat_i    ( wb_rim_dat_o ),
948
        .i5_wb_dat_o    ( wb_rim_dat_i ),
949
        .i5_wb_ack_o    ( wb_rim_ack_i ),
950
        .i5_wb_err_o    ( wb_rim_err_i ),
951
 
952
        // WISHBONE Initiator 6
953
        .i6_wb_cyc_i    ( 1'b0 ),
954
        .i6_wb_stb_i    ( 1'b0 ),
955
        .i6_wb_cab_i    ( 1'b0 ),
956
        .i6_wb_adr_i    ( 32'h0000_0000 ),
957
        .i6_wb_sel_i    ( 4'b0000 ),
958
        .i6_wb_we_i     ( 1'b0 ),
959
        .i6_wb_dat_i    ( 32'h0000_0000 ),
960
        .i6_wb_dat_o    ( ),
961
        .i6_wb_ack_o    ( ),
962
        .i6_wb_err_o    ( ),
963
 
964
        // WISHBONE Initiator 7
965
        .i7_wb_cyc_i    ( 1'b0 ),
966
        .i7_wb_stb_i    ( 1'b0 ),
967
        .i7_wb_cab_i    ( 1'b0 ),
968
        .i7_wb_adr_i    ( 32'h0000_0000 ),
969
        .i7_wb_sel_i    ( 4'b0000 ),
970
        .i7_wb_we_i     ( 1'b0 ),
971
        .i7_wb_dat_i    ( 32'h0000_0000 ),
972
        .i7_wb_dat_o    ( ),
973
        .i7_wb_ack_o    ( ),
974
        .i7_wb_err_o    ( ),
975
 
976
        // WISHBONE Target 0
977
        .t0_wb_cyc_o    ( wb_ss_cyc_i ),
978
        .t0_wb_stb_o    ( wb_ss_stb_i ),
979
        .t0_wb_cab_o    ( wb_ss_cab_i ),
980
        .t0_wb_adr_o    ( wb_ss_adr_i ),
981
        .t0_wb_sel_o    ( wb_ss_sel_i ),
982
        .t0_wb_we_o     ( wb_ss_we_i  ),
983
        .t0_wb_dat_o    ( wb_ss_dat_i ),
984
        .t0_wb_dat_i    ( wb_ss_dat_o ),
985
        .t0_wb_ack_i    ( wb_ss_ack_o ),
986
        .t0_wb_err_i    ( wb_ss_err_o ),
987
 
988
        // WISHBONE Target 1
989
        .t1_wb_cyc_o    ( wb_fs_cyc_i ),
990
        .t1_wb_stb_o    ( wb_fs_stb_i ),
991
        .t1_wb_cab_o    ( wb_fs_cab_i ),
992
        .t1_wb_adr_o    ( wb_fs_adr_i ),
993
        .t1_wb_sel_o    ( wb_fs_sel_i ),
994
        .t1_wb_we_o     ( wb_fs_we_i  ),
995
        .t1_wb_dat_o    ( wb_fs_dat_i ),
996
        .t1_wb_dat_i    ( wb_fs_dat_o ),
997
        .t1_wb_ack_i    ( wb_fs_ack_o ),
998
        .t1_wb_err_i    ( wb_fs_err_o ),
999
 
1000
        // WISHBONE Target 2
1001
        .t2_wb_cyc_o    ( wb_sp_cyc_i ),
1002
        .t2_wb_stb_o    ( wb_sp_stb_i ),
1003
        .t2_wb_cab_o    ( wb_sp_cab_i ),
1004
        .t2_wb_adr_o    ( wb_sp_adr_i ),
1005
        .t2_wb_sel_o    ( wb_sp_sel_i ),
1006
        .t2_wb_we_o     ( wb_sp_we_i  ),
1007
        .t2_wb_dat_o    ( wb_sp_dat_i ),
1008
        .t2_wb_dat_i    ( wb_sp_dat_o ),
1009
        .t2_wb_ack_i    ( wb_sp_ack_o ),
1010
        .t2_wb_err_i    ( wb_sp_err_o ),
1011
 
1012
        // WISHBONE Target 3
1013
        .t3_wb_cyc_o    ( wb_es_cyc_i ),
1014
        .t3_wb_stb_o    ( wb_es_stb_i ),
1015
        .t3_wb_cab_o    ( wb_es_cab_i ),
1016
        .t3_wb_adr_o    ( wb_es_adr_i ),
1017
        .t3_wb_sel_o    ( wb_es_sel_i ),
1018
        .t3_wb_we_o     ( wb_es_we_i  ),
1019
        .t3_wb_dat_o    ( wb_es_dat_i ),
1020
        .t3_wb_dat_i    ( wb_es_dat_o ),
1021
        .t3_wb_ack_i    ( wb_es_ack_o ),
1022
        .t3_wb_err_i    ( wb_es_err_o ),
1023
 
1024
        // WISHBONE Target 4
1025
        .t4_wb_cyc_o    ( ),
1026
        .t4_wb_stb_o    ( ),
1027
        .t4_wb_cab_o    ( ),
1028
        .t4_wb_adr_o    ( ),
1029
        .t4_wb_sel_o    ( ),
1030
        .t4_wb_we_o     ( ),
1031
        .t4_wb_dat_o    ( ),
1032
        .t4_wb_dat_i    ( 32'h0000_0000 ),
1033
        .t4_wb_ack_i    ( 1'b0 ),
1034
        .t4_wb_err_i    ( 1'b1 ),
1035
 
1036
        // WISHBONE Target 5
1037
        .t5_wb_cyc_o    ( wb_us_cyc_i ),
1038
        .t5_wb_stb_o    ( wb_us_stb_i ),
1039
        .t5_wb_cab_o    ( wb_us_cab_i ),
1040
        .t5_wb_adr_o    ( wb_us_adr_i ),
1041
        .t5_wb_sel_o    ( wb_us_sel_i ),
1042
        .t5_wb_we_o     ( wb_us_we_i  ),
1043
        .t5_wb_dat_o    ( wb_us_dat_i ),
1044
        .t5_wb_dat_i    ( wb_us_dat_o ),
1045
        .t5_wb_ack_i    ( wb_us_ack_o ),
1046
        .t5_wb_err_i    ( wb_us_err_o ),
1047
 
1048
        // WISHBONE Target 6
1049
        .t6_wb_cyc_o    ( ),
1050
        .t6_wb_stb_o    ( ),
1051
        .t6_wb_cab_o    ( ),
1052
        .t6_wb_adr_o    ( ),
1053
        .t6_wb_sel_o    ( ),
1054
        .t6_wb_we_o     ( ),
1055
        .t6_wb_dat_o    ( ),
1056
        .t6_wb_dat_i    ( 32'h0000_0000 ),
1057
        .t6_wb_ack_i    ( 1'b0 ),
1058
        .t6_wb_err_i    ( 1'b1 ),
1059
 
1060
        // WISHBONE Target 7
1061
        .t7_wb_cyc_o    ( ),
1062
        .t7_wb_stb_o    ( ),
1063
        .t7_wb_cab_o    ( ),
1064
        .t7_wb_adr_o    ( ),
1065
        .t7_wb_sel_o    ( ),
1066
        .t7_wb_we_o     ( ),
1067
        .t7_wb_dat_o    ( ),
1068
        .t7_wb_dat_i    ( 32'h0000_0000 ),
1069
        .t7_wb_ack_i    ( 1'b0 ),
1070
        .t7_wb_err_i    ( 1'b1 ),
1071
 
1072
        // WISHBONE Target 8
1073
        .t8_wb_cyc_o    ( ),
1074
        .t8_wb_stb_o    ( ),
1075
        .t8_wb_cab_o    ( ),
1076
        .t8_wb_adr_o    ( ),
1077
        .t8_wb_sel_o    ( ),
1078
        .t8_wb_we_o     ( ),
1079
        .t8_wb_dat_o    ( ),
1080
        .t8_wb_dat_i    ( 32'h0000_0000 ),
1081
        .t8_wb_ack_i    ( 1'b0 ),
1082
        .t8_wb_err_i    ( 1'b1 )
1083
);
1084
 
1085
//initial begin
1086
//  $dumpvars(0);
1087
//  $dumpfile("dump.vcd");
1088
//end
1089
 
1090
endmodule

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