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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Blame information for rev 31

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1 2 rfajardo
`include "minsoc_defines.v"
2
`include "or1200_defines.v"
3
 
4
module minsoc_top (
5
   clk,reset
6
 
7
   //JTAG ports
8
`ifdef GENERIC_TAP
9
   , jtag_tdi,jtag_tms,jtag_tck,
10
   jtag_tdo,jtag_vref,jtag_gnd
11
`endif
12
 
13
   //SPI ports
14
`ifdef START_UP
15
   , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss
16
`endif
17
 
18
   //UART ports
19
`ifdef UART
20
   , uart_stx,uart_srx
21
`endif
22
 
23
        // Ethernet ports
24
`ifdef ETHERNET
25
        , eth_col, eth_crs, eth_trste, eth_tx_clk,
26
        eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk,
27
        eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint,
28
        eth_mdc, eth_mdio
29
`endif
30
);
31
 
32
//
33
// I/O Ports
34
//
35
 
36
   input         clk;
37
   input         reset;
38
 
39
//
40
// SPI controller external i/f wires
41
//
42
`ifdef START_UP
43
output spi_flash_mosi;
44
input spi_flash_miso;
45
output spi_flash_sclk;
46
output [1:0] spi_flash_ss;
47
`endif
48
 
49
//
50
// UART
51
//
52
`ifdef UART
53
   output        uart_stx;
54
   input         uart_srx;
55
`endif
56
 
57
//
58
// Ethernet
59
//
60
`ifdef ETHERNET
61
output                  eth_tx_er;
62
input                   eth_tx_clk;
63
output                  eth_tx_en;
64
output  [3:0]            eth_txd;
65
input                   eth_rx_er;
66
input                   eth_rx_clk;
67
input                   eth_rx_dv;
68
input   [3:0]            eth_rxd;
69
input                   eth_col;
70
input                   eth_crs;
71
output                  eth_trste;
72
input                   eth_fds_mdint;
73
inout                   eth_mdio;
74
output                  eth_mdc;
75
`endif
76
 
77
//
78
// JTAG
79
//
80
`ifdef GENERIC_TAP
81
   input         jtag_tdi;
82
   input         jtag_tms;
83
   input         jtag_tck;
84
   output        jtag_tdo;
85
   output        jtag_vref;
86
   output        jtag_gnd;
87
 
88
 
89
assign jtag_vref = 1'b1;
90
assign jtag_gnd = 1'b0;
91
`endif
92
 
93
wire rstn;
94
 
95 7 rfajardo
`ifdef POSITIVE_RESET
96 2 rfajardo
assign rstn = ~reset;
97 7 rfajardo
`elsif NEGATIVE_RESET
98
assign rstn = reset;
99
`endif
100 2 rfajardo
 
101
//
102
// Internal wires
103
//
104
 
105
//
106
// Debug core master i/f wires
107
//
108
wire    [31:0]           wb_dm_adr_o;
109
wire    [31:0]           wb_dm_dat_i;
110
wire    [31:0]           wb_dm_dat_o;
111
wire    [3:0]            wb_dm_sel_o;
112
wire                    wb_dm_we_o;
113
wire                    wb_dm_stb_o;
114
wire                    wb_dm_cyc_o;
115
wire                    wb_dm_ack_i;
116
wire                    wb_dm_err_i;
117
 
118
//
119
// Debug <-> RISC wires
120
//
121
wire    [3:0]            dbg_lss;
122
wire    [1:0]            dbg_is;
123
wire    [10:0]           dbg_wp;
124
wire                    dbg_bp;
125
wire    [31:0]           dbg_dat_dbg;
126
wire    [31:0]           dbg_dat_risc;
127
wire    [31:0]           dbg_adr;
128
wire                    dbg_ewt;
129
wire                    dbg_stall;
130 20 rfajardo
wire            dbg_we;
131
wire            dbg_stb;
132
wire            dbg_ack;
133 2 rfajardo
 
134
//
135
// RISC instruction master i/f wires
136
//
137
wire    [31:0]           wb_rim_adr_o;
138
wire                    wb_rim_cyc_o;
139
wire    [31:0]           wb_rim_dat_i;
140
wire    [31:0]           wb_rim_dat_o;
141
wire    [3:0]            wb_rim_sel_o;
142
wire                    wb_rim_ack_i;
143
wire                    wb_rim_err_i;
144
wire                    wb_rim_rty_i = 1'b0;
145
wire                    wb_rim_we_o;
146
wire                    wb_rim_stb_o;
147
wire    [31:0]           wb_rif_dat_i;
148
wire                    wb_rif_ack_i;
149
 
150
//
151
// RISC data master i/f wires
152
//
153
wire    [31:0]           wb_rdm_adr_o;
154
wire                    wb_rdm_cyc_o;
155
wire    [31:0]           wb_rdm_dat_i;
156
wire    [31:0]           wb_rdm_dat_o;
157
wire    [3:0]            wb_rdm_sel_o;
158
wire                    wb_rdm_ack_i;
159
wire                    wb_rdm_err_i;
160
wire                    wb_rdm_rty_i = 1'b0;
161
wire                    wb_rdm_we_o;
162
wire                    wb_rdm_stb_o;
163
 
164
//
165
// RISC misc
166
//
167 31 rfajardo
wire    [`OR1200_PIC_INTS-1:0]           pic_ints;
168 2 rfajardo
 
169
//
170
// Flash controller slave i/f wires
171
//
172
wire    [31:0]           wb_fs_dat_i;
173
wire    [31:0]           wb_fs_dat_o;
174
wire    [31:0]           wb_fs_adr_i;
175
wire    [3:0]            wb_fs_sel_i;
176
wire                    wb_fs_we_i;
177
wire                    wb_fs_cyc_i;
178
wire                    wb_fs_stb_i;
179
wire                    wb_fs_ack_o;
180
wire                    wb_fs_err_o;
181
 
182
//
183
// SPI controller slave i/f wires
184
//
185
wire    [31:0]           wb_sp_dat_i;
186
wire    [31:0]           wb_sp_dat_o;
187
wire    [31:0]           wb_sp_adr_i;
188
wire    [3:0]            wb_sp_sel_i;
189
wire                    wb_sp_we_i;
190
wire                    wb_sp_cyc_i;
191
wire                    wb_sp_stb_i;
192
wire                    wb_sp_ack_o;
193
wire                    wb_sp_err_o;
194
 
195
//
196
// SPI controller external i/f wires
197
//
198
wire spi_flash_mosi;
199
wire spi_flash_miso;
200
wire spi_flash_sclk;
201
wire [1:0] spi_flash_ss;
202
 
203
//
204
// SRAM controller slave i/f wires
205
//
206
wire    [31:0]           wb_ss_dat_i;
207
wire    [31:0]           wb_ss_dat_o;
208
wire    [31:0]           wb_ss_adr_i;
209
wire    [3:0]            wb_ss_sel_i;
210
wire                    wb_ss_we_i;
211
wire                    wb_ss_cyc_i;
212
wire                    wb_ss_stb_i;
213
wire                    wb_ss_ack_o;
214
wire                    wb_ss_err_o;
215
 
216
//
217
// Ethernet core master i/f wires
218
//
219
wire    [31:0]           wb_em_adr_o;
220
wire    [31:0]           wb_em_dat_i;
221
wire    [31:0]           wb_em_dat_o;
222
wire    [3:0]            wb_em_sel_o;
223
wire                    wb_em_we_o;
224
wire                    wb_em_stb_o;
225
wire                    wb_em_cyc_o;
226
wire                    wb_em_ack_i;
227
wire                    wb_em_err_i;
228
 
229
//
230
// Ethernet core slave i/f wires
231
//
232
wire    [31:0]           wb_es_dat_i;
233
wire    [31:0]           wb_es_dat_o;
234
wire    [31:0]           wb_es_adr_i;
235
wire    [3:0]            wb_es_sel_i;
236
wire                    wb_es_we_i;
237
wire                    wb_es_cyc_i;
238
wire                    wb_es_stb_i;
239
wire                    wb_es_ack_o;
240
wire                    wb_es_err_o;
241
 
242
//
243
// Ethernet external i/f wires
244
//
245
wire                    eth_mdo;
246
wire                    eth_mdoe;
247
 
248
//
249
// UART16550 core slave i/f wires
250
//
251
wire    [31:0]           wb_us_dat_i;
252
wire    [31:0]           wb_us_dat_o;
253
wire    [31:0]           wb_us_adr_i;
254
wire    [3:0]            wb_us_sel_i;
255
wire                    wb_us_we_i;
256
wire                    wb_us_cyc_i;
257
wire                    wb_us_stb_i;
258
wire                    wb_us_ack_o;
259
wire                    wb_us_err_o;
260
 
261
//
262
// UART external i/f wires
263
//
264
wire                    uart_stx;
265
wire                    uart_srx;
266
 
267
//
268
// Reset debounce
269
//
270
reg                     rst_r;
271
reg                     wb_rst;
272
 
273
//
274
// Global clock
275
//
276
wire                    wb_clk;
277
 
278
//
279
// Reset debounce
280
//
281
always @(posedge wb_clk or negedge rstn)
282
        if (~rstn)
283
                rst_r <= 1'b1;
284
        else
285
                rst_r <= #1 1'b0;
286
 
287
//
288
// Reset debounce
289
//
290
always @(posedge wb_clk)
291
        wb_rst <= #1 rst_r;
292
 
293
//
294 7 rfajardo
// Clock Divider
295 2 rfajardo
//
296
minsoc_clock_manager #
297
(
298
   .divisor(`CLOCK_DIVISOR)
299
)
300
clk_adjust (
301
        .clk_i(clk),
302
        .clk_o(wb_clk)
303
);
304
 
305
//
306
// Unused WISHBONE signals
307
//
308
assign wb_us_err_o = 1'b0;
309
assign wb_fs_err_o = 1'b0;
310
assign wb_sp_err_o = 1'b0;
311
 
312
//
313
// Unused interrupts
314
//
315
assign pic_ints[`APP_INT_RES1] = 'b0;
316
assign pic_ints[`APP_INT_RES2] = 'b0;
317
assign pic_ints[`APP_INT_RES3] = 'b0;
318
assign pic_ints[`APP_INT_PS2] = 'b0;
319
 
320
//
321
// Ethernet tri-state
322
//
323
`ifdef ETHERNET
324
assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz;
325
assign eth_trste = `ETH_RESET;
326
`endif
327
 
328
 
329
//
330
// RISC Instruction address for Flash
331
//
332
// Until first access to real Flash area,
333
// CPU instruction is fixed to jump to the Flash area.
334
// After Flash area is accessed, CPU instructions 
335
// come from the tc_top (wishbone "switch").
336
//
337
`ifdef START_UP
338
reg jump_flash;
339
reg [3:0] rif_counter;
340
reg [31:0] rif_dat_int;
341
reg rif_ack_int;
342
 
343
always @(posedge wb_clk or negedge rstn)
344
begin
345
        if (!rstn) begin
346
                jump_flash <= #1 1'b1;
347
                rif_counter <= 4'h0;
348
                rif_ack_int <= 1'b0;
349
        end
350
        else begin
351
                rif_ack_int <= 1'b0;
352
 
353
                if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
354
                        jump_flash <= #1 1'b0;
355
 
356
                if ( jump_flash == 1'b1 ) begin
357
                        if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) begin
358
                                rif_counter <= rif_counter + 1'b1;
359
                                rif_ack_int <= 1'b1;
360
                        end
361
                end
362
        end
363
end
364
 
365
always @ (rif_counter)
366
begin
367
        case ( rif_counter )
368
                4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 };
369
                4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 };
370
                4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 };
371
                4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 };
372
                default: rif_dat_int = 32'h0000_0000;
373
        endcase
374
end
375
 
376
assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i;
377
 
378
assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i;
379
 
380
`else
381
assign wb_rif_dat_i = wb_rim_dat_i;
382
assign wb_rif_ack_i = wb_rim_ack_i;
383
`endif
384
 
385
 
386
//
387
// TAP<->dbg_interface
388
//      
389
wire jtag_tck;
390
wire debug_tdi;
391
wire debug_tdo;
392
wire capture_dr;
393
wire shift_dr;
394
wire pause_dr;
395
wire update_dr;
396
 
397
wire debug_select;
398
wire test_logic_reset;
399
 
400
//
401
// Instantiation of the development i/f
402
//
403
adbg_top dbg_top  (
404
 
405
        // JTAG pins
406
      .tck_i    ( jtag_tck ),
407
      .tdi_i    ( debug_tdi ),
408
      .tdo_o    ( debug_tdo ),
409
      .rst_i    ( test_logic_reset ),           //cable without rst
410
 
411
        // Boundary Scan signals
412
      .capture_dr_i ( capture_dr ),
413
      .shift_dr_i  ( shift_dr ),
414
      .pause_dr_i  ( pause_dr ),
415
      .update_dr_i ( update_dr ),
416
 
417
      .debug_select_i( debug_select ),
418
        // WISHBONE common
419
      .wb_clk_i   ( wb_clk ),
420
 
421
      // WISHBONE master interface
422
      .wb_adr_o  ( wb_dm_adr_o ),
423
      .wb_dat_i  ( wb_dm_dat_i ),
424
      .wb_dat_o  ( wb_dm_dat_o ),
425
      .wb_sel_o  ( wb_dm_sel_o ),
426
      .wb_we_o   ( wb_dm_we_o  ),
427
      .wb_stb_o  ( wb_dm_stb_o ),
428
      .wb_cyc_o  ( wb_dm_cyc_o ),
429
      .wb_ack_i  ( wb_dm_ack_i ),
430
      .wb_err_i  ( wb_dm_err_i ),
431
      .wb_cti_o  ( ),
432
      .wb_bte_o  ( ),
433
 
434
      // RISC signals
435
      .cpu0_clk_i  ( wb_clk ),
436
      .cpu0_addr_o ( dbg_adr ),
437
      .cpu0_data_i ( dbg_dat_risc ),
438
      .cpu0_data_o ( dbg_dat_dbg ),
439
      .cpu0_bp_i   ( dbg_bp ),
440
      .cpu0_stall_o( dbg_stall ),
441 20 rfajardo
      .cpu0_stb_o  ( dbg_stb ),
442
      .cpu0_we_o   ( dbg_we ),
443 2 rfajardo
      .cpu0_ack_i  ( dbg_ack ),
444
      .cpu0_rst_o  ( )
445
 
446
);
447
 
448
//
449
// JTAG TAP controller instantiation
450
//
451
`ifdef GENERIC_TAP
452
tap_top tap_top(
453
         // JTAG pads
454
         .tms_pad_i(jtag_tms),
455
         .tck_pad_i(jtag_tck),
456
         .trstn_pad_i(rstn),
457
         .tdi_pad_i(jtag_tdi),
458
         .tdo_pad_o(jtag_tdo),
459
         .tdo_padoe_o( ),
460
 
461
         // TAP states
462
         .test_logic_reset_o( test_logic_reset ),
463
         .run_test_idle_o(),
464
         .shift_dr_o(shift_dr),
465
         .pause_dr_o(pause_dr),
466
         .update_dr_o(update_dr),
467
         .capture_dr_o(capture_dr),
468
 
469
         // Select signals for boundary scan or mbist
470
         .extest_select_o(),
471
         .sample_preload_select_o(),
472
         .mbist_select_o(),
473
         .debug_select_o(debug_select),
474
 
475
         // TDO signal that is connected to TDI of sub-modules.
476
         .tdi_o(debug_tdi),
477
 
478
         // TDI signals from sub-modules
479
         .debug_tdo_i(debug_tdo),    // from debug module
480
         .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
481
         .mbist_tdo_i(1'b0)     // from Mbist Chain
482
);
483
`elsif FPGA_TAP
484
`ifdef ALTERA_FPGA
485
altera_virtual_jtag tap_top(
486
        .tck_o(jtag_tck),
487 26 rfajardo
        .debug_tdo_i(debug_tdo),
488 2 rfajardo
        .tdi_o(debug_tdi),
489
        .test_logic_reset_o(test_logic_reset),
490
        .run_test_idle_o(),
491
        .shift_dr_o(shift_dr),
492
        .capture_dr_o(capture_dr),
493
        .pause_dr_o(pause_dr),
494
        .update_dr_o(update_dr),
495
        .debug_select_o(debug_select)
496
);
497
`elsif XILINX_FPGA
498
minsoc_xilinx_internal_jtag tap_top(
499
        .tck_o( jtag_tck ),
500
        .debug_tdo_i( debug_tdo ),
501
        .tdi_o( debug_tdi ),
502
 
503
        .test_logic_reset_o( test_logic_reset ),
504
        .run_test_idle_o( ),
505
 
506
        .shift_dr_o( shift_dr ),
507
        .capture_dr_o( capture_dr ),
508
        .pause_dr_o( pause_dr ),
509
        .update_dr_o( update_dr ),
510
        .debug_select_o( debug_select )
511
);
512
`endif // !FPGA_TAP
513
 
514
`endif // !GENERIC_TAP
515
 
516
//
517
// Instantiation of the OR1200 RISC
518
//
519
or1200_top or1200_top (
520
 
521
        // Common
522
        .rst_i          ( wb_rst ),
523
        .clk_i          ( wb_clk ),
524
`ifdef OR1200_CLMODE_1TO2
525
        .clmode_i       ( 2'b01 ),
526
`else
527
`ifdef OR1200_CLMODE_1TO4
528
        .clmode_i       ( 2'b11 ),
529
`else
530
        .clmode_i       ( 2'b00 ),
531
`endif
532
`endif
533
 
534
        // WISHBONE Instruction Master
535
        .iwb_clk_i      ( wb_clk ),
536
        .iwb_rst_i      ( wb_rst ),
537
        .iwb_cyc_o      ( wb_rim_cyc_o ),
538
        .iwb_adr_o      ( wb_rim_adr_o ),
539
        .iwb_dat_i      ( wb_rif_dat_i ),
540
        .iwb_dat_o      ( wb_rim_dat_o ),
541
        .iwb_sel_o      ( wb_rim_sel_o ),
542
        .iwb_ack_i      ( wb_rif_ack_i ),
543
        .iwb_err_i      ( wb_rim_err_i ),
544
        .iwb_rty_i      ( wb_rim_rty_i ),
545
        .iwb_we_o       ( wb_rim_we_o  ),
546
        .iwb_stb_o      ( wb_rim_stb_o ),
547
 
548
        // WISHBONE Data Master
549
        .dwb_clk_i      ( wb_clk ),
550
        .dwb_rst_i      ( wb_rst ),
551
        .dwb_cyc_o      ( wb_rdm_cyc_o ),
552
        .dwb_adr_o      ( wb_rdm_adr_o ),
553
        .dwb_dat_i      ( wb_rdm_dat_i ),
554
        .dwb_dat_o      ( wb_rdm_dat_o ),
555
        .dwb_sel_o      ( wb_rdm_sel_o ),
556
        .dwb_ack_i      ( wb_rdm_ack_i ),
557
        .dwb_err_i      ( wb_rdm_err_i ),
558
        .dwb_rty_i      ( wb_rdm_rty_i ),
559
        .dwb_we_o       ( wb_rdm_we_o  ),
560
        .dwb_stb_o      ( wb_rdm_stb_o ),
561
 
562
        // Debug
563
        .dbg_stall_i    ( dbg_stall ),
564
        .dbg_dat_i      ( dbg_dat_dbg ),
565
        .dbg_adr_i      ( dbg_adr ),
566
        .dbg_ewt_i      ( 1'b0 ),
567
        .dbg_lss_o      ( dbg_lss ),
568
        .dbg_is_o       ( dbg_is ),
569
        .dbg_wp_o       ( dbg_wp ),
570
        .dbg_bp_o       ( dbg_bp ),
571
        .dbg_dat_o      ( dbg_dat_risc ),
572
        .dbg_ack_o      ( dbg_ack ),
573 20 rfajardo
        .dbg_stb_i      ( dbg_stb ),
574
        .dbg_we_i       ( dbg_we ),
575 2 rfajardo
 
576
        // Power Management
577
        .pm_clksd_o     ( ),
578
        .pm_cpustall_i  ( 1'b0 ),
579
        .pm_dc_gate_o   ( ),
580
        .pm_ic_gate_o   ( ),
581
        .pm_dmmu_gate_o ( ),
582
        .pm_immu_gate_o ( ),
583
        .pm_tt_gate_o   ( ),
584
        .pm_cpu_gate_o  ( ),
585
        .pm_wakeup_o    ( ),
586
        .pm_lvolt_o     ( ),
587
 
588
        // Interrupts
589
        .pic_ints_i     ( pic_ints )
590
);
591
 
592
//
593
// Startup OR1k
594
//
595
`ifdef START_UP
596
OR1K_startup OR1K_startup0
597
(
598
    .wb_adr_i(wb_fs_adr_i[6:2]),
599
    .wb_stb_i(wb_fs_stb_i),
600
    .wb_cyc_i(wb_fs_cyc_i),
601
    .wb_dat_o(wb_fs_dat_o),
602
    .wb_ack_o(wb_fs_ack_o),
603
    .wb_clk(wb_clk),
604
    .wb_rst(wb_rst)
605
);
606
 
607
spi_flash_top #
608
(
609
   .divider(0),
610
   .divider_len(2)
611
)
612
spi_flash_top0
613
(
614
   .wb_clk_i(wb_clk),
615
   .wb_rst_i(wb_rst),
616
   .wb_adr_i(wb_sp_adr_i[4:2]),
617
   .wb_dat_i(wb_sp_dat_i),
618
   .wb_dat_o(wb_sp_dat_o),
619
   .wb_sel_i(wb_sp_sel_i),
620
   .wb_we_i(wb_sp_we_i),
621
   .wb_stb_i(wb_sp_stb_i),
622
   .wb_cyc_i(wb_sp_cyc_i),
623
   .wb_ack_o(wb_sp_ack_o),
624
 
625
   .mosi_pad_o(spi_flash_mosi),
626
   .miso_pad_i(spi_flash_miso),
627
   .sclk_pad_o(spi_flash_sclk),
628
   .ss_pad_o(spi_flash_ss)
629
);
630
`else
631
assign wb_fs_dat_o = 32'h0000_0000;
632
assign wb_fs_ack_o = 1'b0;
633
assign wb_sp_dat_o = 32'h0000_0000;
634
assign wb_sp_ack_o = 1'b0;
635
`endif
636
 
637
//
638
// Instantiation of the SRAM controller
639
//
640
minsoc_onchip_ram_top #
641
(
642
    .adr_width(`MEMORY_ADR_WIDTH)     //16 blocks of 2048 bytes memory 32768
643
)
644
onchip_ram_top (
645
 
646
        // WISHBONE common
647
        .wb_clk_i       ( wb_clk ),
648
        .wb_rst_i       ( wb_rst ),
649
 
650
        // WISHBONE slave
651
        .wb_dat_i       ( wb_ss_dat_i ),
652
        .wb_dat_o       ( wb_ss_dat_o ),
653
        .wb_adr_i       ( wb_ss_adr_i ),
654
        .wb_sel_i       ( wb_ss_sel_i ),
655
        .wb_we_i        ( wb_ss_we_i  ),
656
        .wb_cyc_i       ( wb_ss_cyc_i ),
657
        .wb_stb_i       ( wb_ss_stb_i ),
658
        .wb_ack_o       ( wb_ss_ack_o ),
659
        .wb_err_o       ( wb_ss_err_o )
660
);
661
 
662
//
663
// Instantiation of the UART16550
664
//
665
`ifdef UART
666
uart_top uart_top (
667
 
668
        // WISHBONE common
669
        .wb_clk_i       ( wb_clk ),
670
        .wb_rst_i       ( wb_rst ),
671
 
672
        // WISHBONE slave
673
        .wb_adr_i       ( wb_us_adr_i[4:0] ),
674
        .wb_dat_i       ( wb_us_dat_i ),
675
        .wb_dat_o       ( wb_us_dat_o ),
676
        .wb_we_i        ( wb_us_we_i  ),
677
        .wb_stb_i       ( wb_us_stb_i ),
678
        .wb_cyc_i       ( wb_us_cyc_i ),
679
        .wb_ack_o       ( wb_us_ack_o ),
680
        .wb_sel_i       ( wb_us_sel_i ),
681
 
682
        // Interrupt request
683
        .int_o          ( pic_ints[`APP_INT_UART] ),
684
 
685
        // UART signals
686
        // serial input/output
687
        .stx_pad_o      ( uart_stx ),
688
        .srx_pad_i      ( uart_srx ),
689
 
690
        // modem signals
691
        .rts_pad_o      ( ),
692
        .cts_pad_i      ( 1'b0 ),
693
        .dtr_pad_o      ( ),
694
        .dsr_pad_i      ( 1'b0 ),
695
        .ri_pad_i       ( 1'b0 ),
696
        .dcd_pad_i      ( 1'b0 )
697
);
698
`else
699
assign wb_us_dat_o = 32'h0000_0000;
700
assign wb_us_ack_o = 1'b0;
701 17 rfajardo
 
702 16 rfajardo
assign pic_ints[`APP_INT_UART] = 1'b0;
703 2 rfajardo
`endif
704
 
705
//
706
// Instantiation of the Ethernet 10/100 MAC
707
//
708
`ifdef ETHERNET
709
eth_top eth_top (
710
 
711
        // WISHBONE common
712
        .wb_clk_i       ( wb_clk ),
713
        .wb_rst_i       ( wb_rst ),
714
 
715
        // WISHBONE slave
716
        .wb_dat_i       ( wb_es_dat_i ),
717
        .wb_dat_o       ( wb_es_dat_o ),
718
        .wb_adr_i       ( wb_es_adr_i[11:2] ),
719
        .wb_sel_i       ( wb_es_sel_i ),
720
        .wb_we_i        ( wb_es_we_i  ),
721
        .wb_cyc_i       ( wb_es_cyc_i ),
722
        .wb_stb_i       ( wb_es_stb_i ),
723
        .wb_ack_o       ( wb_es_ack_o ),
724
        .wb_err_o       ( wb_es_err_o ),
725
 
726
        // WISHBONE master
727
        .m_wb_adr_o     ( wb_em_adr_o ),
728
        .m_wb_sel_o     ( wb_em_sel_o ),
729
        .m_wb_we_o      ( wb_em_we_o  ),
730
        .m_wb_dat_o     ( wb_em_dat_o ),
731
        .m_wb_dat_i     ( wb_em_dat_i ),
732
        .m_wb_cyc_o     ( wb_em_cyc_o ),
733
        .m_wb_stb_o     ( wb_em_stb_o ),
734
        .m_wb_ack_i     ( wb_em_ack_i ),
735
        .m_wb_err_i     ( wb_em_err_i ),
736
 
737
        // TX
738
        .mtx_clk_pad_i  ( eth_tx_clk ),
739
        .mtxd_pad_o     ( eth_txd ),
740
        .mtxen_pad_o    ( eth_tx_en ),
741
        .mtxerr_pad_o   ( eth_tx_er ),
742
 
743
        // RX
744
        .mrx_clk_pad_i  ( eth_rx_clk ),
745
        .mrxd_pad_i     ( eth_rxd ),
746
        .mrxdv_pad_i    ( eth_rx_dv ),
747
        .mrxerr_pad_i   ( eth_rx_er ),
748
        .mcoll_pad_i    ( eth_col ),
749
        .mcrs_pad_i     ( eth_crs ),
750
 
751
        // MIIM
752
        .mdc_pad_o      ( eth_mdc ),
753
        .md_pad_i       ( eth_mdio ),
754
        .md_pad_o       ( eth_mdo ),
755
        .md_padoe_o     ( eth_mdoe ),
756
 
757
        // Interrupt
758
        .int_o          ( pic_ints[`APP_INT_ETH] )
759
);
760
`else
761
assign wb_es_dat_o = 32'h0000_0000;
762
assign wb_es_ack_o = 1'b0;
763 14 rfajardo
assign wb_es_err_o = 1'b0;
764 2 rfajardo
 
765
assign wb_em_adr_o = 32'h0000_0000;
766
assign wb_em_sel_o = 4'h0;
767
assign wb_em_we_o = 1'b0;
768
assign wb_em_dat_o = 32'h0000_0000;
769
assign wb_em_cyc_o = 1'b0;
770
assign wb_em_stb_o = 1'b0;
771 17 rfajardo
 
772 16 rfajardo
assign pic_ints[`APP_INT_ETH] = 1'b0;
773 2 rfajardo
`endif
774
 
775
//
776
// Instantiation of the Traffic COP
777
//
778
minsoc_tc_top #(`APP_ADDR_DEC_W,
779
         `APP_ADDR_SRAM,
780
         `APP_ADDR_DEC_W,
781
         `APP_ADDR_FLASH,
782
         `APP_ADDR_DECP_W,
783
         `APP_ADDR_PERIP,
784
         `APP_ADDR_DEC_W,
785
         `APP_ADDR_SPI,
786
         `APP_ADDR_ETH,
787
         `APP_ADDR_AUDIO,
788
         `APP_ADDR_UART,
789
         `APP_ADDR_PS2,
790
         `APP_ADDR_RES1,
791
         `APP_ADDR_RES2
792
        ) tc_top (
793
 
794
        // WISHBONE common
795
        .wb_clk_i       ( wb_clk ),
796
        .wb_rst_i       ( wb_rst ),
797
 
798
        // WISHBONE Initiator 0
799
        .i0_wb_cyc_i    ( 1'b0 ),
800
        .i0_wb_stb_i    ( 1'b0 ),
801
        .i0_wb_adr_i    ( 32'h0000_0000 ),
802
        .i0_wb_sel_i    ( 4'b0000 ),
803
        .i0_wb_we_i     ( 1'b0 ),
804
        .i0_wb_dat_i    ( 32'h0000_0000 ),
805
        .i0_wb_dat_o    ( ),
806
        .i0_wb_ack_o    ( ),
807
        .i0_wb_err_o    ( ),
808
 
809
        // WISHBONE Initiator 1
810
        .i1_wb_cyc_i    ( wb_em_cyc_o ),
811
        .i1_wb_stb_i    ( wb_em_stb_o ),
812
        .i1_wb_adr_i    ( wb_em_adr_o ),
813
        .i1_wb_sel_i    ( wb_em_sel_o ),
814
        .i1_wb_we_i     ( wb_em_we_o  ),
815
        .i1_wb_dat_i    ( wb_em_dat_o ),
816
        .i1_wb_dat_o    ( wb_em_dat_i ),
817
        .i1_wb_ack_o    ( wb_em_ack_i ),
818
        .i1_wb_err_o    ( wb_em_err_i ),
819
 
820
        // WISHBONE Initiator 2
821
        .i2_wb_cyc_i    ( 1'b0 ),
822
        .i2_wb_stb_i    ( 1'b0 ),
823
        .i2_wb_adr_i    ( 32'h0000_0000 ),
824
        .i2_wb_sel_i    ( 4'b0000 ),
825
        .i2_wb_we_i     ( 1'b0 ),
826
        .i2_wb_dat_i    ( 32'h0000_0000 ),
827
        .i2_wb_dat_o    ( ),
828
        .i2_wb_ack_o    ( ),
829
        .i2_wb_err_o    ( ),
830
 
831
        // WISHBONE Initiator 3
832
        .i3_wb_cyc_i    ( wb_dm_cyc_o ),
833
        .i3_wb_stb_i    ( wb_dm_stb_o ),
834
        .i3_wb_adr_i    ( wb_dm_adr_o ),
835
        .i3_wb_sel_i    ( wb_dm_sel_o ),
836
        .i3_wb_we_i     ( wb_dm_we_o  ),
837
        .i3_wb_dat_i    ( wb_dm_dat_o ),
838
        .i3_wb_dat_o    ( wb_dm_dat_i ),
839
        .i3_wb_ack_o    ( wb_dm_ack_i ),
840
        .i3_wb_err_o    ( wb_dm_err_i ),
841
 
842
        // WISHBONE Initiator 4
843
        .i4_wb_cyc_i    ( wb_rdm_cyc_o ),
844
        .i4_wb_stb_i    ( wb_rdm_stb_o ),
845
        .i4_wb_adr_i    ( wb_rdm_adr_o ),
846
        .i4_wb_sel_i    ( wb_rdm_sel_o ),
847
        .i4_wb_we_i     ( wb_rdm_we_o  ),
848
        .i4_wb_dat_i    ( wb_rdm_dat_o ),
849
        .i4_wb_dat_o    ( wb_rdm_dat_i ),
850
        .i4_wb_ack_o    ( wb_rdm_ack_i ),
851
        .i4_wb_err_o    ( wb_rdm_err_i ),
852
 
853
        // WISHBONE Initiator 5
854
        .i5_wb_cyc_i    ( wb_rim_cyc_o ),
855
        .i5_wb_stb_i    ( wb_rim_stb_o ),
856
        .i5_wb_adr_i    ( wb_rim_adr_o ),
857
        .i5_wb_sel_i    ( wb_rim_sel_o ),
858
        .i5_wb_we_i     ( wb_rim_we_o  ),
859
        .i5_wb_dat_i    ( wb_rim_dat_o ),
860
        .i5_wb_dat_o    ( wb_rim_dat_i ),
861
        .i5_wb_ack_o    ( wb_rim_ack_i ),
862
        .i5_wb_err_o    ( wb_rim_err_i ),
863
 
864
        // WISHBONE Initiator 6
865
        .i6_wb_cyc_i    ( 1'b0 ),
866
        .i6_wb_stb_i    ( 1'b0 ),
867
        .i6_wb_adr_i    ( 32'h0000_0000 ),
868
        .i6_wb_sel_i    ( 4'b0000 ),
869
        .i6_wb_we_i     ( 1'b0 ),
870
        .i6_wb_dat_i    ( 32'h0000_0000 ),
871
        .i6_wb_dat_o    ( ),
872
        .i6_wb_ack_o    ( ),
873
        .i6_wb_err_o    ( ),
874
 
875
        // WISHBONE Initiator 7
876
        .i7_wb_cyc_i    ( 1'b0 ),
877
        .i7_wb_stb_i    ( 1'b0 ),
878
        .i7_wb_adr_i    ( 32'h0000_0000 ),
879
        .i7_wb_sel_i    ( 4'b0000 ),
880
        .i7_wb_we_i     ( 1'b0 ),
881
        .i7_wb_dat_i    ( 32'h0000_0000 ),
882
        .i7_wb_dat_o    ( ),
883
        .i7_wb_ack_o    ( ),
884
        .i7_wb_err_o    ( ),
885
 
886
        // WISHBONE Target 0
887
        .t0_wb_cyc_o    ( wb_ss_cyc_i ),
888
        .t0_wb_stb_o    ( wb_ss_stb_i ),
889
        .t0_wb_adr_o    ( wb_ss_adr_i ),
890
        .t0_wb_sel_o    ( wb_ss_sel_i ),
891
        .t0_wb_we_o     ( wb_ss_we_i  ),
892
        .t0_wb_dat_o    ( wb_ss_dat_i ),
893
        .t0_wb_dat_i    ( wb_ss_dat_o ),
894
        .t0_wb_ack_i    ( wb_ss_ack_o ),
895
        .t0_wb_err_i    ( wb_ss_err_o ),
896
 
897
        // WISHBONE Target 1
898
        .t1_wb_cyc_o    ( wb_fs_cyc_i ),
899
        .t1_wb_stb_o    ( wb_fs_stb_i ),
900
        .t1_wb_adr_o    ( wb_fs_adr_i ),
901
        .t1_wb_sel_o    ( wb_fs_sel_i ),
902
        .t1_wb_we_o     ( wb_fs_we_i  ),
903
        .t1_wb_dat_o    ( wb_fs_dat_i ),
904
        .t1_wb_dat_i    ( wb_fs_dat_o ),
905
        .t1_wb_ack_i    ( wb_fs_ack_o ),
906
        .t1_wb_err_i    ( wb_fs_err_o ),
907
 
908
        // WISHBONE Target 2
909
        .t2_wb_cyc_o    ( wb_sp_cyc_i ),
910
        .t2_wb_stb_o    ( wb_sp_stb_i ),
911
        .t2_wb_adr_o    ( wb_sp_adr_i ),
912
        .t2_wb_sel_o    ( wb_sp_sel_i ),
913
        .t2_wb_we_o     ( wb_sp_we_i  ),
914
        .t2_wb_dat_o    ( wb_sp_dat_i ),
915
        .t2_wb_dat_i    ( wb_sp_dat_o ),
916
        .t2_wb_ack_i    ( wb_sp_ack_o ),
917
        .t2_wb_err_i    ( wb_sp_err_o ),
918
 
919
        // WISHBONE Target 3
920
        .t3_wb_cyc_o    ( wb_es_cyc_i ),
921
        .t3_wb_stb_o    ( wb_es_stb_i ),
922
        .t3_wb_adr_o    ( wb_es_adr_i ),
923
        .t3_wb_sel_o    ( wb_es_sel_i ),
924
        .t3_wb_we_o     ( wb_es_we_i  ),
925
        .t3_wb_dat_o    ( wb_es_dat_i ),
926
        .t3_wb_dat_i    ( wb_es_dat_o ),
927
        .t3_wb_ack_i    ( wb_es_ack_o ),
928
        .t3_wb_err_i    ( wb_es_err_o ),
929
 
930
        // WISHBONE Target 4
931
        .t4_wb_cyc_o    ( ),
932
        .t4_wb_stb_o    ( ),
933
        .t4_wb_adr_o    ( ),
934
        .t4_wb_sel_o    ( ),
935
        .t4_wb_we_o     ( ),
936
        .t4_wb_dat_o    ( ),
937
        .t4_wb_dat_i    ( 32'h0000_0000 ),
938
        .t4_wb_ack_i    ( 1'b0 ),
939
        .t4_wb_err_i    ( 1'b1 ),
940
 
941
        // WISHBONE Target 5
942
        .t5_wb_cyc_o    ( wb_us_cyc_i ),
943
        .t5_wb_stb_o    ( wb_us_stb_i ),
944
        .t5_wb_adr_o    ( wb_us_adr_i ),
945
        .t5_wb_sel_o    ( wb_us_sel_i ),
946
        .t5_wb_we_o     ( wb_us_we_i  ),
947
        .t5_wb_dat_o    ( wb_us_dat_i ),
948
        .t5_wb_dat_i    ( wb_us_dat_o ),
949
        .t5_wb_ack_i    ( wb_us_ack_o ),
950
        .t5_wb_err_i    ( wb_us_err_o ),
951
 
952
        // WISHBONE Target 6
953
        .t6_wb_cyc_o    ( ),
954
        .t6_wb_stb_o    ( ),
955
        .t6_wb_adr_o    ( ),
956
        .t6_wb_sel_o    ( ),
957
        .t6_wb_we_o     ( ),
958
        .t6_wb_dat_o    ( ),
959
        .t6_wb_dat_i    ( 32'h0000_0000 ),
960
        .t6_wb_ack_i    ( 1'b0 ),
961
        .t6_wb_err_i    ( 1'b1 ),
962
 
963
        // WISHBONE Target 7
964
        .t7_wb_cyc_o    ( ),
965
        .t7_wb_stb_o    ( ),
966
        .t7_wb_adr_o    ( ),
967
        .t7_wb_sel_o    ( ),
968
        .t7_wb_we_o     ( ),
969
        .t7_wb_dat_o    ( ),
970
        .t7_wb_dat_i    ( 32'h0000_0000 ),
971
        .t7_wb_ack_i    ( 1'b0 ),
972
        .t7_wb_err_i    ( 1'b1 ),
973
 
974
        // WISHBONE Target 8
975
        .t8_wb_cyc_o    ( ),
976
        .t8_wb_stb_o    ( ),
977
        .t8_wb_adr_o    ( ),
978
        .t8_wb_sel_o    ( ),
979
        .t8_wb_we_o     ( ),
980
        .t8_wb_dat_o    ( ),
981
        .t8_wb_dat_i    ( 32'h0000_0000 ),
982
        .t8_wb_ack_i    ( 1'b0 ),
983
        .t8_wb_err_i    ( 1'b1 )
984
);
985
 
986
//initial begin
987
//  $dumpvars(0);
988
//  $dumpfile("dump.vcd");
989
//end
990
 
991
endmodule

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