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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Blame information for rev 56

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1 2 rfajardo
`include "minsoc_defines.v"
2
`include "or1200_defines.v"
3
 
4
module minsoc_top (
5
   clk,reset
6
 
7
   //JTAG ports
8
`ifdef GENERIC_TAP
9
   , jtag_tdi,jtag_tms,jtag_tck,
10
   jtag_tdo,jtag_vref,jtag_gnd
11
`endif
12
 
13
   //SPI ports
14
`ifdef START_UP
15
   , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss
16
`endif
17
 
18
   //UART ports
19
`ifdef UART
20
   , uart_stx,uart_srx
21
`endif
22
 
23
        // Ethernet ports
24
`ifdef ETHERNET
25
        , eth_col, eth_crs, eth_trste, eth_tx_clk,
26
        eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk,
27
        eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint,
28
        eth_mdc, eth_mdio
29
`endif
30
);
31
 
32
//
33
// I/O Ports
34
//
35
 
36
   input         clk;
37
   input         reset;
38
 
39
//
40
// SPI controller external i/f wires
41
//
42
`ifdef START_UP
43
output spi_flash_mosi;
44
input spi_flash_miso;
45
output spi_flash_sclk;
46
output [1:0] spi_flash_ss;
47
`endif
48
 
49
//
50
// UART
51
//
52
`ifdef UART
53
   output        uart_stx;
54
   input         uart_srx;
55
`endif
56
 
57
//
58
// Ethernet
59
//
60
`ifdef ETHERNET
61
output                  eth_tx_er;
62
input                   eth_tx_clk;
63
output                  eth_tx_en;
64
output  [3:0]            eth_txd;
65
input                   eth_rx_er;
66
input                   eth_rx_clk;
67
input                   eth_rx_dv;
68
input   [3:0]            eth_rxd;
69
input                   eth_col;
70
input                   eth_crs;
71
output                  eth_trste;
72
input                   eth_fds_mdint;
73
inout                   eth_mdio;
74
output                  eth_mdc;
75
`endif
76
 
77
//
78
// JTAG
79
//
80
`ifdef GENERIC_TAP
81
   input         jtag_tdi;
82
   input         jtag_tms;
83
   input         jtag_tck;
84
   output        jtag_tdo;
85
   output        jtag_vref;
86
   output        jtag_gnd;
87
 
88
 
89
assign jtag_vref = 1'b1;
90
assign jtag_gnd = 1'b0;
91
`endif
92
 
93
wire rstn;
94
 
95 7 rfajardo
`ifdef POSITIVE_RESET
96 2 rfajardo
assign rstn = ~reset;
97 7 rfajardo
`elsif NEGATIVE_RESET
98
assign rstn = reset;
99
`endif
100 2 rfajardo
 
101
//
102
// Internal wires
103
//
104
 
105
//
106
// Debug core master i/f wires
107
//
108
wire    [31:0]           wb_dm_adr_o;
109
wire    [31:0]           wb_dm_dat_i;
110
wire    [31:0]           wb_dm_dat_o;
111
wire    [3:0]            wb_dm_sel_o;
112
wire                    wb_dm_we_o;
113
wire                    wb_dm_stb_o;
114
wire                    wb_dm_cyc_o;
115
wire                    wb_dm_ack_i;
116
wire                    wb_dm_err_i;
117
 
118
//
119
// Debug <-> RISC wires
120
//
121
wire    [3:0]            dbg_lss;
122
wire    [1:0]            dbg_is;
123
wire    [10:0]           dbg_wp;
124
wire                    dbg_bp;
125
wire    [31:0]           dbg_dat_dbg;
126
wire    [31:0]           dbg_dat_risc;
127
wire    [31:0]           dbg_adr;
128
wire                    dbg_ewt;
129
wire                    dbg_stall;
130 20 rfajardo
wire            dbg_we;
131
wire            dbg_stb;
132
wire            dbg_ack;
133 2 rfajardo
 
134
//
135
// RISC instruction master i/f wires
136
//
137
wire    [31:0]           wb_rim_adr_o;
138
wire                    wb_rim_cyc_o;
139
wire    [31:0]           wb_rim_dat_i;
140
wire    [31:0]           wb_rim_dat_o;
141
wire    [3:0]            wb_rim_sel_o;
142
wire                    wb_rim_ack_i;
143
wire                    wb_rim_err_i;
144
wire                    wb_rim_rty_i = 1'b0;
145
wire                    wb_rim_we_o;
146
wire                    wb_rim_stb_o;
147
wire    [31:0]           wb_rif_dat_i;
148
wire                    wb_rif_ack_i;
149
 
150
//
151
// RISC data master i/f wires
152
//
153
wire    [31:0]           wb_rdm_adr_o;
154
wire                    wb_rdm_cyc_o;
155
wire    [31:0]           wb_rdm_dat_i;
156
wire    [31:0]           wb_rdm_dat_o;
157
wire    [3:0]            wb_rdm_sel_o;
158
wire                    wb_rdm_ack_i;
159
wire                    wb_rdm_err_i;
160
wire                    wb_rdm_rty_i = 1'b0;
161
wire                    wb_rdm_we_o;
162
wire                    wb_rdm_stb_o;
163
 
164
//
165
// RISC misc
166
//
167 31 rfajardo
wire    [`OR1200_PIC_INTS-1:0]           pic_ints;
168 2 rfajardo
 
169
//
170
// Flash controller slave i/f wires
171
//
172
wire    [31:0]           wb_fs_dat_i;
173
wire    [31:0]           wb_fs_dat_o;
174
wire    [31:0]           wb_fs_adr_i;
175
wire    [3:0]            wb_fs_sel_i;
176
wire                    wb_fs_we_i;
177
wire                    wb_fs_cyc_i;
178
wire                    wb_fs_stb_i;
179
wire                    wb_fs_ack_o;
180
wire                    wb_fs_err_o;
181
 
182
//
183
// SPI controller slave i/f wires
184
//
185
wire    [31:0]           wb_sp_dat_i;
186
wire    [31:0]           wb_sp_dat_o;
187
wire    [31:0]           wb_sp_adr_i;
188
wire    [3:0]            wb_sp_sel_i;
189
wire                    wb_sp_we_i;
190
wire                    wb_sp_cyc_i;
191
wire                    wb_sp_stb_i;
192
wire                    wb_sp_ack_o;
193
wire                    wb_sp_err_o;
194
 
195
//
196
// SPI controller external i/f wires
197
//
198
wire spi_flash_mosi;
199
wire spi_flash_miso;
200
wire spi_flash_sclk;
201
wire [1:0] spi_flash_ss;
202
 
203
//
204
// SRAM controller slave i/f wires
205
//
206
wire    [31:0]           wb_ss_dat_i;
207
wire    [31:0]           wb_ss_dat_o;
208
wire    [31:0]           wb_ss_adr_i;
209
wire    [3:0]            wb_ss_sel_i;
210
wire                    wb_ss_we_i;
211
wire                    wb_ss_cyc_i;
212
wire                    wb_ss_stb_i;
213
wire                    wb_ss_ack_o;
214
wire                    wb_ss_err_o;
215
 
216
//
217
// Ethernet core master i/f wires
218
//
219
wire    [31:0]           wb_em_adr_o;
220
wire    [31:0]           wb_em_dat_i;
221
wire    [31:0]           wb_em_dat_o;
222
wire    [3:0]            wb_em_sel_o;
223
wire                    wb_em_we_o;
224
wire                    wb_em_stb_o;
225
wire                    wb_em_cyc_o;
226
wire                    wb_em_ack_i;
227
wire                    wb_em_err_i;
228
 
229
//
230
// Ethernet core slave i/f wires
231
//
232
wire    [31:0]           wb_es_dat_i;
233
wire    [31:0]           wb_es_dat_o;
234
wire    [31:0]           wb_es_adr_i;
235
wire    [3:0]            wb_es_sel_i;
236
wire                    wb_es_we_i;
237
wire                    wb_es_cyc_i;
238
wire                    wb_es_stb_i;
239
wire                    wb_es_ack_o;
240
wire                    wb_es_err_o;
241
 
242
//
243
// Ethernet external i/f wires
244
//
245
wire                    eth_mdo;
246
wire                    eth_mdoe;
247
 
248
//
249
// UART16550 core slave i/f wires
250
//
251
wire    [31:0]           wb_us_dat_i;
252
wire    [31:0]           wb_us_dat_o;
253
wire    [31:0]           wb_us_adr_i;
254
wire    [3:0]            wb_us_sel_i;
255
wire                    wb_us_we_i;
256
wire                    wb_us_cyc_i;
257
wire                    wb_us_stb_i;
258
wire                    wb_us_ack_o;
259
wire                    wb_us_err_o;
260
 
261
//
262
// UART external i/f wires
263
//
264
wire                    uart_stx;
265
wire                    uart_srx;
266
 
267
//
268
// Reset debounce
269
//
270
reg                     rst_r;
271
reg                     wb_rst;
272
 
273
//
274
// Global clock
275
//
276
wire                    wb_clk;
277
 
278
//
279
// Reset debounce
280
//
281
always @(posedge wb_clk or negedge rstn)
282
        if (~rstn)
283
                rst_r <= 1'b1;
284
        else
285
                rst_r <= #1 1'b0;
286
 
287
//
288
// Reset debounce
289
//
290
always @(posedge wb_clk)
291
        wb_rst <= #1 rst_r;
292
 
293
//
294 7 rfajardo
// Clock Divider
295 2 rfajardo
//
296
minsoc_clock_manager #
297
(
298 56 javieralso
   .divisor(`CLOCK_DIVISOR)
299 2 rfajardo
)
300
clk_adjust (
301
        .clk_i(clk),
302
        .clk_o(wb_clk)
303
);
304
 
305
//
306
// Unused WISHBONE signals
307
//
308
assign wb_us_err_o = 1'b0;
309
assign wb_fs_err_o = 1'b0;
310
assign wb_sp_err_o = 1'b0;
311
 
312
//
313
// Unused interrupts
314
//
315
assign pic_ints[`APP_INT_RES1] = 'b0;
316
assign pic_ints[`APP_INT_RES2] = 'b0;
317
assign pic_ints[`APP_INT_RES3] = 'b0;
318
assign pic_ints[`APP_INT_PS2] = 'b0;
319
 
320
//
321
// Ethernet tri-state
322
//
323
`ifdef ETHERNET
324
assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz;
325
assign eth_trste = `ETH_RESET;
326
`endif
327
 
328
 
329
//
330
// RISC Instruction address for Flash
331
//
332
// Until first access to real Flash area,
333
// CPU instruction is fixed to jump to the Flash area.
334
// After Flash area is accessed, CPU instructions 
335
// come from the tc_top (wishbone "switch").
336
//
337
`ifdef START_UP
338
reg jump_flash;
339
reg [3:0] rif_counter;
340
reg [31:0] rif_dat_int;
341
reg rif_ack_int;
342
 
343
always @(posedge wb_clk or negedge rstn)
344
begin
345
        if (!rstn) begin
346
                jump_flash <= #1 1'b1;
347
                rif_counter <= 4'h0;
348
                rif_ack_int <= 1'b0;
349
        end
350
        else begin
351
                rif_ack_int <= 1'b0;
352
 
353
                if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
354
                        jump_flash <= #1 1'b0;
355
 
356
                if ( jump_flash == 1'b1 ) begin
357 33 rfajardo
                        if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o )
358
                                rif_ack_int <= 1'b1;
359
 
360
            if ( rif_ack_int == 1'b1 ) begin
361 2 rfajardo
                                rif_counter <= rif_counter + 1'b1;
362 33 rfajardo
                                rif_ack_int <= 1'b0;
363
            end
364 2 rfajardo
                end
365
        end
366
end
367
 
368
always @ (rif_counter)
369
begin
370
        case ( rif_counter )
371
                4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 };
372
                4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 };
373
                4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 };
374
                4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 };
375
                default: rif_dat_int = 32'h0000_0000;
376
        endcase
377
end
378
 
379
assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i;
380
 
381
assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i;
382
 
383
`else
384
assign wb_rif_dat_i = wb_rim_dat_i;
385
assign wb_rif_ack_i = wb_rim_ack_i;
386
`endif
387
 
388
 
389
//
390
// TAP<->dbg_interface
391
//      
392
wire jtag_tck;
393
wire debug_tdi;
394
wire debug_tdo;
395
wire capture_dr;
396
wire shift_dr;
397
wire pause_dr;
398
wire update_dr;
399
 
400
wire debug_select;
401
wire test_logic_reset;
402
 
403
//
404
// Instantiation of the development i/f
405
//
406
adbg_top dbg_top  (
407
 
408
        // JTAG pins
409
      .tck_i    ( jtag_tck ),
410
      .tdi_i    ( debug_tdi ),
411
      .tdo_o    ( debug_tdo ),
412
      .rst_i    ( test_logic_reset ),           //cable without rst
413
 
414
        // Boundary Scan signals
415
      .capture_dr_i ( capture_dr ),
416
      .shift_dr_i  ( shift_dr ),
417
      .pause_dr_i  ( pause_dr ),
418
      .update_dr_i ( update_dr ),
419
 
420
      .debug_select_i( debug_select ),
421
        // WISHBONE common
422
      .wb_clk_i   ( wb_clk ),
423
 
424
      // WISHBONE master interface
425
      .wb_adr_o  ( wb_dm_adr_o ),
426
      .wb_dat_i  ( wb_dm_dat_i ),
427
      .wb_dat_o  ( wb_dm_dat_o ),
428
      .wb_sel_o  ( wb_dm_sel_o ),
429
      .wb_we_o   ( wb_dm_we_o  ),
430
      .wb_stb_o  ( wb_dm_stb_o ),
431
      .wb_cyc_o  ( wb_dm_cyc_o ),
432
      .wb_ack_i  ( wb_dm_ack_i ),
433
      .wb_err_i  ( wb_dm_err_i ),
434
      .wb_cti_o  ( ),
435
      .wb_bte_o  ( ),
436
 
437
      // RISC signals
438
      .cpu0_clk_i  ( wb_clk ),
439
      .cpu0_addr_o ( dbg_adr ),
440
      .cpu0_data_i ( dbg_dat_risc ),
441
      .cpu0_data_o ( dbg_dat_dbg ),
442
      .cpu0_bp_i   ( dbg_bp ),
443
      .cpu0_stall_o( dbg_stall ),
444 20 rfajardo
      .cpu0_stb_o  ( dbg_stb ),
445
      .cpu0_we_o   ( dbg_we ),
446 2 rfajardo
      .cpu0_ack_i  ( dbg_ack ),
447
      .cpu0_rst_o  ( )
448
 
449
);
450
 
451
//
452
// JTAG TAP controller instantiation
453
//
454
`ifdef GENERIC_TAP
455
tap_top tap_top(
456
         // JTAG pads
457
         .tms_pad_i(jtag_tms),
458
         .tck_pad_i(jtag_tck),
459
         .trstn_pad_i(rstn),
460
         .tdi_pad_i(jtag_tdi),
461
         .tdo_pad_o(jtag_tdo),
462
         .tdo_padoe_o( ),
463
 
464
         // TAP states
465
         .test_logic_reset_o( test_logic_reset ),
466
         .run_test_idle_o(),
467
         .shift_dr_o(shift_dr),
468
         .pause_dr_o(pause_dr),
469
         .update_dr_o(update_dr),
470
         .capture_dr_o(capture_dr),
471
 
472
         // Select signals for boundary scan or mbist
473
         .extest_select_o(),
474
         .sample_preload_select_o(),
475
         .mbist_select_o(),
476
         .debug_select_o(debug_select),
477
 
478
         // TDO signal that is connected to TDI of sub-modules.
479
         .tdi_o(debug_tdi),
480
 
481
         // TDI signals from sub-modules
482
         .debug_tdo_i(debug_tdo),    // from debug module
483
         .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
484
         .mbist_tdo_i(1'b0)     // from Mbist Chain
485
);
486
`elsif FPGA_TAP
487
`ifdef ALTERA_FPGA
488
altera_virtual_jtag tap_top(
489
        .tck_o(jtag_tck),
490 26 rfajardo
        .debug_tdo_i(debug_tdo),
491 2 rfajardo
        .tdi_o(debug_tdi),
492
        .test_logic_reset_o(test_logic_reset),
493
        .run_test_idle_o(),
494
        .shift_dr_o(shift_dr),
495
        .capture_dr_o(capture_dr),
496
        .pause_dr_o(pause_dr),
497
        .update_dr_o(update_dr),
498
        .debug_select_o(debug_select)
499
);
500
`elsif XILINX_FPGA
501
minsoc_xilinx_internal_jtag tap_top(
502
        .tck_o( jtag_tck ),
503
        .debug_tdo_i( debug_tdo ),
504
        .tdi_o( debug_tdi ),
505
 
506
        .test_logic_reset_o( test_logic_reset ),
507
        .run_test_idle_o( ),
508
 
509
        .shift_dr_o( shift_dr ),
510
        .capture_dr_o( capture_dr ),
511
        .pause_dr_o( pause_dr ),
512
        .update_dr_o( update_dr ),
513
        .debug_select_o( debug_select )
514
);
515
`endif // !FPGA_TAP
516
 
517
`endif // !GENERIC_TAP
518
 
519
//
520
// Instantiation of the OR1200 RISC
521
//
522
or1200_top or1200_top (
523
 
524
        // Common
525
        .rst_i          ( wb_rst ),
526
        .clk_i          ( wb_clk ),
527
`ifdef OR1200_CLMODE_1TO2
528
        .clmode_i       ( 2'b01 ),
529
`else
530
`ifdef OR1200_CLMODE_1TO4
531
        .clmode_i       ( 2'b11 ),
532
`else
533
        .clmode_i       ( 2'b00 ),
534
`endif
535
`endif
536
 
537
        // WISHBONE Instruction Master
538
        .iwb_clk_i      ( wb_clk ),
539
        .iwb_rst_i      ( wb_rst ),
540
        .iwb_cyc_o      ( wb_rim_cyc_o ),
541
        .iwb_adr_o      ( wb_rim_adr_o ),
542
        .iwb_dat_i      ( wb_rif_dat_i ),
543
        .iwb_dat_o      ( wb_rim_dat_o ),
544
        .iwb_sel_o      ( wb_rim_sel_o ),
545
        .iwb_ack_i      ( wb_rif_ack_i ),
546
        .iwb_err_i      ( wb_rim_err_i ),
547
        .iwb_rty_i      ( wb_rim_rty_i ),
548
        .iwb_we_o       ( wb_rim_we_o  ),
549
        .iwb_stb_o      ( wb_rim_stb_o ),
550
 
551
        // WISHBONE Data Master
552
        .dwb_clk_i      ( wb_clk ),
553
        .dwb_rst_i      ( wb_rst ),
554
        .dwb_cyc_o      ( wb_rdm_cyc_o ),
555
        .dwb_adr_o      ( wb_rdm_adr_o ),
556
        .dwb_dat_i      ( wb_rdm_dat_i ),
557
        .dwb_dat_o      ( wb_rdm_dat_o ),
558
        .dwb_sel_o      ( wb_rdm_sel_o ),
559
        .dwb_ack_i      ( wb_rdm_ack_i ),
560
        .dwb_err_i      ( wb_rdm_err_i ),
561
        .dwb_rty_i      ( wb_rdm_rty_i ),
562
        .dwb_we_o       ( wb_rdm_we_o  ),
563
        .dwb_stb_o      ( wb_rdm_stb_o ),
564
 
565
        // Debug
566
        .dbg_stall_i    ( dbg_stall ),
567
        .dbg_dat_i      ( dbg_dat_dbg ),
568
        .dbg_adr_i      ( dbg_adr ),
569
        .dbg_ewt_i      ( 1'b0 ),
570
        .dbg_lss_o      ( dbg_lss ),
571
        .dbg_is_o       ( dbg_is ),
572
        .dbg_wp_o       ( dbg_wp ),
573
        .dbg_bp_o       ( dbg_bp ),
574
        .dbg_dat_o      ( dbg_dat_risc ),
575
        .dbg_ack_o      ( dbg_ack ),
576 20 rfajardo
        .dbg_stb_i      ( dbg_stb ),
577
        .dbg_we_i       ( dbg_we ),
578 2 rfajardo
 
579
        // Power Management
580
        .pm_clksd_o     ( ),
581
        .pm_cpustall_i  ( 1'b0 ),
582
        .pm_dc_gate_o   ( ),
583
        .pm_ic_gate_o   ( ),
584
        .pm_dmmu_gate_o ( ),
585
        .pm_immu_gate_o ( ),
586
        .pm_tt_gate_o   ( ),
587
        .pm_cpu_gate_o  ( ),
588
        .pm_wakeup_o    ( ),
589
        .pm_lvolt_o     ( ),
590
 
591
        // Interrupts
592
        .pic_ints_i     ( pic_ints )
593
);
594
 
595
//
596
// Startup OR1k
597
//
598
`ifdef START_UP
599
OR1K_startup OR1K_startup0
600
(
601
    .wb_adr_i(wb_fs_adr_i[6:2]),
602
    .wb_stb_i(wb_fs_stb_i),
603
    .wb_cyc_i(wb_fs_cyc_i),
604
    .wb_dat_o(wb_fs_dat_o),
605
    .wb_ack_o(wb_fs_ack_o),
606
    .wb_clk(wb_clk),
607
    .wb_rst(wb_rst)
608
);
609
 
610
spi_flash_top #
611
(
612
   .divider(0),
613
   .divider_len(2)
614
)
615
spi_flash_top0
616
(
617
   .wb_clk_i(wb_clk),
618
   .wb_rst_i(wb_rst),
619
   .wb_adr_i(wb_sp_adr_i[4:2]),
620
   .wb_dat_i(wb_sp_dat_i),
621
   .wb_dat_o(wb_sp_dat_o),
622
   .wb_sel_i(wb_sp_sel_i),
623
   .wb_we_i(wb_sp_we_i),
624
   .wb_stb_i(wb_sp_stb_i),
625
   .wb_cyc_i(wb_sp_cyc_i),
626
   .wb_ack_o(wb_sp_ack_o),
627
 
628
   .mosi_pad_o(spi_flash_mosi),
629
   .miso_pad_i(spi_flash_miso),
630
   .sclk_pad_o(spi_flash_sclk),
631
   .ss_pad_o(spi_flash_ss)
632
);
633
`else
634
assign wb_fs_dat_o = 32'h0000_0000;
635
assign wb_fs_ack_o = 1'b0;
636
assign wb_sp_dat_o = 32'h0000_0000;
637
assign wb_sp_ack_o = 1'b0;
638
`endif
639
 
640
//
641
// Instantiation of the SRAM controller
642
//
643
minsoc_onchip_ram_top #
644
(
645
    .adr_width(`MEMORY_ADR_WIDTH)     //16 blocks of 2048 bytes memory 32768
646
)
647
onchip_ram_top (
648
 
649
        // WISHBONE common
650
        .wb_clk_i       ( wb_clk ),
651
        .wb_rst_i       ( wb_rst ),
652
 
653
        // WISHBONE slave
654
        .wb_dat_i       ( wb_ss_dat_i ),
655
        .wb_dat_o       ( wb_ss_dat_o ),
656
        .wb_adr_i       ( wb_ss_adr_i ),
657
        .wb_sel_i       ( wb_ss_sel_i ),
658
        .wb_we_i        ( wb_ss_we_i  ),
659
        .wb_cyc_i       ( wb_ss_cyc_i ),
660
        .wb_stb_i       ( wb_ss_stb_i ),
661
        .wb_ack_o       ( wb_ss_ack_o ),
662
        .wb_err_o       ( wb_ss_err_o )
663
);
664
 
665
//
666
// Instantiation of the UART16550
667
//
668
`ifdef UART
669
uart_top uart_top (
670
 
671
        // WISHBONE common
672
        .wb_clk_i       ( wb_clk ),
673
        .wb_rst_i       ( wb_rst ),
674
 
675
        // WISHBONE slave
676
        .wb_adr_i       ( wb_us_adr_i[4:0] ),
677
        .wb_dat_i       ( wb_us_dat_i ),
678
        .wb_dat_o       ( wb_us_dat_o ),
679
        .wb_we_i        ( wb_us_we_i  ),
680
        .wb_stb_i       ( wb_us_stb_i ),
681
        .wb_cyc_i       ( wb_us_cyc_i ),
682
        .wb_ack_o       ( wb_us_ack_o ),
683
        .wb_sel_i       ( wb_us_sel_i ),
684
 
685
        // Interrupt request
686
        .int_o          ( pic_ints[`APP_INT_UART] ),
687
 
688
        // UART signals
689
        // serial input/output
690
        .stx_pad_o      ( uart_stx ),
691
        .srx_pad_i      ( uart_srx ),
692
 
693
        // modem signals
694
        .rts_pad_o      ( ),
695
        .cts_pad_i      ( 1'b0 ),
696
        .dtr_pad_o      ( ),
697
        .dsr_pad_i      ( 1'b0 ),
698
        .ri_pad_i       ( 1'b0 ),
699
        .dcd_pad_i      ( 1'b0 )
700
);
701
`else
702
assign wb_us_dat_o = 32'h0000_0000;
703
assign wb_us_ack_o = 1'b0;
704 17 rfajardo
 
705 16 rfajardo
assign pic_ints[`APP_INT_UART] = 1'b0;
706 2 rfajardo
`endif
707
 
708
//
709
// Instantiation of the Ethernet 10/100 MAC
710
//
711
`ifdef ETHERNET
712
eth_top eth_top (
713
 
714
        // WISHBONE common
715
        .wb_clk_i       ( wb_clk ),
716
        .wb_rst_i       ( wb_rst ),
717
 
718
        // WISHBONE slave
719
        .wb_dat_i       ( wb_es_dat_i ),
720
        .wb_dat_o       ( wb_es_dat_o ),
721
        .wb_adr_i       ( wb_es_adr_i[11:2] ),
722
        .wb_sel_i       ( wb_es_sel_i ),
723
        .wb_we_i        ( wb_es_we_i  ),
724
        .wb_cyc_i       ( wb_es_cyc_i ),
725
        .wb_stb_i       ( wb_es_stb_i ),
726
        .wb_ack_o       ( wb_es_ack_o ),
727
        .wb_err_o       ( wb_es_err_o ),
728
 
729
        // WISHBONE master
730
        .m_wb_adr_o     ( wb_em_adr_o ),
731
        .m_wb_sel_o     ( wb_em_sel_o ),
732
        .m_wb_we_o      ( wb_em_we_o  ),
733
        .m_wb_dat_o     ( wb_em_dat_o ),
734
        .m_wb_dat_i     ( wb_em_dat_i ),
735
        .m_wb_cyc_o     ( wb_em_cyc_o ),
736
        .m_wb_stb_o     ( wb_em_stb_o ),
737
        .m_wb_ack_i     ( wb_em_ack_i ),
738
        .m_wb_err_i     ( wb_em_err_i ),
739
 
740
        // TX
741
        .mtx_clk_pad_i  ( eth_tx_clk ),
742
        .mtxd_pad_o     ( eth_txd ),
743
        .mtxen_pad_o    ( eth_tx_en ),
744
        .mtxerr_pad_o   ( eth_tx_er ),
745
 
746
        // RX
747
        .mrx_clk_pad_i  ( eth_rx_clk ),
748
        .mrxd_pad_i     ( eth_rxd ),
749
        .mrxdv_pad_i    ( eth_rx_dv ),
750
        .mrxerr_pad_i   ( eth_rx_er ),
751
        .mcoll_pad_i    ( eth_col ),
752
        .mcrs_pad_i     ( eth_crs ),
753
 
754
        // MIIM
755
        .mdc_pad_o      ( eth_mdc ),
756
        .md_pad_i       ( eth_mdio ),
757
        .md_pad_o       ( eth_mdo ),
758
        .md_padoe_o     ( eth_mdoe ),
759
 
760
        // Interrupt
761
        .int_o          ( pic_ints[`APP_INT_ETH] )
762
);
763
`else
764
assign wb_es_dat_o = 32'h0000_0000;
765
assign wb_es_ack_o = 1'b0;
766 14 rfajardo
assign wb_es_err_o = 1'b0;
767 2 rfajardo
 
768
assign wb_em_adr_o = 32'h0000_0000;
769
assign wb_em_sel_o = 4'h0;
770
assign wb_em_we_o = 1'b0;
771
assign wb_em_dat_o = 32'h0000_0000;
772
assign wb_em_cyc_o = 1'b0;
773
assign wb_em_stb_o = 1'b0;
774 17 rfajardo
 
775 16 rfajardo
assign pic_ints[`APP_INT_ETH] = 1'b0;
776 2 rfajardo
`endif
777
 
778
//
779
// Instantiation of the Traffic COP
780
//
781
minsoc_tc_top #(`APP_ADDR_DEC_W,
782
         `APP_ADDR_SRAM,
783
         `APP_ADDR_DEC_W,
784
         `APP_ADDR_FLASH,
785
         `APP_ADDR_DECP_W,
786
         `APP_ADDR_PERIP,
787
         `APP_ADDR_DEC_W,
788
         `APP_ADDR_SPI,
789
         `APP_ADDR_ETH,
790
         `APP_ADDR_AUDIO,
791
         `APP_ADDR_UART,
792
         `APP_ADDR_PS2,
793
         `APP_ADDR_RES1,
794
         `APP_ADDR_RES2
795
        ) tc_top (
796
 
797
        // WISHBONE common
798
        .wb_clk_i       ( wb_clk ),
799
        .wb_rst_i       ( wb_rst ),
800
 
801
        // WISHBONE Initiator 0
802
        .i0_wb_cyc_i    ( 1'b0 ),
803
        .i0_wb_stb_i    ( 1'b0 ),
804
        .i0_wb_adr_i    ( 32'h0000_0000 ),
805
        .i0_wb_sel_i    ( 4'b0000 ),
806
        .i0_wb_we_i     ( 1'b0 ),
807
        .i0_wb_dat_i    ( 32'h0000_0000 ),
808
        .i0_wb_dat_o    ( ),
809
        .i0_wb_ack_o    ( ),
810
        .i0_wb_err_o    ( ),
811
 
812
        // WISHBONE Initiator 1
813
        .i1_wb_cyc_i    ( wb_em_cyc_o ),
814
        .i1_wb_stb_i    ( wb_em_stb_o ),
815
        .i1_wb_adr_i    ( wb_em_adr_o ),
816
        .i1_wb_sel_i    ( wb_em_sel_o ),
817
        .i1_wb_we_i     ( wb_em_we_o  ),
818
        .i1_wb_dat_i    ( wb_em_dat_o ),
819
        .i1_wb_dat_o    ( wb_em_dat_i ),
820
        .i1_wb_ack_o    ( wb_em_ack_i ),
821
        .i1_wb_err_o    ( wb_em_err_i ),
822
 
823
        // WISHBONE Initiator 2
824
        .i2_wb_cyc_i    ( 1'b0 ),
825
        .i2_wb_stb_i    ( 1'b0 ),
826
        .i2_wb_adr_i    ( 32'h0000_0000 ),
827
        .i2_wb_sel_i    ( 4'b0000 ),
828
        .i2_wb_we_i     ( 1'b0 ),
829
        .i2_wb_dat_i    ( 32'h0000_0000 ),
830
        .i2_wb_dat_o    ( ),
831
        .i2_wb_ack_o    ( ),
832
        .i2_wb_err_o    ( ),
833
 
834
        // WISHBONE Initiator 3
835
        .i3_wb_cyc_i    ( wb_dm_cyc_o ),
836
        .i3_wb_stb_i    ( wb_dm_stb_o ),
837
        .i3_wb_adr_i    ( wb_dm_adr_o ),
838
        .i3_wb_sel_i    ( wb_dm_sel_o ),
839
        .i3_wb_we_i     ( wb_dm_we_o  ),
840
        .i3_wb_dat_i    ( wb_dm_dat_o ),
841
        .i3_wb_dat_o    ( wb_dm_dat_i ),
842
        .i3_wb_ack_o    ( wb_dm_ack_i ),
843
        .i3_wb_err_o    ( wb_dm_err_i ),
844
 
845
        // WISHBONE Initiator 4
846
        .i4_wb_cyc_i    ( wb_rdm_cyc_o ),
847
        .i4_wb_stb_i    ( wb_rdm_stb_o ),
848
        .i4_wb_adr_i    ( wb_rdm_adr_o ),
849
        .i4_wb_sel_i    ( wb_rdm_sel_o ),
850
        .i4_wb_we_i     ( wb_rdm_we_o  ),
851
        .i4_wb_dat_i    ( wb_rdm_dat_o ),
852
        .i4_wb_dat_o    ( wb_rdm_dat_i ),
853
        .i4_wb_ack_o    ( wb_rdm_ack_i ),
854
        .i4_wb_err_o    ( wb_rdm_err_i ),
855
 
856
        // WISHBONE Initiator 5
857
        .i5_wb_cyc_i    ( wb_rim_cyc_o ),
858
        .i5_wb_stb_i    ( wb_rim_stb_o ),
859
        .i5_wb_adr_i    ( wb_rim_adr_o ),
860
        .i5_wb_sel_i    ( wb_rim_sel_o ),
861
        .i5_wb_we_i     ( wb_rim_we_o  ),
862
        .i5_wb_dat_i    ( wb_rim_dat_o ),
863
        .i5_wb_dat_o    ( wb_rim_dat_i ),
864
        .i5_wb_ack_o    ( wb_rim_ack_i ),
865
        .i5_wb_err_o    ( wb_rim_err_i ),
866
 
867
        // WISHBONE Initiator 6
868
        .i6_wb_cyc_i    ( 1'b0 ),
869
        .i6_wb_stb_i    ( 1'b0 ),
870
        .i6_wb_adr_i    ( 32'h0000_0000 ),
871
        .i6_wb_sel_i    ( 4'b0000 ),
872
        .i6_wb_we_i     ( 1'b0 ),
873
        .i6_wb_dat_i    ( 32'h0000_0000 ),
874
        .i6_wb_dat_o    ( ),
875
        .i6_wb_ack_o    ( ),
876
        .i6_wb_err_o    ( ),
877
 
878
        // WISHBONE Initiator 7
879
        .i7_wb_cyc_i    ( 1'b0 ),
880
        .i7_wb_stb_i    ( 1'b0 ),
881
        .i7_wb_adr_i    ( 32'h0000_0000 ),
882
        .i7_wb_sel_i    ( 4'b0000 ),
883
        .i7_wb_we_i     ( 1'b0 ),
884
        .i7_wb_dat_i    ( 32'h0000_0000 ),
885
        .i7_wb_dat_o    ( ),
886
        .i7_wb_ack_o    ( ),
887
        .i7_wb_err_o    ( ),
888
 
889
        // WISHBONE Target 0
890
        .t0_wb_cyc_o    ( wb_ss_cyc_i ),
891
        .t0_wb_stb_o    ( wb_ss_stb_i ),
892
        .t0_wb_adr_o    ( wb_ss_adr_i ),
893
        .t0_wb_sel_o    ( wb_ss_sel_i ),
894
        .t0_wb_we_o     ( wb_ss_we_i  ),
895
        .t0_wb_dat_o    ( wb_ss_dat_i ),
896
        .t0_wb_dat_i    ( wb_ss_dat_o ),
897
        .t0_wb_ack_i    ( wb_ss_ack_o ),
898
        .t0_wb_err_i    ( wb_ss_err_o ),
899
 
900
        // WISHBONE Target 1
901
        .t1_wb_cyc_o    ( wb_fs_cyc_i ),
902
        .t1_wb_stb_o    ( wb_fs_stb_i ),
903
        .t1_wb_adr_o    ( wb_fs_adr_i ),
904
        .t1_wb_sel_o    ( wb_fs_sel_i ),
905
        .t1_wb_we_o     ( wb_fs_we_i  ),
906
        .t1_wb_dat_o    ( wb_fs_dat_i ),
907
        .t1_wb_dat_i    ( wb_fs_dat_o ),
908
        .t1_wb_ack_i    ( wb_fs_ack_o ),
909
        .t1_wb_err_i    ( wb_fs_err_o ),
910
 
911
        // WISHBONE Target 2
912
        .t2_wb_cyc_o    ( wb_sp_cyc_i ),
913
        .t2_wb_stb_o    ( wb_sp_stb_i ),
914
        .t2_wb_adr_o    ( wb_sp_adr_i ),
915
        .t2_wb_sel_o    ( wb_sp_sel_i ),
916
        .t2_wb_we_o     ( wb_sp_we_i  ),
917
        .t2_wb_dat_o    ( wb_sp_dat_i ),
918
        .t2_wb_dat_i    ( wb_sp_dat_o ),
919
        .t2_wb_ack_i    ( wb_sp_ack_o ),
920
        .t2_wb_err_i    ( wb_sp_err_o ),
921
 
922
        // WISHBONE Target 3
923
        .t3_wb_cyc_o    ( wb_es_cyc_i ),
924
        .t3_wb_stb_o    ( wb_es_stb_i ),
925
        .t3_wb_adr_o    ( wb_es_adr_i ),
926
        .t3_wb_sel_o    ( wb_es_sel_i ),
927
        .t3_wb_we_o     ( wb_es_we_i  ),
928
        .t3_wb_dat_o    ( wb_es_dat_i ),
929
        .t3_wb_dat_i    ( wb_es_dat_o ),
930
        .t3_wb_ack_i    ( wb_es_ack_o ),
931
        .t3_wb_err_i    ( wb_es_err_o ),
932
 
933
        // WISHBONE Target 4
934
        .t4_wb_cyc_o    ( ),
935
        .t4_wb_stb_o    ( ),
936
        .t4_wb_adr_o    ( ),
937
        .t4_wb_sel_o    ( ),
938
        .t4_wb_we_o     ( ),
939
        .t4_wb_dat_o    ( ),
940
        .t4_wb_dat_i    ( 32'h0000_0000 ),
941
        .t4_wb_ack_i    ( 1'b0 ),
942
        .t4_wb_err_i    ( 1'b1 ),
943
 
944
        // WISHBONE Target 5
945
        .t5_wb_cyc_o    ( wb_us_cyc_i ),
946
        .t5_wb_stb_o    ( wb_us_stb_i ),
947
        .t5_wb_adr_o    ( wb_us_adr_i ),
948
        .t5_wb_sel_o    ( wb_us_sel_i ),
949
        .t5_wb_we_o     ( wb_us_we_i  ),
950
        .t5_wb_dat_o    ( wb_us_dat_i ),
951
        .t5_wb_dat_i    ( wb_us_dat_o ),
952
        .t5_wb_ack_i    ( wb_us_ack_o ),
953
        .t5_wb_err_i    ( wb_us_err_o ),
954
 
955
        // WISHBONE Target 6
956
        .t6_wb_cyc_o    ( ),
957
        .t6_wb_stb_o    ( ),
958
        .t6_wb_adr_o    ( ),
959
        .t6_wb_sel_o    ( ),
960
        .t6_wb_we_o     ( ),
961
        .t6_wb_dat_o    ( ),
962
        .t6_wb_dat_i    ( 32'h0000_0000 ),
963
        .t6_wb_ack_i    ( 1'b0 ),
964
        .t6_wb_err_i    ( 1'b1 ),
965
 
966
        // WISHBONE Target 7
967
        .t7_wb_cyc_o    ( ),
968
        .t7_wb_stb_o    ( ),
969
        .t7_wb_adr_o    ( ),
970
        .t7_wb_sel_o    ( ),
971
        .t7_wb_we_o     ( ),
972
        .t7_wb_dat_o    ( ),
973
        .t7_wb_dat_i    ( 32'h0000_0000 ),
974
        .t7_wb_ack_i    ( 1'b0 ),
975
        .t7_wb_err_i    ( 1'b1 ),
976
 
977
        // WISHBONE Target 8
978
        .t8_wb_cyc_o    ( ),
979
        .t8_wb_stb_o    ( ),
980
        .t8_wb_adr_o    ( ),
981
        .t8_wb_sel_o    ( ),
982
        .t8_wb_we_o     ( ),
983
        .t8_wb_dat_o    ( ),
984
        .t8_wb_dat_i    ( 32'h0000_0000 ),
985
        .t8_wb_ack_i    ( 1'b0 ),
986
        .t8_wb_err_i    ( 1'b1 )
987
);
988
 
989
//initial begin
990
//  $dumpvars(0);
991
//  $dumpfile("dump.vcd");
992
//end
993
 
994
endmodule

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