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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Blame information for rev 7

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1 2 rfajardo
`include "minsoc_defines.v"
2
`include "or1200_defines.v"
3
 
4
module minsoc_top (
5
   clk,reset
6
 
7
   //JTAG ports
8
`ifdef GENERIC_TAP
9
   , jtag_tdi,jtag_tms,jtag_tck,
10
   jtag_tdo,jtag_vref,jtag_gnd
11
`endif
12
 
13
   //SPI ports
14
`ifdef START_UP
15
   , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss
16
`endif
17
 
18
   //UART ports
19
`ifdef UART
20
   , uart_stx,uart_srx
21
`endif
22
 
23
        // Ethernet ports
24
`ifdef ETHERNET
25
        , eth_col, eth_crs, eth_trste, eth_tx_clk,
26
        eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk,
27
        eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint,
28
        eth_mdc, eth_mdio
29
`endif
30
);
31
 
32
//
33
// I/O Ports
34
//
35
 
36
   input         clk;
37
   input         reset;
38
 
39
//
40
// SPI controller external i/f wires
41
//
42
`ifdef START_UP
43
output spi_flash_mosi;
44
input spi_flash_miso;
45
output spi_flash_sclk;
46
output [1:0] spi_flash_ss;
47
`endif
48
 
49
//
50
// UART
51
//
52
`ifdef UART
53
   output        uart_stx;
54
   input         uart_srx;
55
`endif
56
 
57
//
58
// Ethernet
59
//
60
`ifdef ETHERNET
61
output                  eth_tx_er;
62
input                   eth_tx_clk;
63
output                  eth_tx_en;
64
output  [3:0]            eth_txd;
65
input                   eth_rx_er;
66
input                   eth_rx_clk;
67
input                   eth_rx_dv;
68
input   [3:0]            eth_rxd;
69
input                   eth_col;
70
input                   eth_crs;
71
output                  eth_trste;
72
input                   eth_fds_mdint;
73
inout                   eth_mdio;
74
output                  eth_mdc;
75
`endif
76
 
77
//
78
// JTAG
79
//
80
`ifdef GENERIC_TAP
81
   input         jtag_tdi;
82
   input         jtag_tms;
83
   input         jtag_tck;
84
   output        jtag_tdo;
85
   output        jtag_vref;
86
   output        jtag_gnd;
87
 
88
 
89
assign jtag_vref = 1'b1;
90
assign jtag_gnd = 1'b0;
91
`endif
92
 
93
wire rstn;
94
 
95 7 rfajardo
`ifdef POSITIVE_RESET
96 2 rfajardo
assign rstn = ~reset;
97 7 rfajardo
`elsif NEGATIVE_RESET
98
assign rstn = reset;
99
`endif
100 2 rfajardo
 
101
//
102
// Internal wires
103
//
104
 
105
//
106
// Debug core master i/f wires
107
//
108
wire    [31:0]           wb_dm_adr_o;
109
wire    [31:0]           wb_dm_dat_i;
110
wire    [31:0]           wb_dm_dat_o;
111
wire    [3:0]            wb_dm_sel_o;
112
wire                    wb_dm_we_o;
113
wire                    wb_dm_stb_o;
114
wire                    wb_dm_cyc_o;
115
wire                    wb_dm_ack_i;
116
wire                    wb_dm_err_i;
117
 
118
//
119
// Debug <-> RISC wires
120
//
121
wire    [3:0]            dbg_lss;
122
wire    [1:0]            dbg_is;
123
wire    [10:0]           dbg_wp;
124
wire                    dbg_bp;
125
wire    [31:0]           dbg_dat_dbg;
126
wire    [31:0]           dbg_dat_risc;
127
wire    [31:0]           dbg_adr;
128
wire                    dbg_ewt;
129
wire                    dbg_stall;
130
wire    [2:0]            dbg_op;     //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb  (didn't change for backward compatibility with DBG_IF_MODEL
131
wire                    dbg_ack;
132
 
133
//
134
// RISC instruction master i/f wires
135
//
136
wire    [31:0]           wb_rim_adr_o;
137
wire                    wb_rim_cyc_o;
138
wire    [31:0]           wb_rim_dat_i;
139
wire    [31:0]           wb_rim_dat_o;
140
wire    [3:0]            wb_rim_sel_o;
141
wire                    wb_rim_ack_i;
142
wire                    wb_rim_err_i;
143
wire                    wb_rim_rty_i = 1'b0;
144
wire                    wb_rim_we_o;
145
wire                    wb_rim_stb_o;
146
wire    [31:0]           wb_rif_dat_i;
147
wire                    wb_rif_ack_i;
148
 
149
//
150
// RISC data master i/f wires
151
//
152
wire    [31:0]           wb_rdm_adr_o;
153
wire                    wb_rdm_cyc_o;
154
wire    [31:0]           wb_rdm_dat_i;
155
wire    [31:0]           wb_rdm_dat_o;
156
wire    [3:0]            wb_rdm_sel_o;
157
wire                    wb_rdm_ack_i;
158
wire                    wb_rdm_err_i;
159
wire                    wb_rdm_rty_i = 1'b0;
160
wire                    wb_rdm_we_o;
161
wire                    wb_rdm_stb_o;
162
 
163
//
164
// RISC misc
165
//
166
wire    [19:0]           pic_ints;
167
 
168
//
169
// Flash controller slave i/f wires
170
//
171
wire    [31:0]           wb_fs_dat_i;
172
wire    [31:0]           wb_fs_dat_o;
173
wire    [31:0]           wb_fs_adr_i;
174
wire    [3:0]            wb_fs_sel_i;
175
wire                    wb_fs_we_i;
176
wire                    wb_fs_cyc_i;
177
wire                    wb_fs_stb_i;
178
wire                    wb_fs_ack_o;
179
wire                    wb_fs_err_o;
180
 
181
//
182
// SPI controller slave i/f wires
183
//
184
wire    [31:0]           wb_sp_dat_i;
185
wire    [31:0]           wb_sp_dat_o;
186
wire    [31:0]           wb_sp_adr_i;
187
wire    [3:0]            wb_sp_sel_i;
188
wire                    wb_sp_we_i;
189
wire                    wb_sp_cyc_i;
190
wire                    wb_sp_stb_i;
191
wire                    wb_sp_ack_o;
192
wire                    wb_sp_err_o;
193
 
194
//
195
// SPI controller external i/f wires
196
//
197
wire spi_flash_mosi;
198
wire spi_flash_miso;
199
wire spi_flash_sclk;
200
wire [1:0] spi_flash_ss;
201
 
202
//
203
// SRAM controller slave i/f wires
204
//
205
wire    [31:0]           wb_ss_dat_i;
206
wire    [31:0]           wb_ss_dat_o;
207
wire    [31:0]           wb_ss_adr_i;
208
wire    [3:0]            wb_ss_sel_i;
209
wire                    wb_ss_we_i;
210
wire                    wb_ss_cyc_i;
211
wire                    wb_ss_stb_i;
212
wire                    wb_ss_ack_o;
213
wire                    wb_ss_err_o;
214
 
215
//
216
// Ethernet core master i/f wires
217
//
218
wire    [31:0]           wb_em_adr_o;
219
wire    [31:0]           wb_em_dat_i;
220
wire    [31:0]           wb_em_dat_o;
221
wire    [3:0]            wb_em_sel_o;
222
wire                    wb_em_we_o;
223
wire                    wb_em_stb_o;
224
wire                    wb_em_cyc_o;
225
wire                    wb_em_ack_i;
226
wire                    wb_em_err_i;
227
 
228
//
229
// Ethernet core slave i/f wires
230
//
231
wire    [31:0]           wb_es_dat_i;
232
wire    [31:0]           wb_es_dat_o;
233
wire    [31:0]           wb_es_adr_i;
234
wire    [3:0]            wb_es_sel_i;
235
wire                    wb_es_we_i;
236
wire                    wb_es_cyc_i;
237
wire                    wb_es_stb_i;
238
wire                    wb_es_ack_o;
239
wire                    wb_es_err_o;
240
 
241
//
242
// Ethernet external i/f wires
243
//
244
wire                    eth_mdo;
245
wire                    eth_mdoe;
246
 
247
//
248
// UART16550 core slave i/f wires
249
//
250
wire    [31:0]           wb_us_dat_i;
251
wire    [31:0]           wb_us_dat_o;
252
wire    [31:0]           wb_us_adr_i;
253
wire    [3:0]            wb_us_sel_i;
254
wire                    wb_us_we_i;
255
wire                    wb_us_cyc_i;
256
wire                    wb_us_stb_i;
257
wire                    wb_us_ack_o;
258
wire                    wb_us_err_o;
259
 
260
//
261
// UART external i/f wires
262
//
263
wire                    uart_stx;
264
wire                    uart_srx;
265
 
266
//
267
// Reset debounce
268
//
269
reg                     rst_r;
270
reg                     wb_rst;
271
 
272
//
273
// Global clock
274
//
275
wire                    wb_clk;
276
 
277
//
278
// Reset debounce
279
//
280
always @(posedge wb_clk or negedge rstn)
281
        if (~rstn)
282
                rst_r <= 1'b1;
283
        else
284
                rst_r <= #1 1'b0;
285
 
286
//
287
// Reset debounce
288
//
289
always @(posedge wb_clk)
290
        wb_rst <= #1 rst_r;
291
 
292
//
293 7 rfajardo
// Clock Divider
294 2 rfajardo
//
295
minsoc_clock_manager #
296
(
297
   .divisor(`CLOCK_DIVISOR)
298
)
299
clk_adjust (
300
        .clk_i(clk),
301
        .clk_o(wb_clk)
302
);
303
 
304
//
305
// Unused WISHBONE signals
306
//
307
assign wb_us_err_o = 1'b0;
308
assign wb_fs_err_o = 1'b0;
309
assign wb_sp_err_o = 1'b0;
310
 
311
//
312
// Unused interrupts
313
//
314
assign pic_ints[`APP_INT_RES1] = 'b0;
315
assign pic_ints[`APP_INT_RES2] = 'b0;
316
assign pic_ints[`APP_INT_RES3] = 'b0;
317
assign pic_ints[`APP_INT_PS2] = 'b0;
318
 
319
//
320
// Ethernet tri-state
321
//
322
`ifdef ETHERNET
323
assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz;
324
assign eth_trste = `ETH_RESET;
325
`endif
326
 
327
 
328
//
329
// RISC Instruction address for Flash
330
//
331
// Until first access to real Flash area,
332
// CPU instruction is fixed to jump to the Flash area.
333
// After Flash area is accessed, CPU instructions 
334
// come from the tc_top (wishbone "switch").
335
//
336
`ifdef START_UP
337
reg jump_flash;
338
reg [3:0] rif_counter;
339
reg [31:0] rif_dat_int;
340
reg rif_ack_int;
341
 
342
always @(posedge wb_clk or negedge rstn)
343
begin
344
        if (!rstn) begin
345
                jump_flash <= #1 1'b1;
346
                rif_counter <= 4'h0;
347
                rif_ack_int <= 1'b0;
348
        end
349
        else begin
350
                rif_ack_int <= 1'b0;
351
 
352
                if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
353
                        jump_flash <= #1 1'b0;
354
 
355
                if ( jump_flash == 1'b1 ) begin
356
                        if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) begin
357
                                rif_counter <= rif_counter + 1'b1;
358
                                rif_ack_int <= 1'b1;
359
                        end
360
                end
361
        end
362
end
363
 
364
always @ (rif_counter)
365
begin
366
        case ( rif_counter )
367
                4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 };
368
                4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 };
369
                4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 };
370
                4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 };
371
                default: rif_dat_int = 32'h0000_0000;
372
        endcase
373
end
374
 
375
assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i;
376
 
377
assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i;
378
 
379
`else
380
assign wb_rif_dat_i = wb_rim_dat_i;
381
assign wb_rif_ack_i = wb_rim_ack_i;
382
`endif
383
 
384
 
385
//
386
// TAP<->dbg_interface
387
//      
388
wire jtag_tck;
389
wire debug_tdi;
390
wire debug_tdo;
391
wire capture_dr;
392
wire shift_dr;
393
wire pause_dr;
394
wire update_dr;
395
 
396
wire debug_select;
397
wire test_logic_reset;
398
 
399
//
400
// Instantiation of the development i/f
401
//
402
adbg_top dbg_top  (
403
 
404
        // JTAG pins
405
      .tck_i    ( jtag_tck ),
406
      .tdi_i    ( debug_tdi ),
407
      .tdo_o    ( debug_tdo ),
408
      .rst_i    ( test_logic_reset ),           //cable without rst
409
 
410
        // Boundary Scan signals
411
      .capture_dr_i ( capture_dr ),
412
      .shift_dr_i  ( shift_dr ),
413
      .pause_dr_i  ( pause_dr ),
414
      .update_dr_i ( update_dr ),
415
 
416
      .debug_select_i( debug_select ),
417
        // WISHBONE common
418
      .wb_clk_i   ( wb_clk ),
419
 
420
      // WISHBONE master interface
421
      .wb_adr_o  ( wb_dm_adr_o ),
422
      .wb_dat_i  ( wb_dm_dat_i ),
423
      .wb_dat_o  ( wb_dm_dat_o ),
424
      .wb_sel_o  ( wb_dm_sel_o ),
425
      .wb_we_o   ( wb_dm_we_o  ),
426
      .wb_stb_o  ( wb_dm_stb_o ),
427
      .wb_cyc_o  ( wb_dm_cyc_o ),
428
      .wb_ack_i  ( wb_dm_ack_i ),
429
      .wb_err_i  ( wb_dm_err_i ),
430
      .wb_cti_o  ( ),
431
      .wb_bte_o  ( ),
432
 
433
      // RISC signals
434
      .cpu0_clk_i  ( wb_clk ),
435
      .cpu0_addr_o ( dbg_adr ),
436
      .cpu0_data_i ( dbg_dat_risc ),
437
      .cpu0_data_o ( dbg_dat_dbg ),
438
      .cpu0_bp_i   ( dbg_bp ),
439
      .cpu0_stall_o( dbg_stall ),
440
      .cpu0_stb_o  ( dbg_op[2] ),
441
      .cpu0_we_o   ( dbg_op[0] ),
442
      .cpu0_ack_i  ( dbg_ack ),
443
      .cpu0_rst_o  ( )
444
 
445
);
446
 
447
//
448
// JTAG TAP controller instantiation
449
//
450
`ifdef GENERIC_TAP
451
tap_top tap_top(
452
         // JTAG pads
453
         .tms_pad_i(jtag_tms),
454
         .tck_pad_i(jtag_tck),
455
         .trstn_pad_i(rstn),
456
         .tdi_pad_i(jtag_tdi),
457
         .tdo_pad_o(jtag_tdo),
458
         .tdo_padoe_o( ),
459
 
460
         // TAP states
461
         .test_logic_reset_o( test_logic_reset ),
462
         .run_test_idle_o(),
463
         .shift_dr_o(shift_dr),
464
         .pause_dr_o(pause_dr),
465
         .update_dr_o(update_dr),
466
         .capture_dr_o(capture_dr),
467
 
468
         // Select signals for boundary scan or mbist
469
         .extest_select_o(),
470
         .sample_preload_select_o(),
471
         .mbist_select_o(),
472
         .debug_select_o(debug_select),
473
 
474
         // TDO signal that is connected to TDI of sub-modules.
475
         .tdi_o(debug_tdi),
476
 
477
         // TDI signals from sub-modules
478
         .debug_tdo_i(debug_tdo),    // from debug module
479
         .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
480
         .mbist_tdo_i(1'b0)     // from Mbist Chain
481
);
482
`elsif FPGA_TAP
483
`ifdef ALTERA_FPGA
484
altera_virtual_jtag tap_top(
485
        .tck_o(jtag_tck),
486
        .debug_tdo_o(debug_tdo),
487
        .tdi_o(debug_tdi),
488
        .test_logic_reset_o(test_logic_reset),
489
        .run_test_idle_o(),
490
        .shift_dr_o(shift_dr),
491
        .capture_dr_o(capture_dr),
492
        .pause_dr_o(pause_dr),
493
        .update_dr_o(update_dr),
494
        .debug_select_o(debug_select)
495
);
496
`elsif XILINX_FPGA
497
minsoc_xilinx_internal_jtag tap_top(
498
        .tck_o( jtag_tck ),
499
        .debug_tdo_i( debug_tdo ),
500
        .tdi_o( debug_tdi ),
501
 
502
        .test_logic_reset_o( test_logic_reset ),
503
        .run_test_idle_o( ),
504
 
505
        .shift_dr_o( shift_dr ),
506
        .capture_dr_o( capture_dr ),
507
        .pause_dr_o( pause_dr ),
508
        .update_dr_o( update_dr ),
509
        .debug_select_o( debug_select )
510
);
511
`endif // !FPGA_TAP
512
 
513
`endif // !GENERIC_TAP
514
 
515
//
516
// Instantiation of the OR1200 RISC
517
//
518
or1200_top or1200_top (
519
 
520
        // Common
521
        .rst_i          ( wb_rst ),
522
        .clk_i          ( wb_clk ),
523
`ifdef OR1200_CLMODE_1TO2
524
        .clmode_i       ( 2'b01 ),
525
`else
526
`ifdef OR1200_CLMODE_1TO4
527
        .clmode_i       ( 2'b11 ),
528
`else
529
        .clmode_i       ( 2'b00 ),
530
`endif
531
`endif
532
 
533
        // WISHBONE Instruction Master
534
        .iwb_clk_i      ( wb_clk ),
535
        .iwb_rst_i      ( wb_rst ),
536
        .iwb_cyc_o      ( wb_rim_cyc_o ),
537
        .iwb_adr_o      ( wb_rim_adr_o ),
538
        .iwb_dat_i      ( wb_rif_dat_i ),
539
        .iwb_dat_o      ( wb_rim_dat_o ),
540
        .iwb_sel_o      ( wb_rim_sel_o ),
541
        .iwb_ack_i      ( wb_rif_ack_i ),
542
        .iwb_err_i      ( wb_rim_err_i ),
543
        .iwb_rty_i      ( wb_rim_rty_i ),
544
        .iwb_we_o       ( wb_rim_we_o  ),
545
        .iwb_stb_o      ( wb_rim_stb_o ),
546
 
547
        // WISHBONE Data Master
548
        .dwb_clk_i      ( wb_clk ),
549
        .dwb_rst_i      ( wb_rst ),
550
        .dwb_cyc_o      ( wb_rdm_cyc_o ),
551
        .dwb_adr_o      ( wb_rdm_adr_o ),
552
        .dwb_dat_i      ( wb_rdm_dat_i ),
553
        .dwb_dat_o      ( wb_rdm_dat_o ),
554
        .dwb_sel_o      ( wb_rdm_sel_o ),
555
        .dwb_ack_i      ( wb_rdm_ack_i ),
556
        .dwb_err_i      ( wb_rdm_err_i ),
557
        .dwb_rty_i      ( wb_rdm_rty_i ),
558
        .dwb_we_o       ( wb_rdm_we_o  ),
559
        .dwb_stb_o      ( wb_rdm_stb_o ),
560
 
561
        // Debug
562
        .dbg_stall_i    ( dbg_stall ),
563
        .dbg_dat_i      ( dbg_dat_dbg ),
564
        .dbg_adr_i      ( dbg_adr ),
565
        .dbg_ewt_i      ( 1'b0 ),
566
        .dbg_lss_o      ( dbg_lss ),
567
        .dbg_is_o       ( dbg_is ),
568
        .dbg_wp_o       ( dbg_wp ),
569
        .dbg_bp_o       ( dbg_bp ),
570
        .dbg_dat_o      ( dbg_dat_risc ),
571
        .dbg_ack_o      ( dbg_ack ),
572
        .dbg_stb_i      ( dbg_op[2] ),
573
        .dbg_we_i       ( dbg_op[0] ),
574
 
575
        // Power Management
576
        .pm_clksd_o     ( ),
577
        .pm_cpustall_i  ( 1'b0 ),
578
        .pm_dc_gate_o   ( ),
579
        .pm_ic_gate_o   ( ),
580
        .pm_dmmu_gate_o ( ),
581
        .pm_immu_gate_o ( ),
582
        .pm_tt_gate_o   ( ),
583
        .pm_cpu_gate_o  ( ),
584
        .pm_wakeup_o    ( ),
585
        .pm_lvolt_o     ( ),
586
 
587
        // Interrupts
588
        .pic_ints_i     ( pic_ints )
589
);
590
 
591
//
592
// Startup OR1k
593
//
594
`ifdef START_UP
595
OR1K_startup OR1K_startup0
596
(
597
    .wb_adr_i(wb_fs_adr_i[6:2]),
598
    .wb_stb_i(wb_fs_stb_i),
599
    .wb_cyc_i(wb_fs_cyc_i),
600
    .wb_dat_o(wb_fs_dat_o),
601
    .wb_ack_o(wb_fs_ack_o),
602
    .wb_clk(wb_clk),
603
    .wb_rst(wb_rst)
604
);
605
 
606
spi_flash_top #
607
(
608
   .divider(0),
609
   .divider_len(2)
610
)
611
spi_flash_top0
612
(
613
   .wb_clk_i(wb_clk),
614
   .wb_rst_i(wb_rst),
615
   .wb_adr_i(wb_sp_adr_i[4:2]),
616
   .wb_dat_i(wb_sp_dat_i),
617
   .wb_dat_o(wb_sp_dat_o),
618
   .wb_sel_i(wb_sp_sel_i),
619
   .wb_we_i(wb_sp_we_i),
620
   .wb_stb_i(wb_sp_stb_i),
621
   .wb_cyc_i(wb_sp_cyc_i),
622
   .wb_ack_o(wb_sp_ack_o),
623
 
624
   .mosi_pad_o(spi_flash_mosi),
625
   .miso_pad_i(spi_flash_miso),
626
   .sclk_pad_o(spi_flash_sclk),
627
   .ss_pad_o(spi_flash_ss)
628
);
629
`else
630
assign wb_fs_dat_o = 32'h0000_0000;
631
assign wb_fs_ack_o = 1'b0;
632
assign wb_sp_dat_o = 32'h0000_0000;
633
assign wb_sp_ack_o = 1'b0;
634
`endif
635
 
636
//
637
// Instantiation of the SRAM controller
638
//
639
minsoc_onchip_ram_top #
640
(
641
    .adr_width(`MEMORY_ADR_WIDTH)     //16 blocks of 2048 bytes memory 32768
642
)
643
onchip_ram_top (
644
 
645
        // WISHBONE common
646
        .wb_clk_i       ( wb_clk ),
647
        .wb_rst_i       ( wb_rst ),
648
 
649
        // WISHBONE slave
650
        .wb_dat_i       ( wb_ss_dat_i ),
651
        .wb_dat_o       ( wb_ss_dat_o ),
652
        .wb_adr_i       ( wb_ss_adr_i ),
653
        .wb_sel_i       ( wb_ss_sel_i ),
654
        .wb_we_i        ( wb_ss_we_i  ),
655
        .wb_cyc_i       ( wb_ss_cyc_i ),
656
        .wb_stb_i       ( wb_ss_stb_i ),
657
        .wb_ack_o       ( wb_ss_ack_o ),
658
        .wb_err_o       ( wb_ss_err_o )
659
);
660
 
661
//
662
// Instantiation of the UART16550
663
//
664
`ifdef UART
665
uart_top uart_top (
666
 
667
        // WISHBONE common
668
        .wb_clk_i       ( wb_clk ),
669
        .wb_rst_i       ( wb_rst ),
670
 
671
        // WISHBONE slave
672
        .wb_adr_i       ( wb_us_adr_i[4:0] ),
673
        .wb_dat_i       ( wb_us_dat_i ),
674
        .wb_dat_o       ( wb_us_dat_o ),
675
        .wb_we_i        ( wb_us_we_i  ),
676
        .wb_stb_i       ( wb_us_stb_i ),
677
        .wb_cyc_i       ( wb_us_cyc_i ),
678
        .wb_ack_o       ( wb_us_ack_o ),
679
        .wb_sel_i       ( wb_us_sel_i ),
680
 
681
        // Interrupt request
682
        .int_o          ( pic_ints[`APP_INT_UART] ),
683
 
684
        // UART signals
685
        // serial input/output
686
        .stx_pad_o      ( uart_stx ),
687
        .srx_pad_i      ( uart_srx ),
688
 
689
        // modem signals
690
        .rts_pad_o      ( ),
691
        .cts_pad_i      ( 1'b0 ),
692
        .dtr_pad_o      ( ),
693
        .dsr_pad_i      ( 1'b0 ),
694
        .ri_pad_i       ( 1'b0 ),
695
        .dcd_pad_i      ( 1'b0 )
696
);
697
`else
698
assign wb_us_dat_o = 32'h0000_0000;
699
assign wb_us_ack_o = 1'b0;
700
`endif
701
 
702
//
703
// Instantiation of the Ethernet 10/100 MAC
704
//
705
`ifdef ETHERNET
706
eth_top eth_top (
707
 
708
        // WISHBONE common
709
        .wb_clk_i       ( wb_clk ),
710
        .wb_rst_i       ( wb_rst ),
711
 
712
        // WISHBONE slave
713
        .wb_dat_i       ( wb_es_dat_i ),
714
        .wb_dat_o       ( wb_es_dat_o ),
715
        .wb_adr_i       ( wb_es_adr_i[11:2] ),
716
        .wb_sel_i       ( wb_es_sel_i ),
717
        .wb_we_i        ( wb_es_we_i  ),
718
        .wb_cyc_i       ( wb_es_cyc_i ),
719
        .wb_stb_i       ( wb_es_stb_i ),
720
        .wb_ack_o       ( wb_es_ack_o ),
721
        .wb_err_o       ( wb_es_err_o ),
722
 
723
        // WISHBONE master
724
        .m_wb_adr_o     ( wb_em_adr_o ),
725
        .m_wb_sel_o     ( wb_em_sel_o ),
726
        .m_wb_we_o      ( wb_em_we_o  ),
727
        .m_wb_dat_o     ( wb_em_dat_o ),
728
        .m_wb_dat_i     ( wb_em_dat_i ),
729
        .m_wb_cyc_o     ( wb_em_cyc_o ),
730
        .m_wb_stb_o     ( wb_em_stb_o ),
731
        .m_wb_ack_i     ( wb_em_ack_i ),
732
        .m_wb_err_i     ( wb_em_err_i ),
733
 
734
        // TX
735
        .mtx_clk_pad_i  ( eth_tx_clk ),
736
        .mtxd_pad_o     ( eth_txd ),
737
        .mtxen_pad_o    ( eth_tx_en ),
738
        .mtxerr_pad_o   ( eth_tx_er ),
739
 
740
        // RX
741
        .mrx_clk_pad_i  ( eth_rx_clk ),
742
        .mrxd_pad_i     ( eth_rxd ),
743
        .mrxdv_pad_i    ( eth_rx_dv ),
744
        .mrxerr_pad_i   ( eth_rx_er ),
745
        .mcoll_pad_i    ( eth_col ),
746
        .mcrs_pad_i     ( eth_crs ),
747
 
748
        // MIIM
749
        .mdc_pad_o      ( eth_mdc ),
750
        .md_pad_i       ( eth_mdio ),
751
        .md_pad_o       ( eth_mdo ),
752
        .md_padoe_o     ( eth_mdoe ),
753
 
754
        // Interrupt
755
        .int_o          ( pic_ints[`APP_INT_ETH] )
756
);
757
`else
758
assign wb_es_dat_o = 32'h0000_0000;
759
assign wb_es_ack_o = 1'b0;
760
 
761
assign wb_em_adr_o = 32'h0000_0000;
762
assign wb_em_sel_o = 4'h0;
763
assign wb_em_we_o = 1'b0;
764
assign wb_em_dat_o = 32'h0000_0000;
765
assign wb_em_cyc_o = 1'b0;
766
assign wb_em_stb_o = 1'b0;
767
`endif
768
 
769
//
770
// Instantiation of the Traffic COP
771
//
772
minsoc_tc_top #(`APP_ADDR_DEC_W,
773
         `APP_ADDR_SRAM,
774
         `APP_ADDR_DEC_W,
775
         `APP_ADDR_FLASH,
776
         `APP_ADDR_DECP_W,
777
         `APP_ADDR_PERIP,
778
         `APP_ADDR_DEC_W,
779
         `APP_ADDR_SPI,
780
         `APP_ADDR_ETH,
781
         `APP_ADDR_AUDIO,
782
         `APP_ADDR_UART,
783
         `APP_ADDR_PS2,
784
         `APP_ADDR_RES1,
785
         `APP_ADDR_RES2
786
        ) tc_top (
787
 
788
        // WISHBONE common
789
        .wb_clk_i       ( wb_clk ),
790
        .wb_rst_i       ( wb_rst ),
791
 
792
        // WISHBONE Initiator 0
793
        .i0_wb_cyc_i    ( 1'b0 ),
794
        .i0_wb_stb_i    ( 1'b0 ),
795
        .i0_wb_adr_i    ( 32'h0000_0000 ),
796
        .i0_wb_sel_i    ( 4'b0000 ),
797
        .i0_wb_we_i     ( 1'b0 ),
798
        .i0_wb_dat_i    ( 32'h0000_0000 ),
799
        .i0_wb_dat_o    ( ),
800
        .i0_wb_ack_o    ( ),
801
        .i0_wb_err_o    ( ),
802
 
803
        // WISHBONE Initiator 1
804
        .i1_wb_cyc_i    ( wb_em_cyc_o ),
805
        .i1_wb_stb_i    ( wb_em_stb_o ),
806
        .i1_wb_adr_i    ( wb_em_adr_o ),
807
        .i1_wb_sel_i    ( wb_em_sel_o ),
808
        .i1_wb_we_i     ( wb_em_we_o  ),
809
        .i1_wb_dat_i    ( wb_em_dat_o ),
810
        .i1_wb_dat_o    ( wb_em_dat_i ),
811
        .i1_wb_ack_o    ( wb_em_ack_i ),
812
        .i1_wb_err_o    ( wb_em_err_i ),
813
 
814
        // WISHBONE Initiator 2
815
        .i2_wb_cyc_i    ( 1'b0 ),
816
        .i2_wb_stb_i    ( 1'b0 ),
817
        .i2_wb_adr_i    ( 32'h0000_0000 ),
818
        .i2_wb_sel_i    ( 4'b0000 ),
819
        .i2_wb_we_i     ( 1'b0 ),
820
        .i2_wb_dat_i    ( 32'h0000_0000 ),
821
        .i2_wb_dat_o    ( ),
822
        .i2_wb_ack_o    ( ),
823
        .i2_wb_err_o    ( ),
824
 
825
        // WISHBONE Initiator 3
826
        .i3_wb_cyc_i    ( wb_dm_cyc_o ),
827
        .i3_wb_stb_i    ( wb_dm_stb_o ),
828
        .i3_wb_adr_i    ( wb_dm_adr_o ),
829
        .i3_wb_sel_i    ( wb_dm_sel_o ),
830
        .i3_wb_we_i     ( wb_dm_we_o  ),
831
        .i3_wb_dat_i    ( wb_dm_dat_o ),
832
        .i3_wb_dat_o    ( wb_dm_dat_i ),
833
        .i3_wb_ack_o    ( wb_dm_ack_i ),
834
        .i3_wb_err_o    ( wb_dm_err_i ),
835
 
836
        // WISHBONE Initiator 4
837
        .i4_wb_cyc_i    ( wb_rdm_cyc_o ),
838
        .i4_wb_stb_i    ( wb_rdm_stb_o ),
839
        .i4_wb_adr_i    ( wb_rdm_adr_o ),
840
        .i4_wb_sel_i    ( wb_rdm_sel_o ),
841
        .i4_wb_we_i     ( wb_rdm_we_o  ),
842
        .i4_wb_dat_i    ( wb_rdm_dat_o ),
843
        .i4_wb_dat_o    ( wb_rdm_dat_i ),
844
        .i4_wb_ack_o    ( wb_rdm_ack_i ),
845
        .i4_wb_err_o    ( wb_rdm_err_i ),
846
 
847
        // WISHBONE Initiator 5
848
        .i5_wb_cyc_i    ( wb_rim_cyc_o ),
849
        .i5_wb_stb_i    ( wb_rim_stb_o ),
850
        .i5_wb_adr_i    ( wb_rim_adr_o ),
851
        .i5_wb_sel_i    ( wb_rim_sel_o ),
852
        .i5_wb_we_i     ( wb_rim_we_o  ),
853
        .i5_wb_dat_i    ( wb_rim_dat_o ),
854
        .i5_wb_dat_o    ( wb_rim_dat_i ),
855
        .i5_wb_ack_o    ( wb_rim_ack_i ),
856
        .i5_wb_err_o    ( wb_rim_err_i ),
857
 
858
        // WISHBONE Initiator 6
859
        .i6_wb_cyc_i    ( 1'b0 ),
860
        .i6_wb_stb_i    ( 1'b0 ),
861
        .i6_wb_adr_i    ( 32'h0000_0000 ),
862
        .i6_wb_sel_i    ( 4'b0000 ),
863
        .i6_wb_we_i     ( 1'b0 ),
864
        .i6_wb_dat_i    ( 32'h0000_0000 ),
865
        .i6_wb_dat_o    ( ),
866
        .i6_wb_ack_o    ( ),
867
        .i6_wb_err_o    ( ),
868
 
869
        // WISHBONE Initiator 7
870
        .i7_wb_cyc_i    ( 1'b0 ),
871
        .i7_wb_stb_i    ( 1'b0 ),
872
        .i7_wb_adr_i    ( 32'h0000_0000 ),
873
        .i7_wb_sel_i    ( 4'b0000 ),
874
        .i7_wb_we_i     ( 1'b0 ),
875
        .i7_wb_dat_i    ( 32'h0000_0000 ),
876
        .i7_wb_dat_o    ( ),
877
        .i7_wb_ack_o    ( ),
878
        .i7_wb_err_o    ( ),
879
 
880
        // WISHBONE Target 0
881
        .t0_wb_cyc_o    ( wb_ss_cyc_i ),
882
        .t0_wb_stb_o    ( wb_ss_stb_i ),
883
        .t0_wb_adr_o    ( wb_ss_adr_i ),
884
        .t0_wb_sel_o    ( wb_ss_sel_i ),
885
        .t0_wb_we_o     ( wb_ss_we_i  ),
886
        .t0_wb_dat_o    ( wb_ss_dat_i ),
887
        .t0_wb_dat_i    ( wb_ss_dat_o ),
888
        .t0_wb_ack_i    ( wb_ss_ack_o ),
889
        .t0_wb_err_i    ( wb_ss_err_o ),
890
 
891
        // WISHBONE Target 1
892
        .t1_wb_cyc_o    ( wb_fs_cyc_i ),
893
        .t1_wb_stb_o    ( wb_fs_stb_i ),
894
        .t1_wb_adr_o    ( wb_fs_adr_i ),
895
        .t1_wb_sel_o    ( wb_fs_sel_i ),
896
        .t1_wb_we_o     ( wb_fs_we_i  ),
897
        .t1_wb_dat_o    ( wb_fs_dat_i ),
898
        .t1_wb_dat_i    ( wb_fs_dat_o ),
899
        .t1_wb_ack_i    ( wb_fs_ack_o ),
900
        .t1_wb_err_i    ( wb_fs_err_o ),
901
 
902
        // WISHBONE Target 2
903
        .t2_wb_cyc_o    ( wb_sp_cyc_i ),
904
        .t2_wb_stb_o    ( wb_sp_stb_i ),
905
        .t2_wb_adr_o    ( wb_sp_adr_i ),
906
        .t2_wb_sel_o    ( wb_sp_sel_i ),
907
        .t2_wb_we_o     ( wb_sp_we_i  ),
908
        .t2_wb_dat_o    ( wb_sp_dat_i ),
909
        .t2_wb_dat_i    ( wb_sp_dat_o ),
910
        .t2_wb_ack_i    ( wb_sp_ack_o ),
911
        .t2_wb_err_i    ( wb_sp_err_o ),
912
 
913
        // WISHBONE Target 3
914
        .t3_wb_cyc_o    ( wb_es_cyc_i ),
915
        .t3_wb_stb_o    ( wb_es_stb_i ),
916
        .t3_wb_adr_o    ( wb_es_adr_i ),
917
        .t3_wb_sel_o    ( wb_es_sel_i ),
918
        .t3_wb_we_o     ( wb_es_we_i  ),
919
        .t3_wb_dat_o    ( wb_es_dat_i ),
920
        .t3_wb_dat_i    ( wb_es_dat_o ),
921
        .t3_wb_ack_i    ( wb_es_ack_o ),
922
        .t3_wb_err_i    ( wb_es_err_o ),
923
 
924
        // WISHBONE Target 4
925
        .t4_wb_cyc_o    ( ),
926
        .t4_wb_stb_o    ( ),
927
        .t4_wb_adr_o    ( ),
928
        .t4_wb_sel_o    ( ),
929
        .t4_wb_we_o     ( ),
930
        .t4_wb_dat_o    ( ),
931
        .t4_wb_dat_i    ( 32'h0000_0000 ),
932
        .t4_wb_ack_i    ( 1'b0 ),
933
        .t4_wb_err_i    ( 1'b1 ),
934
 
935
        // WISHBONE Target 5
936
        .t5_wb_cyc_o    ( wb_us_cyc_i ),
937
        .t5_wb_stb_o    ( wb_us_stb_i ),
938
        .t5_wb_adr_o    ( wb_us_adr_i ),
939
        .t5_wb_sel_o    ( wb_us_sel_i ),
940
        .t5_wb_we_o     ( wb_us_we_i  ),
941
        .t5_wb_dat_o    ( wb_us_dat_i ),
942
        .t5_wb_dat_i    ( wb_us_dat_o ),
943
        .t5_wb_ack_i    ( wb_us_ack_o ),
944
        .t5_wb_err_i    ( wb_us_err_o ),
945
 
946
        // WISHBONE Target 6
947
        .t6_wb_cyc_o    ( ),
948
        .t6_wb_stb_o    ( ),
949
        .t6_wb_adr_o    ( ),
950
        .t6_wb_sel_o    ( ),
951
        .t6_wb_we_o     ( ),
952
        .t6_wb_dat_o    ( ),
953
        .t6_wb_dat_i    ( 32'h0000_0000 ),
954
        .t6_wb_ack_i    ( 1'b0 ),
955
        .t6_wb_err_i    ( 1'b1 ),
956
 
957
        // WISHBONE Target 7
958
        .t7_wb_cyc_o    ( ),
959
        .t7_wb_stb_o    ( ),
960
        .t7_wb_adr_o    ( ),
961
        .t7_wb_sel_o    ( ),
962
        .t7_wb_we_o     ( ),
963
        .t7_wb_dat_o    ( ),
964
        .t7_wb_dat_i    ( 32'h0000_0000 ),
965
        .t7_wb_ack_i    ( 1'b0 ),
966
        .t7_wb_err_i    ( 1'b1 ),
967
 
968
        // WISHBONE Target 8
969
        .t8_wb_cyc_o    ( ),
970
        .t8_wb_stb_o    ( ),
971
        .t8_wb_adr_o    ( ),
972
        .t8_wb_sel_o    ( ),
973
        .t8_wb_we_o     ( ),
974
        .t8_wb_dat_o    ( ),
975
        .t8_wb_dat_i    ( 32'h0000_0000 ),
976
        .t8_wb_ack_i    ( 1'b0 ),
977
        .t8_wb_err_i    ( 1'b1 )
978
);
979
 
980
//initial begin
981
//  $dumpvars(0);
982
//  $dumpfile("dump.vcd");
983
//end
984
 
985
endmodule

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