1 |
2 |
rfajardo |
///////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// xilinx_internal_jtag.v ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// ////
|
6 |
|
|
//// ////
|
7 |
|
|
//// Author(s): ////
|
8 |
|
|
//// Nathan Yawn (nathan.yawn@opencores.org) ////
|
9 |
|
|
//// ////
|
10 |
|
|
//// ////
|
11 |
|
|
//// ////
|
12 |
|
|
//////////////////////////////////////////////////////////////////////
|
13 |
|
|
//// ////
|
14 |
|
|
//// Copyright (C) 2008 Authors ////
|
15 |
|
|
//// ////
|
16 |
|
|
//// This source file may be used and distributed without ////
|
17 |
|
|
//// restriction provided that this copyright statement is not ////
|
18 |
|
|
//// removed from the file and that any derivative work contains ////
|
19 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
20 |
|
|
//// ////
|
21 |
|
|
//// This source file is free software; you can redistribute it ////
|
22 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
23 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
24 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
25 |
|
|
//// later version. ////
|
26 |
|
|
//// ////
|
27 |
|
|
//// This source is distributed in the hope that it will be ////
|
28 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
29 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
30 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
31 |
|
|
//// details. ////
|
32 |
|
|
//// ////
|
33 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
34 |
|
|
//// Public License along with this source; if not, download it ////
|
35 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
36 |
|
|
//// ////
|
37 |
|
|
//////////////////////////////////////////////////////////////////////
|
38 |
|
|
// //
|
39 |
|
|
// This file is a wrapper for the various Xilinx internal BSCAN //
|
40 |
|
|
// TAP devices. It is designed to take the place of a separate TAP //
|
41 |
|
|
// controller in Xilinx systems, to allow a user to access a CPU //
|
42 |
|
|
// debug module (such as that of the OR1200) through the FPGA's //
|
43 |
|
|
// dedicated JTAG / configuration port. //
|
44 |
|
|
// //
|
45 |
|
|
//////////////////////////////////////////////////////////////////////
|
46 |
|
|
//
|
47 |
|
|
// CVS Revision History
|
48 |
|
|
//
|
49 |
|
|
// $Log: xilinx_internal_jtag.v,v $
|
50 |
|
|
// Revision 1.3 2009/06/16 02:54:23 Nathan
|
51 |
|
|
// Changed some signal names for better consistency between different hardware modules.
|
52 |
|
|
//
|
53 |
|
|
// Revision 1.2 2009/05/17 20:54:16 Nathan
|
54 |
|
|
// Changed email address to opencores.org
|
55 |
|
|
//
|
56 |
|
|
// Revision 1.1 2008/07/18 20:07:32 Nathan
|
57 |
|
|
// Changed the directory structure to match existing projects.
|
58 |
|
|
//
|
59 |
|
|
// Revision 1.4 2008/07/11 08:26:10 Nathan
|
60 |
|
|
// Ran through dos2unix
|
61 |
|
|
//
|
62 |
|
|
// Revision 1.3 2008/07/11 08:25:52 Nathan
|
63 |
|
|
// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted. Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it. Tested successfully with the adv_dbg_if on Virtex-4.
|
64 |
|
|
//
|
65 |
|
|
// Revision 1.2 2008/06/09 19:34:14 Nathan
|
66 |
|
|
// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools.
|
67 |
|
|
//
|
68 |
|
|
// Revision 1.1 2008/05/22 19:54:07 Nathan
|
69 |
|
|
// Initial version
|
70 |
|
|
//
|
71 |
|
|
|
72 |
|
|
|
73 |
|
|
`include "minsoc_defines.v"
|
74 |
|
|
|
75 |
|
|
// Note that the SPARTAN BSCAN controllers have more than one channel.
|
76 |
|
|
// This implementation always uses channel 1, this is not configurable.
|
77 |
|
|
// If you want to use another channel, then it is probably because you
|
78 |
|
|
// want to attach multiple devices to the BSCAN device, which means
|
79 |
|
|
// you'll be making changes to this file anyway.
|
80 |
|
|
// Virtex BSCAN devices are instantiated separately for each channel.
|
81 |
|
|
// To select something other than the default (1), change the parameter
|
82 |
|
|
// "virtex_jtag_chain".
|
83 |
|
|
|
84 |
|
|
|
85 |
|
|
module minsoc_xilinx_internal_jtag (
|
86 |
|
|
tck_o,
|
87 |
|
|
debug_tdo_i,
|
88 |
|
|
tdi_o,
|
89 |
|
|
test_logic_reset_o,
|
90 |
|
|
run_test_idle_o,
|
91 |
|
|
shift_dr_o,
|
92 |
|
|
capture_dr_o,
|
93 |
|
|
pause_dr_o,
|
94 |
|
|
update_dr_o,
|
95 |
|
|
debug_select_o
|
96 |
|
|
);
|
97 |
|
|
|
98 |
|
|
// May be 1, 2, 3, or 4
|
99 |
|
|
// Only used for Virtex 4/5 devices
|
100 |
|
|
parameter virtex_jtag_chain = 1;
|
101 |
|
|
|
102 |
|
|
input debug_tdo_i;
|
103 |
|
|
output tck_o;
|
104 |
|
|
output tdi_o;
|
105 |
|
|
output test_logic_reset_o;
|
106 |
|
|
output run_test_idle_o;
|
107 |
|
|
output shift_dr_o;
|
108 |
|
|
output capture_dr_o;
|
109 |
|
|
output pause_dr_o;
|
110 |
|
|
output update_dr_o;
|
111 |
|
|
output debug_select_o;
|
112 |
|
|
|
113 |
|
|
wire debug_tdo_i;
|
114 |
|
|
wire tck_o;
|
115 |
|
|
wire drck;
|
116 |
|
|
wire tdi_o;
|
117 |
|
|
wire test_logic_reset_o;
|
118 |
|
|
wire run_test_idle_o;
|
119 |
|
|
wire shift_dr_o;
|
120 |
|
|
wire pause_dr_o;
|
121 |
|
|
wire update_dr_o;
|
122 |
|
|
wire debug_select_o;
|
123 |
|
|
|
124 |
|
|
`ifdef SPARTAN3E
|
125 |
|
|
`define SPARTAN3
|
126 |
|
|
`endif
|
127 |
|
|
|
128 |
|
|
`ifdef SPARTAN2
|
129 |
|
|
|
130 |
|
|
// Note that this version is missing three outputs.
|
131 |
|
|
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected
|
132 |
|
|
// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no
|
133 |
|
|
// capture_dr output.
|
134 |
|
|
|
135 |
|
|
reg capture_dr_o;
|
136 |
|
|
wire update_bscan;
|
137 |
|
|
reg update_out;
|
138 |
|
|
|
139 |
|
|
BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
|
140 |
|
|
.DRCK1(drck), // Data register output for USER1 functions
|
141 |
|
|
.DRCK2(), // Data register output for USER2 functions
|
142 |
|
|
.RESET(test_logic_reset_o), // Reset output from TAP controller
|
143 |
|
|
.SEL1(debug_select_o), // USER1 active output
|
144 |
|
|
.SEL2(), // USER2 active output
|
145 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
146 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
147 |
|
|
.UPDATE(update_bscan), // UPDATE output from TAP controller
|
148 |
|
|
.TDO1(debug_tdo_i), // Data input for USER1 function
|
149 |
|
|
.TDO2( 1'b0 ) // Data input for USER2 function
|
150 |
|
|
);
|
151 |
|
|
|
152 |
|
|
assign pause_dr_o = 1'b0;
|
153 |
|
|
assign run_test_idle_o = 1'b0;
|
154 |
|
|
|
155 |
|
|
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high)
|
156 |
|
|
// On that negative edge, set capture_dr, and it will get registered on the rising
|
157 |
|
|
// edge.
|
158 |
|
|
always @ (negedge tck_o)
|
159 |
|
|
begin
|
160 |
|
|
if(debug_select_o && !shift_dr_o)
|
161 |
|
|
capture_dr_o <= 1'b1;
|
162 |
|
|
else
|
163 |
|
|
capture_dr_o <= 1'b0;
|
164 |
|
|
end
|
165 |
|
|
|
166 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
167 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
168 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
169 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
170 |
|
|
|
171 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
172 |
|
|
// of the clock created above.
|
173 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
174 |
|
|
begin
|
175 |
|
|
if(update_bscan) update_out <= 1'b1;
|
176 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
177 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
178 |
|
|
end
|
179 |
|
|
|
180 |
|
|
assign update_dr_o = update_out;
|
181 |
|
|
|
182 |
|
|
`else
|
183 |
|
|
`ifdef SPARTAN3
|
184 |
|
|
// Note that this version is missing two outputs.
|
185 |
|
|
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
|
186 |
|
|
|
187 |
|
|
wire capture_dr_o;
|
188 |
|
|
wire update_bscan;
|
189 |
|
|
reg update_out;
|
190 |
|
|
|
191 |
|
|
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
|
192 |
|
|
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
|
193 |
|
|
.DRCK1(drck), // Data register output for USER1 functions
|
194 |
|
|
.DRCK2(), // Data register output for USER2 functions
|
195 |
|
|
.RESET(test_logic_reset_o), // Reset output from TAP controller
|
196 |
|
|
.SEL1(debug_select_o), // USER1 active output
|
197 |
|
|
.SEL2(), // USER2 active output
|
198 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
199 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
200 |
|
|
.UPDATE(update_bscan), // UPDATE output from TAP controller
|
201 |
|
|
.TDO1(debug_tdo_i), // Data input for USER1 function
|
202 |
|
|
.TDO2(1'b0) // Data input for USER2 function
|
203 |
|
|
);
|
204 |
|
|
|
205 |
|
|
assign pause_dr_o = 1'b0;
|
206 |
|
|
assign run_test_idle_o = 1'b0;
|
207 |
|
|
|
208 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
209 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
210 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
211 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
212 |
|
|
|
213 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
214 |
|
|
// of the clock created above.
|
215 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
216 |
|
|
begin
|
217 |
|
|
if(update_bscan) update_out <= 1'b1;
|
218 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
219 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
220 |
|
|
end
|
221 |
|
|
|
222 |
|
|
assign update_dr_o = update_out;
|
223 |
|
|
|
224 |
|
|
`ifdef SPARTAN3E
|
225 |
|
|
`undef SPARTAN3
|
226 |
|
|
`endif
|
227 |
|
|
|
228 |
|
|
`else
|
229 |
|
|
`ifdef SPARTAN3A
|
230 |
|
|
// Note that this version is missing two outputs.
|
231 |
|
|
// At least it has a real TCK.
|
232 |
|
|
|
233 |
|
|
wire capture_dr_o;
|
234 |
|
|
|
235 |
|
|
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
|
236 |
|
|
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
|
237 |
|
|
.DRCK1(), // Data register output for USER1 functions
|
238 |
|
|
.DRCK2(), // Data register output for USER2 functions
|
239 |
|
|
.RESET(test_logic_reset_o), // Reset output from TAP controller
|
240 |
|
|
.SEL1(debug_select_o), // USER1 active output
|
241 |
|
|
.SEL2(), // USER2 active output
|
242 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
243 |
|
|
.TCK(tck_o), // TCK output from TAP controller
|
244 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
245 |
|
|
.TMS(), // TMS output from TAP controller
|
246 |
|
|
.UPDATE(update_dr_o), // UPDATE output from TAP controller
|
247 |
|
|
.TDO1(debug_tdo_i), // Data input for USER1 function
|
248 |
|
|
.TDO2( 1'b0) // Data input for USER2 function
|
249 |
|
|
);
|
250 |
|
|
|
251 |
|
|
assign pause_dr_o = 1'b0;
|
252 |
|
|
assign run_test_idle_o = 1'b0;
|
253 |
|
|
|
254 |
173 |
rfajardo |
|
255 |
|
|
|
256 |
|
|
//-----------------------------------------------------------------------
|
257 |
2 |
rfajardo |
`else
|
258 |
173 |
rfajardo |
`ifdef SPARTAN6
|
259 |
|
|
|
260 |
|
|
wire capture_dr_o;
|
261 |
|
|
|
262 |
|
|
BSCAN_SPARTAN6 #(
|
263 |
|
|
.JTAG_CHAIN(1) // Chain number.
|
264 |
|
|
)
|
265 |
|
|
BSCAN_SPARTAN6_inst (
|
266 |
|
|
.CAPTURE(capture_dr_o), // 1-bit Scan Data Register Capture instruction.
|
267 |
|
|
.DRCK(drck), // 1-bit Scan Clock instruction. DRCK is a gated version of TCTCK, it toggles during the CAPTUREDR and SHIFTDR states.
|
268 |
|
|
.RESET(test_logic_reset_o), // 1-bit Scan register reset instruction.
|
269 |
|
|
.RUNTEST(), // 1-bit Asserted when TAP controller is in Run Test Idle state. Make sure is the same name as BSCAN primitive used in Spartan products.
|
270 |
|
|
.SEL(debug_select_o), // 1-bit Scan mode Select instruction.
|
271 |
|
|
.SHIFT(shift_dr_o), // 1-bit Scan Chain Shift instruction.
|
272 |
|
|
.TCK(tck_o), // 1-bit Scan Clock. Fabric connection to TAP Clock pin.
|
273 |
|
|
.TDI(tdi_o), // 1-bit Scan Chain Output. Mirror of TDI input pin to FPGA.
|
274 |
|
|
.TMS(), // 1-bit Test Mode Select. Fabric connection to TAP.
|
275 |
|
|
.UPDATE(update_dr_o), // 1-bit Scan Register Update instruction.
|
276 |
|
|
.TDO(debug_tdo_i) // 1-bit Scan Chain Input.
|
277 |
|
|
);
|
278 |
|
|
// End of BSCAN_SPARTAN6_inst instantiation
|
279 |
|
|
|
280 |
|
|
assign pause_dr_o = 1'b0;
|
281 |
|
|
assign run_test_idle_o = 1'b0;
|
282 |
|
|
|
283 |
|
|
|
284 |
|
|
|
285 |
|
|
|
286 |
|
|
`else
|
287 |
2 |
rfajardo |
`ifdef VIRTEX
|
288 |
|
|
|
289 |
|
|
// Note that this version is missing three outputs.
|
290 |
|
|
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
|
291 |
|
|
|
292 |
|
|
reg capture_dr_o;
|
293 |
|
|
wire update_bscan;
|
294 |
|
|
reg update_out;
|
295 |
|
|
|
296 |
|
|
BSCAN_VIRTEX BSCAN_VIRTEX_inst (
|
297 |
|
|
.DRCK1(drck), // Data register output for USER1 functions
|
298 |
|
|
.DRCK2(), // Data register output for USER2 functions
|
299 |
|
|
.RESET(test_logic_reset_o), // Reset output from TAP controller
|
300 |
|
|
.SEL1(debug_select_o), // USER1 active output
|
301 |
|
|
.SEL2(), // USER2 active output
|
302 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
303 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
304 |
|
|
.UPDATE(update_bscan), // UPDATE output from TAP controller
|
305 |
|
|
.TDO1(debug_tdo_i), // Data input for USER1 function
|
306 |
|
|
.TDO2( 1'b0) // Data input for USER2 function
|
307 |
|
|
);
|
308 |
|
|
|
309 |
|
|
assign pause_dr_o = 1'b0;
|
310 |
|
|
assign run_test_idle_o = 1'b0;
|
311 |
|
|
|
312 |
|
|
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low)
|
313 |
|
|
// On that negative edge, set capture_dr, and it will get registered on the rising
|
314 |
|
|
// edge, then de-asserted on the same edge that SHIFT goes high.
|
315 |
|
|
always @ (negedge tck_o)
|
316 |
|
|
begin
|
317 |
|
|
if(debug_select_o && !shift_dr_o)
|
318 |
|
|
capture_dr_o <= 1'b1;
|
319 |
|
|
else
|
320 |
|
|
capture_dr_o <= 1'b0;
|
321 |
|
|
end
|
322 |
|
|
|
323 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
324 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
325 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
326 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
327 |
|
|
|
328 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
329 |
|
|
// of the clock created above.
|
330 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
331 |
|
|
begin
|
332 |
|
|
if(update_bscan) update_out <= 1'b1;
|
333 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
334 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
335 |
|
|
end
|
336 |
|
|
|
337 |
|
|
assign update_dr_o = update_out;
|
338 |
|
|
|
339 |
|
|
`else
|
340 |
|
|
`ifdef VIRTEX2
|
341 |
|
|
|
342 |
|
|
// Note that this version is missing two outputs.
|
343 |
|
|
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
|
344 |
|
|
|
345 |
|
|
wire capture_dr_o;
|
346 |
|
|
wire update_bscan;
|
347 |
|
|
reg update_out;
|
348 |
|
|
|
349 |
|
|
BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
|
350 |
|
|
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
|
351 |
|
|
.DRCK1(drck), // Data register output for USER1 functions
|
352 |
|
|
.DRCK2(), // Data register output for USER2 functions
|
353 |
|
|
.RESET(test_logic_reset_o), // Reset output from TAP controller
|
354 |
|
|
.SEL1(debug_select_o), // USER1 active output
|
355 |
|
|
.SEL2(), // USER2 active output
|
356 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
357 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
358 |
|
|
.UPDATE(update_bscan), // UPDATE output from TAP controller
|
359 |
|
|
.TDO1(debug_tdo_i), // Data input for USER1 function
|
360 |
|
|
.TDO2( 1'b0 ) // Data input for USER2 function
|
361 |
|
|
);
|
362 |
|
|
|
363 |
|
|
assign pause_dr_o = 1'b0;
|
364 |
|
|
assign run_test_idle_o = 1'b0;
|
365 |
|
|
|
366 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
367 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
368 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
369 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
370 |
|
|
|
371 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
372 |
|
|
// of the clock created above.
|
373 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
374 |
|
|
begin
|
375 |
|
|
if(update_bscan) update_out <= 1'b1;
|
376 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
377 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
378 |
|
|
end
|
379 |
|
|
|
380 |
|
|
assign update_dr_o = update_out;
|
381 |
|
|
|
382 |
|
|
`else
|
383 |
|
|
`ifdef VIRTEX4
|
384 |
|
|
// Note that this version is missing two outputs.
|
385 |
|
|
// It also does not have a real TCK...DRCK is only active when USERn is selected.
|
386 |
|
|
|
387 |
|
|
wire capture_dr_o;
|
388 |
|
|
wire update_bscan;
|
389 |
|
|
reg update_out;
|
390 |
|
|
|
391 |
|
|
BSCAN_VIRTEX4 #(
|
392 |
|
|
.JTAG_CHAIN(virtex_jtag_chain)
|
393 |
|
|
) BSCAN_VIRTEX4_inst (
|
394 |
|
|
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
|
395 |
|
|
.DRCK(drck), // Data register output for USER function
|
396 |
|
|
.RESET(test_logic_reset_o), // Reset output from TAP controller
|
397 |
|
|
.SEL(debug_select_o), // USER active output
|
398 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
399 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
400 |
|
|
.UPDATE(update_bscan), // UPDATE output from TAP controller
|
401 |
|
|
.TDO( debug_tdo_i ) // Data input for USER function
|
402 |
|
|
);
|
403 |
|
|
|
404 |
|
|
assign pause_dr_o = 1'b0;
|
405 |
|
|
assign run_test_idle_o = 1'b0;
|
406 |
|
|
|
407 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
408 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
409 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
410 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
411 |
|
|
|
412 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
413 |
|
|
// of the clock created above.
|
414 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
415 |
|
|
begin
|
416 |
|
|
if(update_bscan) update_out <= 1'b1;
|
417 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
418 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
419 |
|
|
end
|
420 |
|
|
|
421 |
|
|
assign update_dr_o = update_out;
|
422 |
|
|
|
423 |
|
|
`else
|
424 |
|
|
`ifdef VIRTEX5
|
425 |
|
|
// Note that this version is missing two outputs.
|
426 |
|
|
// It also does not have a real TCK...DRCK is only active when USERn is selected.
|
427 |
|
|
|
428 |
|
|
wire capture_dr_o;
|
429 |
|
|
wire update_bscan;
|
430 |
|
|
reg update_out;
|
431 |
|
|
|
432 |
|
|
BSCAN_VIRTEX5 #(
|
433 |
|
|
.JTAG_CHAIN(virtex_jtag_chain)
|
434 |
|
|
) BSCAN_VIRTEX5_inst (
|
435 |
|
|
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
|
436 |
|
|
.DRCK(drck), // Data register output for USER function
|
437 |
|
|
.RESET(test_logic_reset), // Reset output from TAP controller
|
438 |
|
|
.SEL(debug_select_o), // USER active output
|
439 |
|
|
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
|
440 |
|
|
.TDI(tdi_o), // TDI output from TAP controller
|
441 |
|
|
.UPDATE(update_bscan), // UPDATE output from TAP controller
|
442 |
|
|
.TDO(debug_tdo_i) // Data input for USER function
|
443 |
|
|
);
|
444 |
|
|
|
445 |
|
|
assign pause_dr_o = 1'b0;
|
446 |
|
|
assign run_test_idle_o = 1'b0;
|
447 |
|
|
|
448 |
|
|
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
|
449 |
|
|
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
|
450 |
|
|
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
|
451 |
|
|
assign tck_o = (drck & debug_select_o & !update_bscan);
|
452 |
|
|
|
453 |
|
|
// This will hold the update_dr output so it can be registered on the rising edge
|
454 |
|
|
// of the clock created above.
|
455 |
|
|
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
|
456 |
|
|
begin
|
457 |
|
|
if(update_bscan) update_out <= 1'b1;
|
458 |
|
|
else if(capture_dr_o) update_out <= 1'b0;
|
459 |
|
|
else if(!debug_select_o) update_out <= 1'b0;
|
460 |
|
|
end
|
461 |
|
|
|
462 |
|
|
assign update_dr_o = update_out;
|
463 |
|
|
|
464 |
|
|
|
465 |
|
|
`endif
|
466 |
|
|
`endif
|
467 |
|
|
`endif
|
468 |
|
|
`endif
|
469 |
|
|
`endif
|
470 |
|
|
`endif
|
471 |
173 |
rfajardo |
`endif // !`ifdef SPARTAN3
|
472 |
|
|
`endif // !`ifdef SPARTAN2
|
473 |
2 |
rfajardo |
`endif
|
474 |
|
|
|
475 |
|
|
endmodule
|