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///////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  xilinx_internal_jtag.v                                      ////
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////                                                              ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Nathan Yawn (nathan.yawn@opencores.org)                ////
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////                                                              ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//                                                                  //
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// This file is a wrapper for the various Xilinx internal BSCAN     //
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// TAP devices.  It is designed to take the place of a separate TAP //
41
// controller in Xilinx systems, to allow a user to access a CPU    //
42
// debug module (such as that of the OR1200) through the FPGA's     //
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// dedicated JTAG / configuration port.                             //
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//                                                                  //
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//////////////////////////////////////////////////////////////////////
46
//
47
// CVS Revision History
48
//
49
// $Log: xilinx_internal_jtag.v,v $
50
// Revision 1.3  2009/06/16 02:54:23  Nathan
51
// Changed some signal names for better consistency between different hardware modules.
52
//
53
// Revision 1.2  2009/05/17 20:54:16  Nathan
54
// Changed email address to opencores.org
55
//
56
// Revision 1.1  2008/07/18 20:07:32  Nathan
57
// Changed the directory structure to match existing projects.
58
//
59
// Revision 1.4  2008/07/11 08:26:10  Nathan
60
// Ran through dos2unix
61
//
62
// Revision 1.3  2008/07/11 08:25:52  Nathan
63
// Added logic to provide CAPTURE_DR signal when necessary, and to provide a TCK while UPDATE_DR is asserted.  Note that there is no TCK event between SHIFT_DR and UPDATE_DR, and no TCK event between UPDATE_DR and the next CAPTURE_DR; the Xilinx BSCAN devices do not provide it.  Tested successfully with the adv_dbg_if on Virtex-4.
64
//
65
// Revision 1.2  2008/06/09 19:34:14  Nathan
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// Syntax and functional fixes made after compiling each type of BSCAN module using Xilinx tools.
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//
68
// Revision 1.1  2008/05/22 19:54:07  Nathan
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// Initial version
70
//
71
 
72
 
73
`include "minsoc_defines.v"
74
 
75
// Note that the SPARTAN BSCAN controllers have more than one channel.
76
// This implementation always uses channel 1, this is not configurable.
77
// If you want to use another channel, then it is probably because you
78
// want to attach multiple devices to the BSCAN device, which means
79
// you'll be making changes to this file anyway.
80
// Virtex BSCAN devices are instantiated separately for each channel.
81
// To select something other than the default (1), change the parameter
82
// "virtex_jtag_chain".
83
 
84
 
85
module minsoc_xilinx_internal_jtag (
86
        tck_o,
87
        debug_tdo_i,
88
        tdi_o,
89
        test_logic_reset_o,
90
        run_test_idle_o,
91
        shift_dr_o,
92
        capture_dr_o,
93
        pause_dr_o,
94
        update_dr_o,
95
        debug_select_o
96
);
97
 
98
// May be 1, 2, 3, or 4
99
// Only used for Virtex 4/5 devices
100
parameter virtex_jtag_chain = 1;
101
 
102
input debug_tdo_i;
103
output tck_o;
104
output tdi_o;
105
output test_logic_reset_o;
106
output run_test_idle_o;
107
output shift_dr_o;
108
output capture_dr_o;
109
output pause_dr_o;
110
output update_dr_o;
111
output debug_select_o;
112
 
113
wire debug_tdo_i;
114
wire tck_o;
115
wire drck;
116
wire tdi_o;
117
wire test_logic_reset_o;
118
wire run_test_idle_o;
119
wire shift_dr_o;
120
wire pause_dr_o;
121
wire update_dr_o;
122
wire debug_select_o;
123
 
124
`ifdef SPARTAN3E
125
        `define SPARTAN3
126
`endif
127
 
128
`ifdef SPARTAN2
129
 
130
// Note that this version is missing three outputs.
131
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected
132
// AND the TAP is in SHIFT_DR or CAPTURE_DR states...except there's no
133
// capture_dr output. 
134
 
135
reg capture_dr_o;
136
wire update_bscan;
137
reg update_out;
138
 
139
BSCAN_SPARTAN2 BSCAN_SPARTAN2_inst (
140
.DRCK1(drck), // Data register output for USER1 functions
141
.DRCK2(), // Data register output for USER2 functions
142
.RESET(test_logic_reset_o), // Reset output from TAP controller
143
.SEL1(debug_select_o), // USER1 active output
144
.SEL2(), // USER2 active output
145
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
146
.TDI(tdi_o), // TDI output from TAP controller
147
.UPDATE(update_bscan), // UPDATE output from TAP controller
148
.TDO1(debug_tdo_i), // Data input for USER1 function
149
.TDO2( 1'b0 ) // Data input for USER2 function
150
);
151
 
152
assign pause_dr_o = 1'b0;
153
assign run_test_idle_o = 1'b0;
154
 
155
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK high)
156
// On that negative edge, set capture_dr, and it will get registered on the rising
157
// edge.
158
always @ (negedge tck_o)
159
begin
160
        if(debug_select_o && !shift_dr_o)
161
                capture_dr_o <= 1'b1;
162
        else
163
                capture_dr_o <= 1'b0;
164
end
165
 
166
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
167
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
168
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
169
assign tck_o = (drck & debug_select_o & !update_bscan);
170
 
171
// This will hold the update_dr output so it can be registered on the rising edge
172
// of the clock created above.
173
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
174
begin
175
        if(update_bscan) update_out <= 1'b1;
176
        else if(capture_dr_o) update_out <= 1'b0;
177
        else if(!debug_select_o) update_out <= 1'b0;
178
end
179
 
180
assign update_dr_o = update_out;
181
 
182
`else
183
`ifdef SPARTAN3
184
// Note that this version is missing two outputs.
185
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
186
 
187
wire capture_dr_o;
188
wire update_bscan;
189
reg update_out;
190
 
191
BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst (
192
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
193
.DRCK1(drck), // Data register output for USER1 functions
194
.DRCK2(), // Data register output for USER2 functions
195
.RESET(test_logic_reset_o), // Reset output from TAP controller
196
.SEL1(debug_select_o), // USER1 active output
197
.SEL2(), // USER2 active output
198
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
199
.TDI(tdi_o), // TDI output from TAP controller
200
.UPDATE(update_bscan), // UPDATE output from TAP controller
201
.TDO1(debug_tdo_i), // Data input for USER1 function
202
.TDO2(1'b0) // Data input for USER2 function
203
);
204
 
205
assign pause_dr_o = 1'b0;
206
assign run_test_idle_o = 1'b0;
207
 
208
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
209
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
210
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
211
assign tck_o = (drck & debug_select_o & !update_bscan);
212
 
213
// This will hold the update_dr output so it can be registered on the rising edge
214
// of the clock created above.
215
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
216
begin
217
        if(update_bscan) update_out <= 1'b1;
218
        else if(capture_dr_o) update_out <= 1'b0;
219
        else if(!debug_select_o) update_out <= 1'b0;
220
end
221
 
222
assign update_dr_o = update_out;
223
 
224
`ifdef SPARTAN3E
225
        `undef SPARTAN3
226
`endif
227
 
228
`else
229
`ifdef SPARTAN3A
230
// Note that this version is missing two outputs.
231
// At least it has a real TCK.
232
 
233
wire capture_dr_o;
234
 
235
BSCAN_SPARTAN3A BSCAN_SPARTAN3A_inst (
236
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
237
.DRCK1(), // Data register output for USER1 functions
238
.DRCK2(), // Data register output for USER2 functions
239
.RESET(test_logic_reset_o), // Reset output from TAP controller
240
.SEL1(debug_select_o), // USER1 active output
241
.SEL2(), // USER2 active output
242
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
243
.TCK(tck_o), // TCK output from TAP controller
244
.TDI(tdi_o), // TDI output from TAP controller
245
.TMS(), // TMS output from TAP controller
246
.UPDATE(update_dr_o), // UPDATE output from TAP controller
247
.TDO1(debug_tdo_i), // Data input for USER1 function
248
.TDO2( 1'b0) // Data input for USER2 function
249
);
250
 
251
assign pause_dr_o = 1'b0;
252
assign run_test_idle_o = 1'b0;
253
 
254
`else
255
`ifdef VIRTEX
256
 
257
// Note that this version is missing three outputs.
258
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
259
 
260
reg capture_dr_o;
261
wire update_bscan;
262
reg update_out;
263
 
264
BSCAN_VIRTEX BSCAN_VIRTEX_inst (
265
.DRCK1(drck), // Data register output for USER1 functions
266
.DRCK2(), // Data register output for USER2 functions
267
.RESET(test_logic_reset_o), // Reset output from TAP controller
268
.SEL1(debug_select_o), // USER1 active output
269
.SEL2(), // USER2 active output
270
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
271
.TDI(tdi_o), // TDI output from TAP controller
272
.UPDATE(update_bscan), // UPDATE output from TAP controller
273
.TDO1(debug_tdo_i), // Data input for USER1 function
274
.TDO2( 1'b0) // Data input for USER2 function
275
);
276
 
277
assign pause_dr_o = 1'b0;
278
assign run_test_idle_o = 1'b0;
279
 
280
// We get one TCK during capture_dr state (low,high,SHIFT goes high on next DRCK low)
281
// On that negative edge, set capture_dr, and it will get registered on the rising
282
// edge, then de-asserted on the same edge that SHIFT goes high.
283
always @ (negedge tck_o)
284
begin
285
        if(debug_select_o && !shift_dr_o)
286
                capture_dr_o <= 1'b1;
287
        else
288
                capture_dr_o <= 1'b0;
289
end
290
 
291
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
292
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
293
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
294
assign tck_o = (drck & debug_select_o & !update_bscan);
295
 
296
// This will hold the update_dr output so it can be registered on the rising edge
297
// of the clock created above.
298
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
299
begin
300
        if(update_bscan) update_out <= 1'b1;
301
        else if(capture_dr_o) update_out <= 1'b0;
302
        else if(!debug_select_o) update_out <= 1'b0;
303
end
304
 
305
assign update_dr_o = update_out;
306
 
307
`else
308
`ifdef VIRTEX2
309
 
310
// Note that this version is missing two outputs.
311
// It also does not have a real TCK...DRCK1 is only active when USER1 is selected.
312
 
313
wire capture_dr_o;
314
wire update_bscan;
315
reg update_out;
316
 
317
BSCAN_VIRTEX2 BSCAN_VIRTEX2_inst (
318
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
319
.DRCK1(drck), // Data register output for USER1 functions
320
.DRCK2(), // Data register output for USER2 functions
321
.RESET(test_logic_reset_o), // Reset output from TAP controller
322
.SEL1(debug_select_o), // USER1 active output
323
.SEL2(), // USER2 active output
324
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
325
.TDI(tdi_o), // TDI output from TAP controller
326
.UPDATE(update_bscan), // UPDATE output from TAP controller
327
.TDO1(debug_tdo_i), // Data input for USER1 function
328
.TDO2( 1'b0 ) // Data input for USER2 function
329
);
330
 
331
assign pause_dr_o = 1'b0;
332
assign run_test_idle_o = 1'b0;
333
 
334
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
335
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
336
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
337
assign tck_o = (drck & debug_select_o & !update_bscan);
338
 
339
// This will hold the update_dr output so it can be registered on the rising edge
340
// of the clock created above.
341
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
342
begin
343
        if(update_bscan) update_out <= 1'b1;
344
        else if(capture_dr_o) update_out <= 1'b0;
345
        else if(!debug_select_o) update_out <= 1'b0;
346
end
347
 
348
assign update_dr_o = update_out;
349
 
350
`else
351
`ifdef VIRTEX4
352
// Note that this version is missing two outputs.
353
// It also does not have a real TCK...DRCK is only active when USERn is selected.
354
 
355
wire capture_dr_o;
356
wire update_bscan;
357
reg update_out;
358
 
359
BSCAN_VIRTEX4 #(
360
.JTAG_CHAIN(virtex_jtag_chain)
361
) BSCAN_VIRTEX4_inst (
362
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
363
.DRCK(drck), // Data register output for USER function
364
.RESET(test_logic_reset_o), // Reset output from TAP controller
365
.SEL(debug_select_o), // USER active output
366
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
367
.TDI(tdi_o), // TDI output from TAP controller
368
.UPDATE(update_bscan), // UPDATE output from TAP controller
369
.TDO( debug_tdo_i ) // Data input for USER function
370
);
371
 
372
assign pause_dr_o = 1'b0;
373
assign run_test_idle_o = 1'b0;
374
 
375
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
376
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
377
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
378
assign tck_o = (drck & debug_select_o & !update_bscan);
379
 
380
// This will hold the update_dr output so it can be registered on the rising edge
381
// of the clock created above.
382
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
383
begin
384
        if(update_bscan) update_out <= 1'b1;
385
        else if(capture_dr_o) update_out <= 1'b0;
386
        else if(!debug_select_o) update_out <= 1'b0;
387
end
388
 
389
assign update_dr_o = update_out;
390
 
391
`else
392
`ifdef VIRTEX5
393
// Note that this version is missing two outputs.
394
// It also does not have a real TCK...DRCK is only active when USERn is selected.
395
 
396
wire capture_dr_o;
397
wire update_bscan;
398
reg update_out;
399
 
400
BSCAN_VIRTEX5 #(
401
.JTAG_CHAIN(virtex_jtag_chain)
402
) BSCAN_VIRTEX5_inst (
403
.CAPTURE(capture_dr_o), // CAPTURE output from TAP controller
404
.DRCK(drck), // Data register output for USER function
405
.RESET(test_logic_reset), // Reset output from TAP controller
406
.SEL(debug_select_o), // USER active output
407
.SHIFT(shift_dr_o), // SHIFT output from TAP controller
408
.TDI(tdi_o), // TDI output from TAP controller
409
.UPDATE(update_bscan), // UPDATE output from TAP controller
410
.TDO(debug_tdo_i) // Data input for USER function
411
);
412
 
413
assign pause_dr_o = 1'b0;
414
assign run_test_idle_o = 1'b0;
415
 
416
// The & !update_bscan tern will provide a clock edge so update_dr_o can be registered
417
// The &debug_select term will drop TCK when the module is un-selected (does not happen in the BSCAN block).
418
// This allows a user to kludge clock ticks in the IDLE state, which is needed by the advanced debug module.
419
assign tck_o = (drck & debug_select_o & !update_bscan);
420
 
421
// This will hold the update_dr output so it can be registered on the rising edge
422
// of the clock created above.
423
always @(posedge update_bscan or posedge capture_dr_o or negedge debug_select_o)
424
begin
425
        if(update_bscan) update_out <= 1'b1;
426
        else if(capture_dr_o) update_out <= 1'b0;
427
        else if(!debug_select_o) update_out <= 1'b0;
428
end
429
 
430
assign update_dr_o = update_out;
431
 
432
 
433
`endif
434
`endif
435
`endif
436
`endif
437
`endif
438
`endif
439
`endif
440
 
441
endmodule

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