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[/] [minsoc/] [trunk/] [sim/] [run/] [generate_bench] - Blame information for rev 166

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Line No. Rev Author Line
1 30 rfajardo
#!/bin/sh
2 166 rfajardo
iverilog -Wimplicit -Wportbind -Wselect-range -Wsensitivity-entire-array -c ../../prj/sim/minsoc_verilog.src -o minsoc_bench

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