OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [sw/] [drivers/] [eth.c] - Blame information for rev 158

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 80 rfajardo
#include <support.h>
2 158 rfajardo
#include "interconnect.h"
3 36 rfajardo
#include "eth.h"
4
 
5
int eth_tx_done;
6
int eth_rx_done;
7
int eth_rx_len;
8
unsigned char eth_tx_packet[1536];     //max length
9
unsigned char eth_rx_packet[1536];
10
unsigned char * eth_tx_data;
11
unsigned char * eth_rx_data;
12
 
13
void eth_recv_ack(void)
14
{
15 53 ConX.
        eth_rx_done = 0;
16
        eth_rx_len = 0;
17
        //accept further data (reset RXBD to empty)
18
        REG32(ETH_BASE + ETH_RXBD0L) = RX_READY;        //len = 0 | IRQ & WR = 1 | EMPTY = 1    
19 36 rfajardo
}
20
 
21
void eth_init()
22
{
23
        //TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1
24
        REG32(ETH_BASE + ETH_MODER) = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD;
25
        //PHY Address = 0x001
26
        REG32(ETH_BASE + ETH_MIIADDRESS) = 0x00000001;
27
 
28
        //enable all interrupts
29
        REG32(ETH_BASE + ETH_INT_MASK) = ETH_RXB | ETH_TXB;
30
 
31
        //set MAC ADDRESS
32
        REG32(ETH_BASE + ETH_MAC_ADDR1) = (OWN_MAC_ADDRESS_5 << 8) | OWN_MAC_ADDRESS_4; //low word = mac address high word
33
        REG32(ETH_BASE + ETH_MAC_ADDR0) = (OWN_MAC_ADDRESS_3 << 24) | (OWN_MAC_ADDRESS_2 << 16)
34 53 ConX.
                | (OWN_MAC_ADDRESS_1 << 8) | OWN_MAC_ADDRESS_0;         //mac address rest
35 36 rfajardo
 
36
        //configure TXBD0
37 37 rfajardo
        REG32(ETH_BASE + ETH_TXBD0H) = (unsigned long)eth_tx_packet;            //address used for tx_data
38 36 rfajardo
        REG32(ETH_BASE + ETH_TXBD0L) = TX_READY;        //length = 0 | PAD & CRC = 1 | IRQ & WR = 1
39
 
40
        //configure RXBD0
41 37 rfajardo
        REG32(ETH_BASE + ETH_RXBD0H) = (unsigned long)eth_rx_packet;            //address used for tx_data
42 36 rfajardo
        REG32(ETH_BASE + ETH_RXBD0L) = RX_READY;        //len = 0 | IRQ & WR = 1 | EMPTY = 1
43
 
44
        //set txdata
45
        eth_tx_packet[0] = BROADCAST_ADDRESS_5;
46
        eth_tx_packet[1] = BROADCAST_ADDRESS_4;
47
        eth_tx_packet[2] = BROADCAST_ADDRESS_3;
48
        eth_tx_packet[3] = BROADCAST_ADDRESS_2;
49
        eth_tx_packet[4] = BROADCAST_ADDRESS_1;
50
        eth_tx_packet[5] = BROADCAST_ADDRESS_0;
51
 
52
        eth_tx_packet[6] = OWN_MAC_ADDRESS_5;
53
        eth_tx_packet[7] = OWN_MAC_ADDRESS_4;
54
        eth_tx_packet[8] = OWN_MAC_ADDRESS_3;
55
        eth_tx_packet[9] = OWN_MAC_ADDRESS_2;
56
        eth_tx_packet[10] = OWN_MAC_ADDRESS_1;
57
        eth_tx_packet[11] = OWN_MAC_ADDRESS_0;
58
 
59
        //erase interrupts
60
        REG32(ETH_BASE + ETH_INT_SOURCE) = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB;
61
 
62 53 ConX.
        eth_tx_done = 1;
63
        eth_rx_done = 0;
64
        eth_rx_len = 0;
65
        eth_tx_data = &eth_tx_packet[HDR_LEN];
66
        eth_rx_data = &eth_rx_packet[HDR_LEN];
67 36 rfajardo
}
68
 
69
int eth_send(int length)
70
{
71 53 ConX.
        if (!eth_tx_done)       //if previous command not fully processed, bail out
72
                return -1;
73 36 rfajardo
 
74 53 ConX.
        eth_tx_done = 0;
75 36 rfajardo
        eth_tx_packet[12] = length >> 8;
76
        eth_tx_packet[13] = length;
77
 
78
        REG32(ETH_BASE + ETH_TXBD0L) = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND;
79
 
80 53 ConX.
        return length;
81 36 rfajardo
}
82
 
83
void eth_interrupt()
84
{
85 53 ConX.
        unsigned long source = REG32(ETH_BASE + ETH_INT_SOURCE);
86
        if ( source & ETH_TXB )
87
        {
88
                eth_tx_done = 1;
89
                //erase interrupt
90
                REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_TXB;
91
        }
92
        if ( source & ETH_RXB )
93
        {
94
                eth_rx_done = 1;
95
                eth_rx_len = (REG32(ETH_BASE + ETH_RXBD0L) >> 16) - HDR_LEN - CRC_LEN;
96
                //erase interrupt
97
                REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_RXB;
98
        }
99 36 rfajardo
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.