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[/] [minsoc/] [trunk/] [sw/] [drivers/] [eth.c] - Blame information for rev 36

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Line No. Rev Author Line
1 36 rfajardo
#include "../support/board.h"
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#include "../support/support.h"
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#include "eth.h"
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int eth_tx_done;
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int eth_rx_done;
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int eth_rx_len;
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unsigned char eth_tx_packet[1536];     //max length
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unsigned char eth_rx_packet[1536];
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unsigned char * eth_tx_data;
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unsigned char * eth_rx_data;
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void eth_recv_ack(void)
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{
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    eth_rx_done = 0;
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    eth_rx_len = 0;
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    //accept further data (reset RXBD to empty)
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    REG32(ETH_BASE + ETH_RXBD0L) = RX_READY;    //len = 0 | IRQ & WR = 1 | EMPTY = 1    
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}
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void eth_init()
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{
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        //TXEN & RXEN = 1; PAD & CRC = 1; FULLD = 1
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        REG32(ETH_BASE + ETH_MODER) = ETH_TXEN | ETH_RXEN | ETH_PAD | ETH_CRCEN | ETH_FULLD;
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        //PHY Address = 0x001
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        REG32(ETH_BASE + ETH_MIIADDRESS) = 0x00000001;
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        //enable all interrupts
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        REG32(ETH_BASE + ETH_INT_MASK) = ETH_RXB | ETH_TXB;
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        //set MAC ADDRESS
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        REG32(ETH_BASE + ETH_MAC_ADDR1) = (OWN_MAC_ADDRESS_5 << 8) | OWN_MAC_ADDRESS_4; //low word = mac address high word
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        REG32(ETH_BASE + ETH_MAC_ADDR0) = (OWN_MAC_ADDRESS_3 << 24) | (OWN_MAC_ADDRESS_2 << 16)
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                                                                         | (OWN_MAC_ADDRESS_1 << 8) | OWN_MAC_ADDRESS_0;                //mac address rest
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        //configure TXBD0
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        REG32(ETH_BASE + ETH_TXBD0H) = eth_tx_packet;           //address used for tx_data
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        REG32(ETH_BASE + ETH_TXBD0L) = TX_READY;        //length = 0 | PAD & CRC = 1 | IRQ & WR = 1
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        //configure RXBD0
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        REG32(ETH_BASE + ETH_RXBD0H) = eth_rx_packet;           //address used for tx_data
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        REG32(ETH_BASE + ETH_RXBD0L) = RX_READY;        //len = 0 | IRQ & WR = 1 | EMPTY = 1
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        //set txdata
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        eth_tx_packet[0] = BROADCAST_ADDRESS_5;
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        eth_tx_packet[1] = BROADCAST_ADDRESS_4;
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        eth_tx_packet[2] = BROADCAST_ADDRESS_3;
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        eth_tx_packet[3] = BROADCAST_ADDRESS_2;
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        eth_tx_packet[4] = BROADCAST_ADDRESS_1;
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        eth_tx_packet[5] = BROADCAST_ADDRESS_0;
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        eth_tx_packet[6] = OWN_MAC_ADDRESS_5;
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        eth_tx_packet[7] = OWN_MAC_ADDRESS_4;
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        eth_tx_packet[8] = OWN_MAC_ADDRESS_3;
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        eth_tx_packet[9] = OWN_MAC_ADDRESS_2;
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        eth_tx_packet[10] = OWN_MAC_ADDRESS_1;
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        eth_tx_packet[11] = OWN_MAC_ADDRESS_0;
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        //erase interrupts
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        REG32(ETH_BASE + ETH_INT_SOURCE) = ETH_RXC | ETH_TXC | ETH_BUSY | ETH_RXE | ETH_RXB | ETH_TXE | ETH_TXB;
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    eth_tx_done = 1;
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    eth_rx_done = 0;
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    eth_rx_len = 0;
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    eth_tx_data = &eth_tx_packet[HDR_LEN];
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    eth_rx_data = &eth_rx_packet[HDR_LEN];
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}
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int eth_send(int length)
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{
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    if (!eth_tx_done)       //if previous command not fully processed, bail out
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        return -1;
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    int i;
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    eth_tx_done = 0;
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        eth_tx_packet[12] = length >> 8;
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        eth_tx_packet[13] = length;
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        REG32(ETH_BASE + ETH_TXBD0L) = (( 0x0000FFFF & ( length + HDR_LEN ) ) << 16) | BD_SND;
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    return length;
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}
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void eth_interrupt()
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{
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    unsigned long source = REG32(ETH_BASE + ETH_INT_SOURCE);
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    if ( source & ETH_TXB )
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    {
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        eth_tx_done = 1;
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        //erase interrupt
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        REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_TXB;
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    }
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    if ( source & ETH_RXB )
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    {
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        eth_rx_done = 1;
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        eth_rx_len = (REG32(ETH_BASE + ETH_RXBD0L) >> 16) - HDR_LEN - CRC_LEN;
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        //erase interrupt
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        REG32(ETH_BASE + ETH_INT_SOURCE) |= ETH_RXB;
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    }
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}
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