OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [sw/] [drivers/] [uart.h] - Blame information for rev 158

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 53 ConX.
#define UART_RX         0        /* In:  Receive buffer (DLAB=0) */
2
#define UART_TX         0        /* Out: Transmit buffer (DLAB=0) */
3
#define UART_DLL        0        /* Out: Divisor Latch Low (DLAB=1) */
4
#define UART_DLM        1       /* Out: Divisor Latch High (DLAB=1) */
5
#define UART_IER        1       /* Out: Interrupt Enable Register */
6
#define UART_IIR        2       /* In:  Interrupt ID Register */
7
#define UART_FCR        2       /* Out: FIFO Control Register */
8
#define UART_EFR        2       /* I/O: Extended Features Register */
9
                                /* (DLAB=1, 16C660 only) */
10
#define UART_LCR        3       /* Out: Line Control Register */
11
#define UART_MCR        4       /* Out: Modem Control Register */
12
#define UART_LSR        5       /* In:  Line Status Register */
13
#define UART_MSR        6       /* In:  Modem Status Register */
14
#define UART_SCR        7       /* I/O: Scratch Register */
15 36 rfajardo
 
16 53 ConX.
/*
17
 * These are the definitions for the FIFO Control Register
18
 * (16650 only)
19
 */
20
#define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
21
#define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
22
#define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
23
#define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
24
#define UART_FCR_TRIGGER_MASK   0xC0 /* Mask for the FIFO trigger range */
25
#define UART_FCR_TRIGGER_1      0x00 /* Mask for trigger set at 1 */
26
#define UART_FCR_TRIGGER_4      0x40 /* Mask for trigger set at 4 */
27
#define UART_FCR_TRIGGER_8      0x80 /* Mask for trigger set at 8 */
28
#define UART_FCR_TRIGGER_14     0xC0 /* Mask for trigger set at 14 */
29 36 rfajardo
 
30 53 ConX.
/* 16650 redefinitions */
31
#define UART_FCR6_R_TRIGGER_8   0x00 /* Mask for receive trigger set at 1 */
32
#define UART_FCR6_R_TRIGGER_16  0x40 /* Mask for receive trigger set at 4 */
33
#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
34
#define UART_FCR6_R_TRIGGER_28  0xC0 /* Mask for receive trigger set at 14 */
35
#define UART_FCR6_T_TRIGGER_16  0x00 /* Mask for transmit trigger set at 16 */
36
#define UART_FCR6_T_TRIGGER_8   0x10 /* Mask for transmit trigger set at 8 */
37
#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
38
#define UART_FCR6_T_TRIGGER_30  0x30 /* Mask for transmit trigger set at 30 */
39
 
40
/*
41
 * These are the definitions for the Line Control Register
42
 *
43
 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
44
 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
45
 */
46
#define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
47
#define UART_LCR_SBC    0x40    /* Set break control */
48
#define UART_LCR_SPAR   0x20    /* Stick parity (?) */
49
#define UART_LCR_EPAR   0x10    /* Even parity select */
50
#define UART_LCR_PARITY 0x08    /* Parity Enable */
51
#define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
52
#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
53
#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
54
#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
55
#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
56
 
57
/*
58
 * These are the definitions for the Line Status Register
59
 */
60
#define UART_LSR_TEMT   0x40    /* Transmitter empty */
61
#define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
62
#define UART_LSR_BI     0x10    /* Break interrupt indicator */
63
#define UART_LSR_FE     0x08    /* Frame error indicator */
64
#define UART_LSR_PE     0x04    /* Parity error indicator */
65
#define UART_LSR_OE     0x02    /* Overrun error indicator */
66
#define UART_LSR_DR     0x01    /* Receiver data ready */
67
 
68
/*
69
 * These are the definitions for the Interrupt Identification Register
70
 */
71
#define UART_IIR_NO_INT 0x01    /* No interrupts pending */
72
#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
73
 
74
#define UART_IIR_MSI    0x00    /* Modem status interrupt */
75
#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
76
#define UART_IIR_TOI    0x0c    /* Receive time out interrupt */
77
#define UART_IIR_RDI    0x04    /* Receiver data interrupt */
78
#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
79
 
80
/*
81
 * These are the definitions for the Interrupt Enable Register
82
 */
83
#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
84
#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
85
#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
86
#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
87
 
88
/*
89
 * These are the definitions for the Modem Control Register
90
 */
91
#define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
92
#define UART_MCR_OUT2   0x08    /* Out2 complement */
93
#define UART_MCR_OUT1   0x04    /* Out1 complement */
94
#define UART_MCR_RTS    0x02    /* RTS complement */
95
#define UART_MCR_DTR    0x01    /* DTR complement */
96
 
97
/*
98
 * These are the definitions for the Modem Status Register
99
 */
100
#define UART_MSR_DCD    0x80    /* Data Carrier Detect */
101
#define UART_MSR_RI     0x40    /* Ring Indicator */
102
#define UART_MSR_DSR    0x20    /* Data Set Ready */
103
#define UART_MSR_CTS    0x10    /* Clear to Send */
104
#define UART_MSR_DDCD   0x08    /* Delta DCD */
105
#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
106
#define UART_MSR_DDSR   0x02    /* Delta DSR */
107
#define UART_MSR_DCTS   0x01    /* Delta CTS */
108
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
109
 
110
/*
111
 * These are the definitions for the Extended Features Register
112
 * (StarTech 16C660 only, when DLAB=1)
113
 */
114
#define UART_EFR_CTS    0x80    /* CTS flow control */
115
#define UART_EFR_RTS    0x40    /* RTS flow control */
116
#define UART_EFR_SCD    0x20    /* Special character detect */
117
#define UART_EFR_ENI    0x10    /* Enhanced Interrupt */
118
 
119
 
120 158 rfajardo
void uart_init(unsigned long);
121 53 ConX.
void uart_putc(char);
122
char uart_getc(void);
123 36 rfajardo
void uart_print_str(char *);
124
void uart_print_long(unsigned long);
125
void uart_interrupt();
126
void uart_print_short(unsigned long ul);

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.