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[/] [minsoc/] [trunk/] [sw/] [support/] [int.c] - Blame information for rev 53

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1 2 rfajardo
/* This file is part of test microkernel for OpenRISC 1000. */
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/* (C) 2001 Simon Srot, srot@opencores.org */
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#include "support.h"
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#include "or1200.h"
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#include "int.h"
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#ifdef OR1K
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/* Interrupt handlers table */
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struct ihnd int_handlers[MAX_INT_HANDLERS];
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/* Initialize routine */
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int int_init()
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{
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        int i;
17 2 rfajardo
 
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        for(i = 0; i < MAX_INT_HANDLERS; i++) {
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                int_handlers[i].handler = 0;
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                int_handlers[i].arg = 0;
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        }
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        mtspr(SPR_PICMR, 0x00000000);
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        //set OR1200 to accept exceptions
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        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
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        return 0;
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}
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/* Add interrupt handler */
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int int_add(unsigned long vect, void (* handler)(void *), void *arg)
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{
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        if(vect >= MAX_INT_HANDLERS)
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                return -1;
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36 53 ConX.
        int_handlers[vect].handler = handler;
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        int_handlers[vect].arg = arg;
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        mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
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        return 0;
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}
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/* Disable interrupt */
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int int_disable(unsigned long vect)
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{
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        if(vect >= MAX_INT_HANDLERS)
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                return -1;
49 2 rfajardo
 
50 53 ConX.
        mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
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        return 0;
53 2 rfajardo
}
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/* Enable interrupt */
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int int_enable(unsigned long vect)
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{
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        if(vect >= MAX_INT_HANDLERS)
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                return -1;
60 2 rfajardo
 
61 53 ConX.
        mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
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        return 0;
64 2 rfajardo
}
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/* Main interrupt handler */
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void int_main()
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{
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        unsigned long picsr = mfspr(SPR_PICSR);   //process only the interrupts asserted at signal catch, ignore all during process
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        unsigned long i = 0;
71 2 rfajardo
 
72 53 ConX.
        while(i < 32) {
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                if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
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                        (*int_handlers[i].handler)(int_handlers[i].arg);
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                }
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                i++;
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        }
78 11 rfajardo
 
79 53 ConX.
        mtspr(SPR_PICSR, 0);      //clear interrupt status: all modules have level interrupts, which have to be cleared by software,
80 11 rfajardo
}                           //thus this is safe, since non processed interrupts will get re-asserted soon enough
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82 53 ConX.
 
83 2 rfajardo
#endif

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