OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [sw/] [support/] [int.c] - Blame information for rev 55

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rfajardo
/* This file is part of test microkernel for OpenRISC 1000. */
2
/* (C) 2001 Simon Srot, srot@opencores.org */
3
 
4
#include "support.h"
5 53 ConX.
#include "or1200.h"
6 2 rfajardo
#include "int.h"
7
 
8
/* Interrupt handlers table */
9
struct ihnd int_handlers[MAX_INT_HANDLERS];
10
 
11
/* Initialize routine */
12
int int_init()
13
{
14 53 ConX.
        int i;
15 2 rfajardo
 
16 53 ConX.
        for(i = 0; i < MAX_INT_HANDLERS; i++) {
17
                int_handlers[i].handler = 0;
18
                int_handlers[i].arg = 0;
19
        }
20
        mtspr(SPR_PICMR, 0x00000000);
21 2 rfajardo
 
22 53 ConX.
        //set OR1200 to accept exceptions
23
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
24
 
25
        return 0;
26 2 rfajardo
}
27
 
28
/* Add interrupt handler */
29
int int_add(unsigned long vect, void (* handler)(void *), void *arg)
30
{
31 53 ConX.
        if(vect >= MAX_INT_HANDLERS)
32
                return -1;
33 2 rfajardo
 
34 53 ConX.
        int_handlers[vect].handler = handler;
35
        int_handlers[vect].arg = arg;
36 2 rfajardo
 
37 53 ConX.
        mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
38
 
39
        return 0;
40 2 rfajardo
}
41
 
42
/* Disable interrupt */
43
int int_disable(unsigned long vect)
44
{
45 53 ConX.
        if(vect >= MAX_INT_HANDLERS)
46
                return -1;
47 2 rfajardo
 
48 53 ConX.
        mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
49
 
50
        return 0;
51 2 rfajardo
}
52
 
53
/* Enable interrupt */
54
int int_enable(unsigned long vect)
55
{
56 53 ConX.
        if(vect >= MAX_INT_HANDLERS)
57
                return -1;
58 2 rfajardo
 
59 53 ConX.
        mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
60
 
61
        return 0;
62 2 rfajardo
}
63
 
64
/* Main interrupt handler */
65
void int_main()
66
{
67 53 ConX.
        unsigned long picsr = mfspr(SPR_PICSR);   //process only the interrupts asserted at signal catch, ignore all during process
68
        unsigned long i = 0;
69 2 rfajardo
 
70 53 ConX.
        while(i < 32) {
71
                if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
72
                        (*int_handlers[i].handler)(int_handlers[i].arg);
73
                }
74
                i++;
75
        }
76 11 rfajardo
 
77 53 ConX.
        mtspr(SPR_PICSR, 0);      //clear interrupt status: all modules have level interrupts, which have to be cleared by software,
78 11 rfajardo
}                           //thus this is safe, since non processed interrupts will get re-asserted soon enough
79
 

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.