OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [sw/] [support/] [reset.S] - Blame information for rev 17

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rfajardo
/* Support file for c based tests */
2
#include "spr_defs.h"
3
#include "board.h"
4
#include "mc.h"
5
 
6
        .section .stack
7
        .space STACK_SIZE
8
_stack:
9
 
10
        .section .reset, "ax"
11
 
12
        .org    0x100
13
_reset_vector:
14
        l.nop
15
        l.nop
16
        l.addi  r2,r0,0x0
17
        l.addi  r3,r0,0x0
18
        l.addi  r4,r0,0x0
19
        l.addi  r5,r0,0x0
20
        l.addi  r6,r0,0x0
21
        l.addi  r7,r0,0x0
22
        l.addi  r8,r0,0x0
23
        l.addi  r9,r0,0x0
24
        l.addi  r10,r0,0x0
25
        l.addi  r11,r0,0x0
26
        l.addi  r12,r0,0x0
27
        l.addi  r13,r0,0x0
28
        l.addi  r14,r0,0x0
29
        l.addi  r15,r0,0x0
30
        l.addi  r16,r0,0x0
31
        l.addi  r17,r0,0x0
32
        l.addi  r18,r0,0x0
33
        l.addi  r19,r0,0x0
34
        l.addi  r20,r0,0x0
35
        l.addi  r21,r0,0x0
36
        l.addi  r22,r0,0x0
37
        l.addi  r23,r0,0x0
38
        l.addi  r24,r0,0x0
39
        l.addi  r25,r0,0x0
40
        l.addi  r26,r0,0x0
41
        l.addi  r27,r0,0x0
42
        l.addi  r28,r0,0x0
43
        l.addi  r29,r0,0x0
44
        l.addi  r30,r0,0x0
45
        l.addi  r31,r0,0x0
46
 
47
/*
48
        l.movhi r3,hi(MC_BASE_ADDR)
49
        l.ori   r3,r3,MC_BA_MASK
50
        l.addi  r5,r0,0x00
51
        l.sw    0(r3),r5
52
        */
53
        l.movhi r3,hi(_start)
54
        l.ori   r3,r3,lo(_start)
55
        l.jr    r3
56
        l.nop
57
 
58
        .section .text
59
 
60
_start:
61
 
62
.if IC | DC
63
        /* Flush IC and/or DC */
64
        l.addi  r10,r0,0
65
        l.addi  r11,r0,0
66
        l.addi  r12,r0,0
67
.if IC
68
        l.addi  r11,r0,IC_SIZE
69
.endif
70
.if DC
71
        l.addi  r12,r0,DC_SIZE
72
.endif
73
        l.sfleu r12,r11
74
        l.bf    loop
75
        l.nop
76
        l.add   r11,r0,r12
77
loop:
78
.if IC
79
        l.mtspr r0,r10,SPR_ICBIR
80
.endif
81
.if DC
82
        l.mtspr r0,r10,SPR_DCBIR
83
.endif
84
        l.sfne  r10,r11
85
        l.bf    loop
86
        l.addi  r10,r10,16
87
 
88
        /* Enable IC and/or DC */
89
        l.addi  r10,r0,(SPR_SR_SM)
90
.if IC
91
        l.ori   r10,r10,(SPR_SR_ICE)
92
.endif
93
.if DC
94
        l.ori   r10,r10,(SPR_SR_DCE)
95
.endif
96
        l.mtspr r0,r10,SPR_SR
97
        l.nop
98
        l.nop
99
        l.nop
100
        l.nop
101
        l.nop
102
.endif
103
 
104
        /* Set stack pointer */
105
        l.movhi r1,hi(_stack)
106
        l.ori   r1,r1,lo(_stack)
107
 
108
        /* Jump to main */
109
        l.movhi r2,hi(_reset)
110
        l.ori   r2,r2,lo(_reset)
111
        l.jr    r2
112
        l.nop
113
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.