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[/] [minsoc/] [trunk/] [syn/] [xilinx/] [Makefile] - Blame information for rev 85

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Line No. Rev Author Line
1 64 rfajardo
MINSOC = ../
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MINSOC_DEFINES = ${MINSOC}/backend
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MINSOC_RTL = ${MINSOC}/rtl/verilog
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MINSOC_STARTUP_RTL = ${MINSOC_RTL}/minsoc_startup
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UART_RTL = ${MINSOC_RTL}/uart16550/rtl/verilog
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ADV_DEBUG_ROOT = ${MINSOC_RTL}/adv_debug_sys/Hardware
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DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog
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OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog
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ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog
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BUILD_SUPPORT = $(MINSOC)/syn/buildSupport
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help:
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        @echo "  all: Synthesize and implement the SoC, then generate a bit stream"
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        @echo ""
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        @echo "  soc: Synthesize the SoC"
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        @echo "  translate: Convert the SoC's ngc file to an ngd file for mapping"
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        @echo "  map: Express the SoC netlist in the target hardware"
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        @echo "  par: Place the target hardware, then route the wires"
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        @echo "  bitgen: Generate a programming file for the target FPGA"
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        @echo ""
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        @echo "  modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers"
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        @echo "  or1200: Synthesize the OR1200 processor"
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        @echo "  debug: Synthesize the debug interface"
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        @echo "  uart: Synthesize the UART"
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        @echo "  eth: Synthesize the Ethernet controller"
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        @echo ""
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        @echo "  clean: Delete all superfluous files generated by Xilinx tools"
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        @echo "  distclean: Delete all generated files"
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30 64 rfajardo
all: minsoc.bit
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soc: minsoc_top.ngc
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translate: minsoc.ngd
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map: minsoc.ncd
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par: minsoc_par.ncd
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bitgen: minsoc.bit
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modules: or1200 debug uart eth
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MODULES = or1200_top.ngc adbg_top.ngc uart_top.ngc ethmac.ngc
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prepare:
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        rm -rf xst
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        mkdir xst
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clean:
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        rm -rf _xmsgs xst xlnx_auto_0_xdb
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        rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html
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distclean:
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        rm -rf *.ngc *.ncd *.ngd *.bit
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        make clean
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49 85 rfajardo
minsoc_top.ngc: ${MINSOC_RTL}/*.v ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.xst $(BUILD_SUPPORT)/minsoc_top.prj
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        make prepare
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        xst -ifn "$(BUILD_SUPPORT)/minsoc_top.xst"
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uart: uart_top.ngc
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uart_top.ngc: ${UART_RTL}/*.v $(BUILD_SUPPORT)/uart_top.xst $(BUILD_SUPPORT)/uart_top.prj
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        make prepare
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        xst -ifn "$(BUILD_SUPPORT)/uart_top.xst"
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58 85 rfajardo
eth: ethmac.ngc
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ethmac.ngc: ${ETH_RTL}/*.v $(BUILD_SUPPORT)/ethmac.xst $(BUILD_SUPPORT)/ethmac.prj
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        make prepare
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        xst -ifn "$(BUILD_SUPPORT)/ethmac.xst"
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debug: adbg_top.ngc
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adbg_top.ngc: ${DEBUG_RTL}/*.v $(BUILD_SUPPORT)/adbg_top.xst $(BUILD_SUPPORT)/adbg_top.prj
65 64 rfajardo
        make prepare
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        xst -ifn "$(BUILD_SUPPORT)/adbg_top.xst"
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or1200: or1200_top.ngc
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or1200_top.ngc: ${OR1200_RTL}/*.v $(BUILD_SUPPORT)/or1200_top.xst $(BUILD_SUPPORT)/or1200_top.prj
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        make prepare
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        xst -ifn "$(BUILD_SUPPORT)/or1200_top.xst"
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minsoc.ngd: ${MINSOC}/backend/CONSTRAINT_FILE minsoc_top.ngc $(MODULES)
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        ngdbuild -p DEVICE_PART -uc ${MINSOC}/backend/CONSTRAINT_FILE -aul minsoc_top.ngc minsoc.ngd
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minsoc.ncd: minsoc.ngd
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        map -bp -timing -cm speed -equivalent_register_removal on -logic_opt on -ol high -power off -register_duplication on -retiming on -w -xe n minsoc.ngd
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minsoc_par.ncd: minsoc.ncd
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        par -ol high -w -xe n minsoc.ncd minsoc_par.ncd
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minsoc.bit: minsoc_par.ncd
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        bitgen -d -w minsoc_par.ncd minsoc.bit

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