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[/] [minsoc/] [trunk/] [utils/] [contributions/] [gpio/] [rtl/] [gpio_top.v] - Blame information for rev 40

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1 40 rfajardo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  WISHBONE General-Purpose I/O                                ////
4
////                                                              ////
5
////  This file is part of the GPIO project                       ////
6
////  http://www.opencores.org/cores/gpio/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Implementation of GPIO IP core according to                 ////
10
////  GPIO IP core specification document.                        ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   Nothing                                                    ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48
// Revision 1.17  2004/05/05 08:21:00  andreje
49
// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec
50
//
51
// Revision 1.16  2003/12/17 13:00:52  gorand
52
// added ECLK and NEC registers, all tests passed.
53
//
54
// Revision 1.15  2003/11/10 23:21:22  gorand
55
// bug fixed. all tests passed.
56
//
57
// Revision 1.14  2003/11/06 13:59:07  gorand
58
// added support for 8-bit access to registers.
59
//
60
// Revision 1.13  2002/11/18 22:35:18  lampret
61
// Bug fix. Interrupts were also asserted when condition was not met.
62
//
63
// Revision 1.12  2002/11/11 21:36:28  lampret
64
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
65
//
66
// Revision 1.11  2002/03/13 20:56:28  lampret
67
// Removed zero padding as per Avi Shamli suggestion.
68
//
69
// Revision 1.10  2002/03/13 20:47:57  lampret
70
// Ports changed per Ran Aviram suggestions.
71
//
72
// Revision 1.9  2002/03/09 03:43:27  lampret
73
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
74
//
75
// Revision 1.8  2002/01/14 19:06:28  lampret
76
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
77
//
78
// Revision 1.7  2001/12/25 17:21:21  lampret
79
// Fixed two typos.
80
//
81
// Revision 1.6  2001/12/25 17:12:35  lampret
82
// Added RGPIO_INTS.
83
//
84
// Revision 1.5  2001/12/12 20:35:53  lampret
85
// Fixing style.
86
//
87
// Revision 1.4  2001/12/12 07:12:58  lampret
88
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
89
//
90
// Revision 1.3  2001/11/15 02:24:37  lampret
91
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
92
//
93
// Revision 1.2  2001/10/31 02:26:51  lampret
94
// Fixed wb_err_o.
95
//
96
// Revision 1.1  2001/09/18 18:49:07  lampret
97
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
98
//
99
// Revision 1.1  2001/08/21 21:39:28  lampret
100
// Changed directory structure, port names and drfines.
101
//
102
// Revision 1.2  2001/07/14 20:39:26  lampret
103
// Better configurability.
104
//
105
// Revision 1.1  2001/06/05 07:45:26  lampret
106
// Added initial RTL and test benches. There are still some issues with these files.
107
//
108
//
109
 
110
// synopsys translate_off
111
`include "timescale.v"
112
// synopsys translate_on
113
`include "gpio_defines.v"
114
 
115
module gpio_top(
116
        // WISHBONE Interface
117
        wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
118
        wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
119
 
120
`ifdef GPIO_AUX_IMPLEMENT
121
        // Auxiliary inputs interface
122
        aux_i,
123
`endif //  GPIO_AUX_IMPLEMENT
124
 
125
        // External GPIO Interface
126
        ext_pad_i, ext_pad_o, ext_padoe_o
127
`ifdef GPIO_CLKPAD
128
  , clk_pad_i
129
`endif
130
);
131
 
132
parameter dw = 32;
133
parameter aw = `GPIO_ADDRHH+1;
134
parameter gw = `GPIO_IOS;
135
//
136
// WISHBONE Interface
137
//
138
input             wb_clk_i;     // Clock
139
input             wb_rst_i;     // Reset
140
input             wb_cyc_i;     // cycle valid input
141
input   [aw-1:0] wb_adr_i;       // address bus inputs
142
input   [dw-1:0] wb_dat_i;       // input data bus
143
input     [3:0]     wb_sel_i;    // byte select inputs
144
input             wb_we_i;      // indicates write transfer
145
input             wb_stb_i;     // strobe input
146
output  [dw-1:0]  wb_dat_o;      // output data bus
147
output            wb_ack_o;     // normal termination
148
output            wb_err_o;     // termination w/ error
149
output            wb_inta_o;    // Interrupt request output
150
 
151
`ifdef GPIO_AUX_IMPLEMENT
152
// Auxiliary Inputs Interface
153
input     [gw-1:0]  aux_i;               // Auxiliary inputs
154
`endif // GPIO_AUX_IMPLEMENT
155
 
156
//
157
// External GPIO Interface
158
//
159
input   [gw-1:0]  ext_pad_i;     // GPIO Inputs
160
`ifdef GPIO_CLKPAD
161
input             clk_pad_i;    // GPIO Eclk
162
`endif //  GPIO_CLKPAD
163
output  [gw-1:0]  ext_pad_o;     // GPIO Outputs
164
output  [gw-1:0]  ext_padoe_o;   // GPIO output drivers enables
165
 
166
`ifdef GPIO_IMPLEMENTED
167
 
168
//
169
// GPIO Input Register (or no register)
170
//
171
`ifdef GPIO_RGPIO_IN
172
reg     [gw-1:0] rgpio_in;       // RGPIO_IN register
173
`else
174
wire    [gw-1:0] rgpio_in;       // No register
175
`endif
176
 
177
//
178
// GPIO Output Register (or no register)
179
//
180
`ifdef GPIO_RGPIO_OUT
181
reg     [gw-1:0] rgpio_out;      // RGPIO_OUT register
182
`else
183
wire    [gw-1:0] rgpio_out;      // No register
184
`endif
185
 
186
//
187
// GPIO Output Driver Enable Register (or no register)
188
//
189
`ifdef GPIO_RGPIO_OE
190
reg     [gw-1:0] rgpio_oe;       // RGPIO_OE register
191
`else
192
wire    [gw-1:0] rgpio_oe;       // No register
193
`endif
194
 
195
//
196
// GPIO Interrupt Enable Register (or no register)
197
//
198
`ifdef GPIO_RGPIO_INTE
199
reg     [gw-1:0] rgpio_inte;     // RGPIO_INTE register
200
`else
201
wire    [gw-1:0] rgpio_inte;     // No register
202
`endif
203
 
204
//
205
// GPIO Positive edge Triggered Register (or no register)
206
//
207
`ifdef GPIO_RGPIO_PTRIG
208
reg     [gw-1:0] rgpio_ptrig;    // RGPIO_PTRIG register
209
`else
210
wire    [gw-1:0] rgpio_ptrig;    // No register
211
`endif
212
 
213
//
214
// GPIO Auxiliary select Register (or no register)
215
//
216
`ifdef GPIO_RGPIO_AUX
217
reg     [gw-1:0] rgpio_aux;      // RGPIO_AUX register
218
`else
219
wire    [gw-1:0] rgpio_aux;      // No register
220
`endif
221
 
222
//
223
// GPIO Control Register (or no register)
224
//
225
`ifdef GPIO_RGPIO_CTRL
226
reg     [1:0]            rgpio_ctrl;     // RGPIO_CTRL register
227
`else
228
wire    [1:0]            rgpio_ctrl;     // No register
229
`endif
230
 
231
//
232
// GPIO Interrupt Status Register (or no register)
233
//
234
`ifdef GPIO_RGPIO_INTS
235
reg     [gw-1:0] rgpio_ints;     // RGPIO_INTS register
236
`else
237
wire    [gw-1:0] rgpio_ints;     // No register
238
`endif
239
 
240
//
241
// GPIO Enable Clock  Register (or no register)
242
//
243
`ifdef GPIO_RGPIO_ECLK
244
reg     [gw-1:0] rgpio_eclk;     // RGPIO_ECLK register
245
`else
246
wire    [gw-1:0] rgpio_eclk;     // No register
247
`endif
248
 
249
//
250
// GPIO Active Negative Edge  Register (or no register)
251
//
252
`ifdef GPIO_RGPIO_NEC
253
reg     [gw-1:0] rgpio_nec;      // RGPIO_NEC register
254
`else
255
wire    [gw-1:0] rgpio_nec;      // No register
256
`endif
257
 
258
 
259
//
260
// Synchronization flops for input signals
261
//
262
`ifdef GPIO_SYNC_IN_WB
263
reg  [gw-1:0]  sync      ,
264
               ext_pad_s ;
265
`else
266
wire [gw-1:0]  ext_pad_s ;
267
`endif
268
 
269
 
270
 
271
//
272
// Internal wires & regs
273
//
274
wire            rgpio_out_sel;  // RGPIO_OUT select
275
wire            rgpio_oe_sel; // RGPIO_OE select
276
wire            rgpio_inte_sel; // RGPIO_INTE select
277
wire            rgpio_ptrig_sel;// RGPIO_PTRIG select
278
wire            rgpio_aux_sel;  // RGPIO_AUX select
279
wire            rgpio_ctrl_sel; // RGPIO_CTRL select
280
wire            rgpio_ints_sel; // RGPIO_INTS select
281
wire            rgpio_eclk_sel ;
282
wire            rgpio_nec_sel ;
283
wire            full_decoding;  // Full address decoding qualification
284
wire  [gw-1:0]  in_muxed; // Muxed inputs
285
wire            wb_ack;   // WB Acknowledge
286
wire            wb_err;   // WB Error
287
wire            wb_inta;  // WB Interrupt
288
reg   [dw-1:0]  wb_dat;   // WB Data out
289
`ifdef GPIO_REGISTERED_WB_OUTPUTS
290
reg             wb_ack_o; // WB Acknowledge
291
reg             wb_err_o; // WB Error
292
reg             wb_inta_o;  // WB Interrupt
293
reg   [dw-1:0]  wb_dat_o; // WB Data out
294
`endif
295
wire  [gw-1:0]  out_pad;  // GPIO Outputs
296
`ifdef GPIO_REGISTERED_IO_OUTPUTS
297
reg   [gw-1:0]  ext_pad_o;  // GPIO Outputs
298
`endif
299
`ifdef GPIO_CLKPAD
300
wire  [gw-1:0]  extc_in;  // Muxed inputs sampled by external clock
301
wire  [gw-1:0]  pext_clk; // External clock for posedge flops
302
reg   [gw-1:0]  pextc_sampled;  // Posedge external clock sampled inputs
303
`ifdef GPIO_NO_NEGEDGE_FLOPS
304
`ifdef GPIO_NO_CLKPAD_LOGIC
305
`else
306
reg   [gw-1:0]  nextc_sampled;  // Negedge external clock sampled inputs
307
`endif //  GPIO_NO_CLKPAD_LOGIC
308
`else
309
reg   [gw-1:0]  nextc_sampled;  // Negedge external clock sampled inputs
310
`endif
311
`endif //  GPIO_CLKPAD
312
 
313
 
314
//
315
// All WISHBONE transfer terminations are successful except when:
316
// a) full address decoding is enabled and address doesn't match
317
//    any of the GPIO registers
318
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
319
//
320
 
321
//
322
// WB Acknowledge
323
//
324
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
325
 
326
//
327
// Optional registration of WB Ack
328
//
329
`ifdef GPIO_REGISTERED_WB_OUTPUTS
330
always @(posedge wb_clk_i or posedge wb_rst_i)
331
        if (wb_rst_i)
332
                wb_ack_o <= #1 1'b0;
333
        else
334
                wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;
335
`else
336
assign wb_ack_o = wb_ack;
337
`endif
338
 
339
//
340
// WB Error
341
//
342
`ifdef GPIO_FULL_DECODE
343
`ifdef GPIO_STRICT_32BIT_ACCESS
344
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
345
`else
346
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
347
`endif
348
`else
349
`ifdef GPIO_STRICT_32BIT_ACCESS
350
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
351
`else
352
assign wb_err = 1'b0;
353
`endif
354
`endif
355
 
356
//
357
// Optional registration of WB error
358
//
359
`ifdef GPIO_REGISTERED_WB_OUTPUTS
360
always @(posedge wb_clk_i or posedge wb_rst_i)
361
        if (wb_rst_i)
362
                wb_err_o <= #1 1'b0;
363
        else
364
                wb_err_o <= #1 wb_err & ~wb_err_o;
365
`else
366
assign wb_err_o = wb_err;
367
`endif
368
 
369
//
370
// Full address decoder
371
//
372
`ifdef GPIO_FULL_DECODE
373
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
374
                        (wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
375
`else
376
assign full_decoding = 1'b1;
377
`endif
378
 
379
//
380
// GPIO registers address decoder
381
//
382
`ifdef GPIO_RGPIO_OUT
383
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
384
`endif
385
`ifdef GPIO_RGPIO_OE
386
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
387
`endif
388
`ifdef GPIO_RGPIO_INTE
389
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
390
`endif
391
`ifdef GPIO_RGPIO_PTRIG
392
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
393
`endif
394
`ifdef GPIO_RGPIO_AUX
395
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
396
`endif
397
`ifdef GPIO_RGPIO_CTRL
398
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
399
`endif
400
`ifdef GPIO_RGPIO_INTS
401
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
402
`endif
403
`ifdef GPIO_RGPIO_ECLK
404
assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
405
`endif
406
`ifdef GPIO_RGPIO_NEC
407
assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
408
`endif
409
 
410
 
411
//
412
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
413
//
414
`ifdef GPIO_RGPIO_CTRL
415
always @(posedge wb_clk_i or posedge wb_rst_i)
416
        if (wb_rst_i)
417
                rgpio_ctrl <= #1 2'b0;
418
        else if (rgpio_ctrl_sel && wb_we_i)
419
                rgpio_ctrl <= #1 wb_dat_i[1:0];
420
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
421
                rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
422
`else
423
assign rgpio_ctrl = 2'h01;      // RGPIO_CTRL[EN] = 1
424
`endif
425
 
426
//
427
// Write to RGPIO_OUT
428
//
429
`ifdef GPIO_RGPIO_OUT
430
always @(posedge wb_clk_i or posedge wb_rst_i)
431
        if (wb_rst_i)
432
                rgpio_out <= #1 {gw{1'b0}};
433
        else if (rgpio_out_sel && wb_we_i)
434
    begin
435
`ifdef GPIO_STRICT_32BIT_ACCESS
436
                rgpio_out <= #1 wb_dat_i[gw-1:0];
437
`endif
438
 
439
`ifdef GPIO_WB_BYTES4
440
     if ( wb_sel_i [3] == 1'b1 )
441
       rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
442
     if ( wb_sel_i [2] == 1'b1 )
443
       rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;
444
     if ( wb_sel_i [1] == 1'b1 )
445
       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
446
     if ( wb_sel_i [0] == 1'b1 )
447
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
448
`endif
449
`ifdef GPIO_WB_BYTES3
450
     if ( wb_sel_i [2] == 1'b1 )
451
       rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
452
     if ( wb_sel_i [1] == 1'b1 )
453
       rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
454
     if ( wb_sel_i [0] == 1'b1 )
455
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
456
`endif
457
`ifdef GPIO_WB_BYTES2
458
     if ( wb_sel_i [1] == 1'b1 )
459
       rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
460
     if ( wb_sel_i [0] == 1'b1 )
461
       rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
462
`endif
463
`ifdef GPIO_WB_BYTES1
464
     if ( wb_sel_i [0] == 1'b1 )
465
       rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
466
`endif
467
   end
468
 
469
`else
470
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
471
`endif
472
 
473
//
474
// Write to RGPIO_OE.
475
//
476
`ifdef GPIO_RGPIO_OE
477
always @(posedge wb_clk_i or posedge wb_rst_i)
478
        if (wb_rst_i)
479
                rgpio_oe <= #1 {gw{1'b0}};
480
        else if (rgpio_oe_sel && wb_we_i)
481
  begin
482
`ifdef GPIO_STRICT_32BIT_ACCESS
483
                rgpio_oe <= #1 wb_dat_i[gw-1:0];
484
`endif
485
 
486
`ifdef GPIO_WB_BYTES4
487
     if ( wb_sel_i [3] == 1'b1 )
488
       rgpio_oe [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
489
     if ( wb_sel_i [2] == 1'b1 )
490
       rgpio_oe [23:16] <= #1 wb_dat_i [23:16] ;
491
     if ( wb_sel_i [1] == 1'b1 )
492
       rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ;
493
     if ( wb_sel_i [0] == 1'b1 )
494
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
495
`endif
496
`ifdef GPIO_WB_BYTES3
497
     if ( wb_sel_i [2] == 1'b1 )
498
       rgpio_oe [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
499
     if ( wb_sel_i [1] == 1'b1 )
500
       rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ;
501
     if ( wb_sel_i [0] == 1'b1 )
502
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
503
`endif
504
`ifdef GPIO_WB_BYTES2
505
     if ( wb_sel_i [1] == 1'b1 )
506
       rgpio_oe [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
507
     if ( wb_sel_i [0] == 1'b1 )
508
       rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
509
`endif
510
`ifdef GPIO_WB_BYTES1
511
     if ( wb_sel_i [0] == 1'b1 )
512
       rgpio_oe [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
513
`endif
514
   end
515
 
516
`else
517
assign rgpio_oe = `GPIO_DEF_RGPIO_OE;   // RGPIO_OE = 0x0
518
`endif
519
 
520
//
521
// Write to RGPIO_INTE
522
//
523
`ifdef GPIO_RGPIO_INTE
524
always @(posedge wb_clk_i or posedge wb_rst_i)
525
        if (wb_rst_i)
526
                rgpio_inte <= #1 {gw{1'b0}};
527
        else if (rgpio_inte_sel && wb_we_i)
528
  begin
529
`ifdef GPIO_STRICT_32BIT_ACCESS
530
                rgpio_inte <= #1 wb_dat_i[gw-1:0];
531
`endif
532
 
533
`ifdef GPIO_WB_BYTES4
534
     if ( wb_sel_i [3] == 1'b1 )
535
       rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
536
     if ( wb_sel_i [2] == 1'b1 )
537
       rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;
538
     if ( wb_sel_i [1] == 1'b1 )
539
       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
540
     if ( wb_sel_i [0] == 1'b1 )
541
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
542
`endif
543
`ifdef GPIO_WB_BYTES3
544
     if ( wb_sel_i [2] == 1'b1 )
545
       rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
546
     if ( wb_sel_i [1] == 1'b1 )
547
       rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
548
     if ( wb_sel_i [0] == 1'b1 )
549
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
550
`endif
551
`ifdef GPIO_WB_BYTES2
552
     if ( wb_sel_i [1] == 1'b1 )
553
       rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
554
     if ( wb_sel_i [0] == 1'b1 )
555
       rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
556
`endif
557
`ifdef GPIO_WB_BYTES1
558
     if ( wb_sel_i [0] == 1'b1 )
559
       rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
560
`endif
561
   end
562
 
563
 
564
`else
565
assign rgpio_inte = `GPIO_DEF_RGPIO_INTE;       // RGPIO_INTE = 0x0
566
`endif
567
 
568
//
569
// Write to RGPIO_PTRIG
570
//
571
`ifdef GPIO_RGPIO_PTRIG
572
always @(posedge wb_clk_i or posedge wb_rst_i)
573
        if (wb_rst_i)
574
                rgpio_ptrig <= #1 {gw{1'b0}};
575
        else if (rgpio_ptrig_sel && wb_we_i)
576
  begin
577
`ifdef GPIO_STRICT_32BIT_ACCESS
578
                rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
579
`endif
580
 
581
`ifdef GPIO_WB_BYTES4
582
     if ( wb_sel_i [3] == 1'b1 )
583
       rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
584
     if ( wb_sel_i [2] == 1'b1 )
585
       rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;
586
     if ( wb_sel_i [1] == 1'b1 )
587
       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
588
     if ( wb_sel_i [0] == 1'b1 )
589
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
590
`endif
591
`ifdef GPIO_WB_BYTES3
592
     if ( wb_sel_i [2] == 1'b1 )
593
       rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
594
     if ( wb_sel_i [1] == 1'b1 )
595
       rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
596
     if ( wb_sel_i [0] == 1'b1 )
597
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
598
`endif
599
`ifdef GPIO_WB_BYTES2
600
     if ( wb_sel_i [1] == 1'b1 )
601
       rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
602
     if ( wb_sel_i [0] == 1'b1 )
603
       rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
604
`endif
605
`ifdef GPIO_WB_BYTES1
606
     if ( wb_sel_i [0] == 1'b1 )
607
       rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
608
`endif
609
   end
610
 
611
`else
612
assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG;     // RGPIO_PTRIG = 0x0
613
`endif
614
 
615
//
616
// Write to RGPIO_AUX
617
//
618
`ifdef GPIO_RGPIO_AUX
619
always @(posedge wb_clk_i or posedge wb_rst_i)
620
        if (wb_rst_i)
621
                rgpio_aux <= #1 {gw{1'b0}};
622
        else if (rgpio_aux_sel && wb_we_i)
623
  begin
624
`ifdef GPIO_STRICT_32BIT_ACCESS
625
                rgpio_aux <= #1 wb_dat_i[gw-1:0];
626
`endif
627
 
628
`ifdef GPIO_WB_BYTES4
629
     if ( wb_sel_i [3] == 1'b1 )
630
       rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
631
     if ( wb_sel_i [2] == 1'b1 )
632
       rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;
633
     if ( wb_sel_i [1] == 1'b1 )
634
       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
635
     if ( wb_sel_i [0] == 1'b1 )
636
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
637
`endif
638
`ifdef GPIO_WB_BYTES3
639
     if ( wb_sel_i [2] == 1'b1 )
640
       rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
641
     if ( wb_sel_i [1] == 1'b1 )
642
       rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
643
     if ( wb_sel_i [0] == 1'b1 )
644
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
645
`endif
646
`ifdef GPIO_WB_BYTES2
647
     if ( wb_sel_i [1] == 1'b1 )
648
       rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
649
     if ( wb_sel_i [0] == 1'b1 )
650
       rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
651
`endif
652
`ifdef GPIO_WB_BYTES1
653
     if ( wb_sel_i [0] == 1'b1 )
654
       rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
655
`endif
656
   end
657
 
658
`else
659
assign rgpio_aux = `GPIO_DEF_RGPIO_AUX; // RGPIO_AUX = 0x0
660
`endif
661
 
662
 
663
//
664
// Write to RGPIO_ECLK
665
//
666
`ifdef GPIO_RGPIO_ECLK
667
always @(posedge wb_clk_i or posedge wb_rst_i)
668
        if (wb_rst_i)
669
                rgpio_eclk <= #1 {gw{1'b0}};
670
        else if (rgpio_eclk_sel && wb_we_i)
671
  begin
672
`ifdef GPIO_STRICT_32BIT_ACCESS
673
                rgpio_eclk <= #1 wb_dat_i[gw-1:0];
674
`endif
675
 
676
`ifdef GPIO_WB_BYTES4
677
     if ( wb_sel_i [3] == 1'b1 )
678
       rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
679
     if ( wb_sel_i [2] == 1'b1 )
680
       rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ;
681
     if ( wb_sel_i [1] == 1'b1 )
682
       rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
683
     if ( wb_sel_i [0] == 1'b1 )
684
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
685
`endif
686
`ifdef GPIO_WB_BYTES3
687
     if ( wb_sel_i [2] == 1'b1 )
688
       rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
689
     if ( wb_sel_i [1] == 1'b1 )
690
       rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
691
     if ( wb_sel_i [0] == 1'b1 )
692
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
693
`endif
694
`ifdef GPIO_WB_BYTES2
695
     if ( wb_sel_i [1] == 1'b1 )
696
       rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
697
     if ( wb_sel_i [0] == 1'b1 )
698
       rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
699
`endif
700
`ifdef GPIO_WB_BYTES1
701
     if ( wb_sel_i [0] == 1'b1 )
702
       rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
703
`endif
704
   end
705
 
706
 
707
`else
708
assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK;       // RGPIO_ECLK = 0x0
709
`endif
710
 
711
 
712
 
713
//
714
// Write to RGPIO_NEC
715
//
716
`ifdef GPIO_RGPIO_NEC
717
always @(posedge wb_clk_i or posedge wb_rst_i)
718
        if (wb_rst_i)
719
                rgpio_nec <= #1 {gw{1'b0}};
720
        else if (rgpio_nec_sel && wb_we_i)
721
  begin
722
`ifdef GPIO_STRICT_32BIT_ACCESS
723
                rgpio_nec <= #1 wb_dat_i[gw-1:0];
724
`endif
725
 
726
`ifdef GPIO_WB_BYTES4
727
     if ( wb_sel_i [3] == 1'b1 )
728
       rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
729
     if ( wb_sel_i [2] == 1'b1 )
730
       rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ;
731
     if ( wb_sel_i [1] == 1'b1 )
732
       rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
733
     if ( wb_sel_i [0] == 1'b1 )
734
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
735
`endif
736
`ifdef GPIO_WB_BYTES3
737
     if ( wb_sel_i [2] == 1'b1 )
738
       rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
739
     if ( wb_sel_i [1] == 1'b1 )
740
       rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
741
     if ( wb_sel_i [0] == 1'b1 )
742
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
743
`endif
744
`ifdef GPIO_WB_BYTES2
745
     if ( wb_sel_i [1] == 1'b1 )
746
       rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
747
     if ( wb_sel_i [0] == 1'b1 )
748
       rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
749
`endif
750
`ifdef GPIO_WB_BYTES1
751
     if ( wb_sel_i [0] == 1'b1 )
752
       rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
753
`endif
754
   end
755
 
756
 
757
`else
758
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0
759
`endif
760
 
761
//
762
// synchronize inputs to systam clock
763
//
764
`ifdef  GPIO_SYNC_IN_WB
765
always @(posedge wb_clk_i or posedge wb_rst_i)
766
  if (wb_rst_i) begin
767
    sync      <= #1 {gw{1'b0}} ;
768
    ext_pad_s <= #1 {gw{1'b0}} ;
769
  end else begin
770
    sync      <= #1 ext_pad_i  ;
771
    ext_pad_s <= #1 sync       ;
772
  end
773
`else
774
assign  ext_pad_s = ext_pad_i;
775
`endif // GPIO_SYNC_IN_WB
776
 
777
//
778
// Latch into RGPIO_IN
779
//
780
`ifdef GPIO_RGPIO_IN
781
always @(posedge wb_clk_i or posedge wb_rst_i)
782
        if (wb_rst_i)
783
                rgpio_in <= #1 {gw{1'b0}};
784
        else
785
                rgpio_in <= #1 in_muxed;
786
`else
787
assign rgpio_in = in_muxed;
788
`endif
789
 
790
`ifdef GPIO_CLKPAD
791
 
792
`ifdef GPIO_SYNC_CLK_WB
793
//
794
// external clock enabled
795
// synchronized to system clock
796
// (one clock domain)
797
//
798
 
799
reg  sync_clk,
800
     clk_s   ,
801
     clk_r   ;
802
wire pedge   ,
803
     nedge   ;
804
wire [gw-1:0] pedge_vec   ,
805
              nedge_vec   ;
806
wire [gw-1:0] in_lach     ;
807
 
808
assign pedge =  clk_s & !clk_r ;
809
assign nedge = !clk_s &  clk_r ;
810
assign pedge_vec = {gw{pedge}} ;
811
assign nedge_vec = {gw{nedge}} ;
812
 
813
assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ;
814
assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ;
815
 
816
always @(posedge wb_clk_i or posedge wb_rst_i)
817
  if (wb_rst_i) begin
818
    sync_clk <= #1 1'b0 ;
819
    clk_s    <= #1 1'b0 ;
820
    clk_r    <= #1 1'b0 ;
821
  end else begin
822
    sync_clk <= #1 clk_pad_i ;
823
    clk_s    <= #1 sync_clk  ;
824
    clk_r    <= #1 clk_s     ;
825
  end
826
 
827
always @(posedge wb_clk_i or posedge wb_rst_i)
828
  if (wb_rst_i) begin
829
    pextc_sampled <= #1 {gw{1'b0}};
830
  end else begin
831
    pextc_sampled <= #1 extc_in ;
832
  end
833
 
834
assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ;
835
 
836
`else
837
//
838
// external clock enabled
839
// not  synchronized to system clock
840
// (two clock domains)
841
//
842
 
843
`ifdef GPIO_SYNC_IN_CLK_WB
844
 
845
reg [gw-1:0] syn_extc  ,
846
             extc_s    ;
847
 
848
always @(posedge wb_clk_i or posedge wb_rst_i)
849
  if (wb_rst_i) begin
850
    syn_extc  <= #1 {gw{1'b0}};
851
    extc_s    <= #1 {gw{1'b0}};
852
  end else begin
853
    syn_extc  <= #1 extc_in ;
854
    extc_s    <= #1 syn_extc;
855
  end
856
 
857
`else
858
 
859
wire [gw-1:0] extc_s   ;
860
assign extc_s = syn_extc ;
861
 
862
`endif // GPIO_SYNC_IN_CLK_WB
863
 
864
`ifdef GPIO_SYNC_IN_CLK
865
reg [gw-1:0] syn_pclk    ,
866
             ext_pad_spc ;
867
 
868
always @(posedge clk_pad_i or posedge wb_rst_i)
869
  if (wb_rst_i) begin
870
    syn_pclk    <= #1 {gw{1'b0}} ;
871
    ext_pad_spc <= #1 {gw{1'b0}} ;
872
  end else begin
873
    syn_pclk    <= #1 ext_pad_i ;
874
    ext_pad_spc <= #1 syn_pclk  ;
875
  end
876
 
877
`else
878
 
879
wire [gw-1:0] ext_pad_spc      ;
880
assign ext_pad_spc = ext_pad_i ;
881
 
882
`endif // GPIO_SYNC_IN_CLK
883
 
884
always @(posedge clk_pad_i or posedge wb_rst_i)
885
  if (wb_rst_i) begin
886
    pextc_sampled <= #1 {gw{1'b0}};
887
  end else begin
888
    pextc_sampled <= #1 ext_pad_spc ;
889
  end
890
 
891
 
892
`ifdef GPIO_NO_NEGEDGE_FLOPS
893
 
894
`ifdef GPIO_NO_CLKPAD_LOGIC
895
 
896
assign extc_in = pextc_sampled;
897
 
898
`else
899
 
900
wire  clk_n;
901
assign clk_n = !clk_pad_i;
902
 
903
`ifdef GPIO_SYNC_IN_CLK
904
reg [gw-1:0] syn_nclk    ,
905
             ext_pad_snc ;
906
 
907
always @(posedge clk_n or posedge wb_rst_i)
908
  if (wb_rst_i) begin
909
    syn_nclk    <= #1 {gw{1'b0}} ;
910
    ext_pad_snc <= #1 {gw{1'b0}} ;
911
  end else begin
912
    syn_nclk    <= #1 ext_pad_i ;
913
    ext_pad_snc <= #1 syn_nclk  ;
914
  end
915
 
916
`else
917
 
918
wire [gw-1:0] ext_pad_snc      ;
919
assign ext_pad_snc = ext_pad_i ;
920
 
921
`endif // GPIO_SYNC_IN_CLK
922
 
923
always @(posedge clk_n or posedge wb_rst_i)
924
  if (wb_rst_i) begin
925
    nextc_sampled <= #1 {gw{1'b0}};
926
  end else begin
927
    nextc_sampled <= #1 ext_pad_snc ;
928
  end
929
 
930
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
931
 
932
`endif //  GPIO_NO_CLKPAD_LOGIC
933
 
934
 
935
`else
936
 
937
`ifdef GPIO_SYNC_IN_CLK
938
reg [gw-1:0] syn_nclk    ,
939
             ext_pad_snc ;
940
 
941
always @(negedge clk_n or posedge wb_rst_i)
942
  if (wb_rst_i) begin
943
    syn_nclk    <= #1 {gw{1'b0}} ;
944
    ext_pad_snc <= #1 {gw{1'b0}} ;
945
  end else begin
946
    syn_nclk    <= #1 ext_pad_i ;
947
    ext_pad_snc <= #1 syn_nclk  ;
948
  end
949
 
950
`else
951
 
952
wire [gw-1:0] ext_pad_snc      ;
953
assign ext_pad_snc = ext_pad_i ;
954
 
955
`endif // GPIO_SYNC_IN_CLK
956
 
957
always @(negedge clk_pad_i or posedge wb_rst_i)
958
  if (wb_rst_i) begin
959
    nextc_sampled <= #1 {gw{1'b0}};
960
  end else begin
961
    nextc_sampled <= #1 ext_pad_snc ;
962
  end
963
 
964
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
965
 
966
`endif //  GPIO_NO_NEGEDGE_FLOPS
967
 
968
assign in_muxed = (rgpio_eclk & extc_s)      | (~rgpio_eclk & ext_pad_s) ;
969
 
970
 
971
`endif //  GPIO_SYNC_CLK_WB
972
 
973
 
974
`else
975
 
976
assign  in_muxed  = ext_pad_s ;
977
 
978
`endif //  GPIO_CLKPAD
979
 
980
 
981
 
982
//
983
// Mux all registers when doing a read of GPIO registers
984
//
985
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
986
                rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec)
987
        case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
988
`ifdef GPIO_READREGS
989
  `ifdef GPIO_RGPIO_OUT
990
        `GPIO_RGPIO_OUT: begin
991
                        wb_dat[dw-1:0] = rgpio_out;
992
                end
993
  `endif
994
  `ifdef GPIO_RGPIO_OE
995
                `GPIO_RGPIO_OE: begin
996
                        wb_dat[dw-1:0] = rgpio_oe;
997
                end
998
  `endif
999
  `ifdef GPIO_RGPIO_INTE
1000
                `GPIO_RGPIO_INTE: begin
1001
                        wb_dat[dw-1:0] = rgpio_inte;
1002
                end
1003
  `endif
1004
  `ifdef GPIO_RGPIO_PTRIG
1005
                `GPIO_RGPIO_PTRIG: begin
1006
                        wb_dat[dw-1:0] = rgpio_ptrig;
1007
                end
1008
  `endif
1009
  `ifdef GPIO_RGPIO_NEC
1010
                `GPIO_RGPIO_NEC: begin
1011
                        wb_dat[dw-1:0] = rgpio_nec;
1012
                end
1013
  `endif
1014
  `ifdef GPIO_RGPIO_ECLK
1015
                `GPIO_RGPIO_ECLK: begin
1016
                        wb_dat[dw-1:0] = rgpio_eclk;
1017
                end
1018
  `endif
1019
  `ifdef GPIO_RGPIO_AUX
1020
                `GPIO_RGPIO_AUX: begin
1021
                        wb_dat[dw-1:0] = rgpio_aux;
1022
                end
1023
  `endif
1024
  `ifdef GPIO_RGPIO_CTRL
1025
                `GPIO_RGPIO_CTRL: begin
1026
                        wb_dat[1:0] = rgpio_ctrl;
1027
                        wb_dat[dw-1:2] = {dw-2{1'b0}};
1028
                end
1029
  `endif
1030
`endif
1031
  `ifdef GPIO_RGPIO_INTS
1032
                `GPIO_RGPIO_INTS: begin
1033
                        wb_dat[dw-1:0] = rgpio_ints;
1034
                end
1035
  `endif
1036
                default: begin
1037
                        wb_dat[dw-1:0] = rgpio_in;
1038
                end
1039
        endcase
1040
 
1041
//
1042
// WB data output
1043
//
1044
`ifdef GPIO_REGISTERED_WB_OUTPUTS
1045
always @(posedge wb_clk_i or posedge wb_rst_i)
1046
        if (wb_rst_i)
1047
                wb_dat_o <= #1 {dw{1'b0}};
1048
        else
1049
                wb_dat_o <= #1 wb_dat;
1050
`else
1051
assign wb_dat_o = wb_dat;
1052
`endif
1053
 
1054
//
1055
// RGPIO_INTS
1056
//
1057
`ifdef GPIO_RGPIO_INTS
1058
always @(posedge wb_clk_i or posedge wb_rst_i)
1059
        if (wb_rst_i)
1060
                rgpio_ints <= #1 {gw{1'b0}};
1061
        else if (rgpio_ints_sel && wb_we_i)
1062
                rgpio_ints <= #1 wb_dat_i[gw-1:0];
1063
        else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
1064
                rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
1065
`else
1066
assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
1067
`endif
1068
 
1069
//
1070
// Generate interrupt request
1071
//
1072
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
1073
 
1074
//
1075
// Optional registration of WB interrupt
1076
//
1077
`ifdef GPIO_REGISTERED_WB_OUTPUTS
1078
always @(posedge wb_clk_i or posedge wb_rst_i)
1079
        if (wb_rst_i)
1080
                wb_inta_o <= #1 1'b0;
1081
        else
1082
                wb_inta_o <= #1 wb_inta;
1083
`else
1084
assign wb_inta_o = wb_inta;
1085
`endif // GPIO_REGISTERED_WB_OUTPUTS
1086
 
1087
//
1088
// Output enables are RGPIO_OE bits
1089
//
1090
assign ext_padoe_o = rgpio_oe;
1091
 
1092
//
1093
// Generate GPIO outputs
1094
//
1095
`ifdef GPIO_AUX_IMPLEMENT
1096
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
1097
`else
1098
assign out_pad = rgpio_out ;
1099
`endif //  GPIO_AUX_IMPLEMENT
1100
 
1101
//
1102
// Optional registration of GPIO outputs
1103
//
1104
`ifdef GPIO_REGISTERED_IO_OUTPUTS
1105
always @(posedge wb_clk_i or posedge wb_rst_i)
1106
        if (wb_rst_i)
1107
                ext_pad_o <= #1 {gw{1'b0}};
1108
        else
1109
                ext_pad_o <= #1 out_pad;
1110
`else
1111
assign ext_pad_o = out_pad;
1112
`endif // GPIO_REGISTERED_IO_OUTPUTS
1113
 
1114
 
1115
`else
1116
 
1117
//
1118
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
1119
// is cleared and WISHBONE transfers complete with errors
1120
//
1121
assign wb_inta_o = 1'b0;
1122
assign wb_ack_o = 1'b0;
1123
assign wb_err_o = wb_cyc_i & wb_stb_i;
1124
assign ext_padoe_o = {gw{1'b1}};
1125
assign ext_pad_o = {gw{1'b0}};
1126
 
1127
//
1128
// Read GPIO registers
1129
//
1130
assign wb_dat_o = {dw{1'b0}};
1131
 
1132
`endif //  GPIO_IMPLEMENTED
1133
 
1134
endmodule
1135
 

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