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[/] [minsoc/] [trunk/] [utils/] [contributions/] [gpio/] [rtl/] [minsoc_defines.v] - Blame information for rev 40

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Line No. Rev Author Line
1 40 rfajardo
//
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// Define FPGA manufacturer
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//
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//`define GENERIC_FPGA
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//`define ALTERA_FPGA
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`define XILINX_FPGA
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// 
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// Define FPGA Model (comment all out for ALTERA)
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//
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//`define SPARTAN2
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//`define SPARTAN3
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//`define SPARTAN3E
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`define SPARTAN3A
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//`define VIRTEX
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//`define VIRTEX2
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//`define VIRTEX4
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//`define VIRTEX5
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//
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// Memory
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//
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`define MEMORY_ADR_WIDTH   13   //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12, memory is composed by blocks of address width 11
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                                                                //Address width of memory -> select memory depth, 2 powers MEMORY_ADR_WIDTH defines the memory depth 
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                                                                //the memory data width is 32 bit, memory amount in Bytes = 4*memory depth
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//
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// Memory type  (uncomment something if ASIC or generic memory)
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//
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//`define GENERIC_MEMORY
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//`define AVANT_ATP
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//`define VIRAGE_SSP
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//`define VIRTUALSILICON_SSP
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//
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// TAP selection
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//
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//`define GENERIC_TAP
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`define FPGA_TAP
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//
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// Clock Division selection
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//
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//`define NO_CLOCK_DIVISION
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//`define GENERIC_CLOCK_DIVISION
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`define FPGA_CLOCK_DIVISION             //Altera ALTPLL is not implemented, didn't find the code for its verilog instantiation
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                                                                //if you selected altera and this, the GENERIC_CLOCK_DIVISION will be automatically taken
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//
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// Define division
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//
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`define CLOCK_DIVISOR 5         //in case of GENERIC_CLOCK_DIVISION the real value will be rounded down to an even value
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                                                        //in FPGA case, check minsoc_clock_manager for allowed divisors
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                                                        //DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION INSTEAD
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//
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// Reset polarity
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//
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//`define NEGATIVE_RESET;      //rstn
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`define POSITIVE_RESET;      //rst
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//
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// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
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//
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//`define START_UP
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//
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// Connected modules
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//
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`define UART
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//`define ETHERNET
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`define GPIO
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//
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// Ethernet reset
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//
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//`define ETH_RESET     1'b0
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`define ETH_RESET       1'b1
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//
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// GPIO Pins
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//
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`define GPIO_HAS_INPUT_PINS
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//`define GPIO_HAS_OUTPUT_PINS
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`define GPIO_HAS_BIDIR_PINS
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`define GPIO_NUM_INPUT          4'd8
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`define GPIO_NUM_OUTPUT         4'd0
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`define GPIO_NUM_BIDIR          4'd8
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//
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// Interrupts
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//
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`define APP_INT_RES1    1:0
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`define APP_INT_UART    2
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`define APP_INT_RES2    3
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`define APP_INT_ETH     4
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`define APP_INT_PS2     5
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`define APP_INT_GPIO 6
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`define APP_INT_RES3    19:7
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//
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// Address map
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//
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`define APP_ADDR_DEC_W  8
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`define APP_ADDR_SRAM   `APP_ADDR_DEC_W'h00
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`define APP_ADDR_FLASH  `APP_ADDR_DEC_W'h04
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`define APP_ADDR_DECP_W  4
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`define APP_ADDR_PERIP  `APP_ADDR_DECP_W'h9
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`define APP_ADDR_SPI    `APP_ADDR_DEC_W'h97
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`define APP_ADDR_ETH    `APP_ADDR_DEC_W'h92
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`define APP_ADDR_AUDIO  `APP_ADDR_DEC_W'h9d
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`define APP_ADDR_UART   `APP_ADDR_DEC_W'h90
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`define APP_ADDR_PS2    `APP_ADDR_DEC_W'h94
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`define APP_ADDR_GPIO   `APP_ADDR_DEC_W'h9e
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`define APP_ADDR_RES2   `APP_ADDR_DEC_W'h9f
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//
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// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
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// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
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//
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`ifdef GENERIC_FPGA
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        `define GENERIC_TAP
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        `define GENERIC_MEMORY
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        `ifndef NO_CLOCK_DIVISION
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                `define GENERIC_CLOCK_DIVISION
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        `endif
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`endif

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