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[/] [minsoc/] [trunk/] [utils/] [contributions/] [gpio/] [rtl/] [minsoc_top.ucf] - Blame information for rev 40

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Line No. Rev Author Line
1 40 rfajardo
 
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NET "clk" LOC = E12;    # 50 MHz on-board clock oscillator
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NET "reset" LOC = T14;  # Push Button BTN_NORTH
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# UART Peripheral
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NET "uart_stx" LOC = E15;    # RS232 Serial port ( DTE Connector )
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NET "uart_srx" LOC = F16;    #
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# GPIO
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NET "io_pins<0>" LOC = R20;
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NET "io_pins<1>" LOC = T19;
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NET "io_pins<2>" LOC = U20;
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NET "io_pins<3>" LOC = U19;
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NET "io_pins<4>" LOC = V19;
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NET "io_pins<5>" LOC = V20;
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NET "io_pins<6>" LOC = Y22;
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NET "io_pins<7>" LOC = W21;
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NET "i_pins<0>" LOC = V8;
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NET "i_pins<1>" LOC = U10;
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NET "i_pins<2>" LOC = U8;
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NET "i_pins<3>" LOC = T9;
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NET "i_pins<4>" LOC = T16;
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NET "i_pins<5>" LOC = U15;
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#NET "i_pins<6>" LOC = ;
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NET "i_pins<7>" LOC = T15;
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#################################################################################
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#    Pin constraints including the IOSTANDARD and DRIVE
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#    Reference : Spartan-3A/3AN FPGA Starter Kit Board User Guide ( UG334 v1.1 )
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#################################################################################
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#NET "clk" LOC = E12 | IOSTANDARD = LVCMOS33;
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#NET "uart_stx" LOC = E15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
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#NET "uart_srx" LOC = F16 | IOSTANDARD = LVCMOS33;
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#NET "reset" LOC = T14 | IOSTANDARD = LVCMOS33 | PULLDOWN ;

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