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[/] [minsoc/] [trunk/] [utils/] [contributions/] [gpio/] [rtl/] [minsoc_top.v] - Blame information for rev 40

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1 40 rfajardo
`include "minsoc_defines.v"
2
`include "or1200_defines.v"
3
 
4
`include "gpio_defines.v"
5
 
6
module minsoc_top (
7
   clk,reset
8
 
9
   //JTAG ports
10
`ifdef GENERIC_TAP
11
   , jtag_tdi,jtag_tms,jtag_tck,
12
   jtag_tdo,jtag_vref,jtag_gnd
13
`endif
14
 
15
   //SPI ports
16
`ifdef START_UP
17
   , spi_flash_mosi, spi_flash_miso, spi_flash_sclk, spi_flash_ss
18
`endif
19
 
20
   //UART ports
21
`ifdef UART
22
   , uart_stx,uart_srx
23
`endif
24
 
25
        // Ethernet ports
26
`ifdef ETHERNET
27
        , eth_col, eth_crs, eth_trste, eth_tx_clk,
28
        eth_tx_en, eth_tx_er, eth_txd, eth_rx_clk,
29
        eth_rx_dv, eth_rx_er, eth_rxd, eth_fds_mdint,
30
        eth_mdc, eth_mdio
31
`endif
32
 
33
        // GPIO ports
34
`ifdef GPIO
35
    `ifdef GPIO_HAS_INPUT_PINS
36
             ,i_pins
37
         `endif
38
         `ifdef GPIO_HAS_OUTPUT_PINS
39
                  ,o_pins
40
         `endif
41
         `ifdef GPIO_HAS_BIDIR_PINS
42
                  ,io_pins
43
         `endif
44
`endif
45
);
46
 
47
//
48
// I/O Ports
49
//
50
 
51
   input         clk;
52
   input         reset;
53
 
54
//
55
// SPI controller external i/f wires
56
//
57
`ifdef START_UP
58
output spi_flash_mosi;
59
input spi_flash_miso;
60
output spi_flash_sclk;
61
output [1:0] spi_flash_ss;
62
`endif
63
 
64
//
65
// UART
66
//
67
`ifdef UART
68
   output        uart_stx;
69
   input         uart_srx;
70
`endif
71
 
72
//
73
// Ethernet
74
//
75
`ifdef ETHERNET
76
output                  eth_tx_er;
77
input                   eth_tx_clk;
78
output                  eth_tx_en;
79
output  [3:0]            eth_txd;
80
input                   eth_rx_er;
81
input                   eth_rx_clk;
82
input                   eth_rx_dv;
83
input   [3:0]            eth_rxd;
84
input                   eth_col;
85
input                   eth_crs;
86
output                  eth_trste;
87
input                   eth_fds_mdint;
88
inout                   eth_mdio;
89
output                  eth_mdc;
90
`endif
91
 
92
//
93
// GPIO
94
//
95
`ifdef GPIO
96
    `ifdef GPIO_HAS_INPUT_PINS
97
        input [`GPIO_NUM_INPUT-1:0] i_pins;
98
         `endif
99
         `ifdef GPIO_HAS_OUTPUT_PINS
100
        output [`GPIO_NUM_OUTPUT-1:0] o_pins;
101
         `endif
102
         `ifdef GPIO_HAS_BIDIR_PINS
103
        inout [`GPIO_NUM_BIDIR-1:0] io_pins;
104
         `endif
105
`endif
106
 
107
//
108
// JTAG
109
//
110
`ifdef GENERIC_TAP
111
   input         jtag_tdi;
112
   input         jtag_tms;
113
   input         jtag_tck;
114
   output        jtag_tdo;
115
   output        jtag_vref;
116
   output        jtag_gnd;
117
 
118
 
119
assign jtag_vref = 1'b1;
120
assign jtag_gnd = 1'b0;
121
`endif
122
 
123
wire rstn;
124
 
125
`ifdef POSITIVE_RESET
126
assign rstn = ~reset;
127
`elsif NEGATIVE_RESET
128
assign rstn = reset;
129
`endif
130
 
131
//
132
// Internal wires
133
//
134
 
135
//
136
// Debug core master i/f wires
137
//
138
wire    [31:0]           wb_dm_adr_o;
139
wire    [31:0]           wb_dm_dat_i;
140
wire    [31:0]           wb_dm_dat_o;
141
wire    [3:0]            wb_dm_sel_o;
142
wire                    wb_dm_we_o;
143
wire                    wb_dm_stb_o;
144
wire                    wb_dm_cyc_o;
145
wire                    wb_dm_ack_i;
146
wire                    wb_dm_err_i;
147
 
148
//
149
// Debug <-> RISC wires
150
//
151
wire    [3:0]            dbg_lss;
152
wire    [1:0]            dbg_is;
153
wire    [10:0]           dbg_wp;
154
wire                    dbg_bp;
155
wire    [31:0]           dbg_dat_dbg;
156
wire    [31:0]           dbg_dat_risc;
157
wire    [31:0]           dbg_adr;
158
wire                    dbg_ewt;
159
wire                    dbg_stall;
160
wire    [2:0]            dbg_op;     //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb  (didn't change for backward compatibility with DBG_IF_MODEL
161
wire                    dbg_ack;
162
 
163
//
164
// RISC instruction master i/f wires
165
//
166
wire    [31:0]           wb_rim_adr_o;
167
wire                    wb_rim_cyc_o;
168
wire    [31:0]           wb_rim_dat_i;
169
wire    [31:0]           wb_rim_dat_o;
170
wire    [3:0]            wb_rim_sel_o;
171
wire                    wb_rim_ack_i;
172
wire                    wb_rim_err_i;
173
wire                    wb_rim_rty_i = 1'b0;
174
wire                    wb_rim_we_o;
175
wire                    wb_rim_stb_o;
176
wire    [31:0]           wb_rif_dat_i;
177
wire                    wb_rif_ack_i;
178
 
179
//
180
// RISC data master i/f wires
181
//
182
wire    [31:0]           wb_rdm_adr_o;
183
wire                    wb_rdm_cyc_o;
184
wire    [31:0]           wb_rdm_dat_i;
185
wire    [31:0]           wb_rdm_dat_o;
186
wire    [3:0]            wb_rdm_sel_o;
187
wire                    wb_rdm_ack_i;
188
wire                    wb_rdm_err_i;
189
wire                    wb_rdm_rty_i = 1'b0;
190
wire                    wb_rdm_we_o;
191
wire                    wb_rdm_stb_o;
192
 
193
//
194
// RISC misc
195
//
196
wire    [19:0]           pic_ints;
197
 
198
//
199
// Flash controller slave i/f wires
200
//
201
wire    [31:0]           wb_fs_dat_i;
202
wire    [31:0]           wb_fs_dat_o;
203
wire    [31:0]           wb_fs_adr_i;
204
wire    [3:0]            wb_fs_sel_i;
205
wire                    wb_fs_we_i;
206
wire                    wb_fs_cyc_i;
207
wire                    wb_fs_stb_i;
208
wire                    wb_fs_ack_o;
209
wire                    wb_fs_err_o;
210
 
211
//
212
// SPI controller slave i/f wires
213
//
214
wire    [31:0]           wb_sp_dat_i;
215
wire    [31:0]           wb_sp_dat_o;
216
wire    [31:0]           wb_sp_adr_i;
217
wire    [3:0]            wb_sp_sel_i;
218
wire                    wb_sp_we_i;
219
wire                    wb_sp_cyc_i;
220
wire                    wb_sp_stb_i;
221
wire                    wb_sp_ack_o;
222
wire                    wb_sp_err_o;
223
 
224
//
225
// SPI controller external i/f wires
226
//
227
wire spi_flash_mosi;
228
wire spi_flash_miso;
229
wire spi_flash_sclk;
230
wire [1:0] spi_flash_ss;
231
 
232
//
233
// SRAM controller slave i/f wires
234
//
235
wire    [31:0]           wb_ss_dat_i;
236
wire    [31:0]           wb_ss_dat_o;
237
wire    [31:0]           wb_ss_adr_i;
238
wire    [3:0]            wb_ss_sel_i;
239
wire                    wb_ss_we_i;
240
wire                    wb_ss_cyc_i;
241
wire                    wb_ss_stb_i;
242
wire                    wb_ss_ack_o;
243
wire                    wb_ss_err_o;
244
 
245
//
246
// Ethernet core master i/f wires
247
//
248
wire    [31:0]           wb_em_adr_o;
249
wire    [31:0]           wb_em_dat_i;
250
wire    [31:0]           wb_em_dat_o;
251
wire    [3:0]            wb_em_sel_o;
252
wire                    wb_em_we_o;
253
wire                    wb_em_stb_o;
254
wire                    wb_em_cyc_o;
255
wire                    wb_em_ack_i;
256
wire                    wb_em_err_i;
257
 
258
//
259
// Ethernet core slave i/f wires
260
//
261
wire    [31:0]           wb_es_dat_i;
262
wire    [31:0]           wb_es_dat_o;
263
wire    [31:0]           wb_es_adr_i;
264
wire    [3:0]            wb_es_sel_i;
265
wire                    wb_es_we_i;
266
wire                    wb_es_cyc_i;
267
wire                    wb_es_stb_i;
268
wire                    wb_es_ack_o;
269
wire                    wb_es_err_o;
270
 
271
//
272
// Ethernet external i/f wires
273
//
274
wire                    eth_mdo;
275
wire                    eth_mdoe;
276
 
277
//
278
// UART16550 core slave i/f wires
279
//
280
wire    [31:0]           wb_us_dat_i;
281
wire    [31:0]           wb_us_dat_o;
282
wire    [31:0]           wb_us_adr_i;
283
wire    [3:0]            wb_us_sel_i;
284
wire                    wb_us_we_i;
285
wire                    wb_us_cyc_i;
286
wire                    wb_us_stb_i;
287
wire                    wb_us_ack_o;
288
wire                    wb_us_err_o;
289
 
290
//
291
// UART external i/f wires
292
//
293
wire                    uart_stx;
294
wire                    uart_srx;
295
 
296
//
297
// GPIO core slave i/f wires
298
//
299
wire    [31:0]           wb_gpio_dat_i;
300
wire    [31:0]           wb_gpio_dat_o;
301
wire    [31:0]           wb_gpio_adr_i;
302
wire    [3:0]            wb_gpio_sel_i;
303
wire                    wb_gpio_we_i;
304
wire                    wb_gpio_cyc_i;
305
wire                    wb_gpio_stb_i;
306
wire                    wb_gpio_ack_o;
307
wire                    wb_gpio_err_o;
308
 
309
//
310
// Interface to GPIO core - Device specific core
311
//
312
wire [`GPIO_IOS:0]       ext_pad_o;
313
wire [`GPIO_IOS:0]       ext_pad_i;
314
wire [`GPIO_IOS:0]       ext_pad_oe_o;
315
 
316
//
317
// Reset debounce
318
//
319
reg                     rst_r;
320
reg                     wb_rst;
321
 
322
//
323
// Global clock
324
//
325
wire                    wb_clk;
326
 
327
//
328
// Reset debounce
329
//
330
always @(posedge wb_clk or negedge rstn)
331
        if (~rstn)
332
                rst_r <= 1'b1;
333
        else
334
                rst_r <= #1 1'b0;
335
 
336
//
337
// Reset debounce
338
//
339
always @(posedge wb_clk)
340
        wb_rst <= #1 rst_r;
341
 
342
//
343
// Clock Divider
344
//
345
minsoc_clock_manager #
346
(
347
   .divisor(`CLOCK_DIVISOR)
348
)
349
clk_adjust (
350
        .clk_i(clk),
351
        .clk_o(wb_clk)
352
);
353
 
354
//
355
// Unused WISHBONE signals
356
//
357
assign wb_us_err_o = 1'b0;
358
assign wb_fs_err_o = 1'b0;
359
assign wb_sp_err_o = 1'b0;
360
 
361
//
362
// Unused interrupts
363
//
364
assign pic_ints[`APP_INT_RES1] = 'b0;
365
assign pic_ints[`APP_INT_RES2] = 'b0;
366
assign pic_ints[`APP_INT_RES3] = 'b0;
367
assign pic_ints[`APP_INT_PS2] = 'b0;
368
 
369
//
370
// Ethernet tri-state
371
//
372
`ifdef ETHERNET
373
assign eth_mdio = eth_mdoe ? eth_mdo : 1'bz;
374
assign eth_trste = `ETH_RESET;
375
`endif
376
 
377
 
378
//
379
// RISC Instruction address for Flash
380
//
381
// Until first access to real Flash area,
382
// CPU instruction is fixed to jump to the Flash area.
383
// After Flash area is accessed, CPU instructions 
384
// come from the tc_top (wishbone "switch").
385
//
386
`ifdef START_UP
387
reg jump_flash;
388
reg [3:0] rif_counter;
389
reg [31:0] rif_dat_int;
390
reg rif_ack_int;
391
 
392
always @(posedge wb_clk or negedge rstn)
393
begin
394
        if (!rstn) begin
395
                jump_flash <= #1 1'b1;
396
                rif_counter <= 4'h0;
397
                rif_ack_int <= 1'b0;
398
        end
399
        else begin
400
                rif_ack_int <= 1'b0;
401
 
402
                if (wb_rim_cyc_o && (wb_rim_adr_o[31:32-`APP_ADDR_DEC_W] == `APP_ADDR_FLASH))
403
                        jump_flash <= #1 1'b0;
404
 
405
                if ( jump_flash == 1'b1 ) begin
406
                        if ( wb_rim_cyc_o && wb_rim_stb_o && ~wb_rim_we_o ) begin
407
                                rif_counter <= rif_counter + 1'b1;
408
                                rif_ack_int <= 1'b1;
409
                        end
410
                end
411
        end
412
end
413
 
414
always @ (rif_counter)
415
begin
416
        case ( rif_counter )
417
                4'h0: rif_dat_int = { `OR1200_OR32_MOVHI , 5'h01 , 4'h0 , 1'b0 , `APP_ADDR_FLASH , 8'h00 };
418
                4'h1: rif_dat_int = { `OR1200_OR32_ORI , 5'h01 , 5'h01 , 16'h0000 };
419
                4'h2: rif_dat_int = { `OR1200_OR32_JR , 10'h000 , 5'h01 , 11'h000 };
420
                4'h3: rif_dat_int = { `OR1200_OR32_NOP , 10'h000 , 16'h0000 };
421
                default: rif_dat_int = 32'h0000_0000;
422
        endcase
423
end
424
 
425
assign wb_rif_dat_i = jump_flash ? rif_dat_int : wb_rim_dat_i;
426
 
427
assign wb_rif_ack_i = jump_flash ? rif_ack_int : wb_rim_ack_i;
428
 
429
`else
430
assign wb_rif_dat_i = wb_rim_dat_i;
431
assign wb_rif_ack_i = wb_rim_ack_i;
432
`endif
433
 
434
 
435
//
436
// TAP<->dbg_interface
437
//      
438
wire jtag_tck;
439
wire debug_tdi;
440
wire debug_tdo;
441
wire capture_dr;
442
wire shift_dr;
443
wire pause_dr;
444
wire update_dr;
445
 
446
wire debug_select;
447
wire test_logic_reset;
448
 
449
//
450
// Instantiation of the development i/f
451
//
452
adbg_top dbg_top  (
453
 
454
        // JTAG pins
455
      .tck_i    ( jtag_tck ),
456
      .tdi_i    ( debug_tdi ),
457
      .tdo_o    ( debug_tdo ),
458
      .rst_i    ( test_logic_reset ),           //cable without rst
459
 
460
        // Boundary Scan signals
461
      .capture_dr_i ( capture_dr ),
462
      .shift_dr_i  ( shift_dr ),
463
      .pause_dr_i  ( pause_dr ),
464
      .update_dr_i ( update_dr ),
465
 
466
      .debug_select_i( debug_select ),
467
        // WISHBONE common
468
      .wb_clk_i   ( wb_clk ),
469
 
470
      // WISHBONE master interface
471
      .wb_adr_o  ( wb_dm_adr_o ),
472
      .wb_dat_i  ( wb_dm_dat_i ),
473
      .wb_dat_o  ( wb_dm_dat_o ),
474
      .wb_sel_o  ( wb_dm_sel_o ),
475
      .wb_we_o   ( wb_dm_we_o  ),
476
      .wb_stb_o  ( wb_dm_stb_o ),
477
      .wb_cyc_o  ( wb_dm_cyc_o ),
478
      .wb_ack_i  ( wb_dm_ack_i ),
479
      .wb_err_i  ( wb_dm_err_i ),
480
      .wb_cti_o  ( ),
481
      .wb_bte_o  ( ),
482
 
483
      // RISC signals
484
      .cpu0_clk_i  ( wb_clk ),
485
      .cpu0_addr_o ( dbg_adr ),
486
      .cpu0_data_i ( dbg_dat_risc ),
487
      .cpu0_data_o ( dbg_dat_dbg ),
488
      .cpu0_bp_i   ( dbg_bp ),
489
      .cpu0_stall_o( dbg_stall ),
490
      .cpu0_stb_o  ( dbg_op[2] ),
491
      .cpu0_we_o   ( dbg_op[0] ),
492
      .cpu0_ack_i  ( dbg_ack ),
493
      .cpu0_rst_o  ( )
494
 
495
);
496
 
497
//
498
// JTAG TAP controller instantiation
499
//
500
`ifdef GENERIC_TAP
501
tap_top tap_top(
502
         // JTAG pads
503
         .tms_pad_i(jtag_tms),
504
         .tck_pad_i(jtag_tck),
505
         .trstn_pad_i(rstn),
506
         .tdi_pad_i(jtag_tdi),
507
         .tdo_pad_o(jtag_tdo),
508
         .tdo_padoe_o( ),
509
 
510
         // TAP states
511
         .test_logic_reset_o( test_logic_reset ),
512
         .run_test_idle_o(),
513
         .shift_dr_o(shift_dr),
514
         .pause_dr_o(pause_dr),
515
         .update_dr_o(update_dr),
516
         .capture_dr_o(capture_dr),
517
 
518
         // Select signals for boundary scan or mbist
519
         .extest_select_o(),
520
         .sample_preload_select_o(),
521
         .mbist_select_o(),
522
         .debug_select_o(debug_select),
523
 
524
         // TDO signal that is connected to TDI of sub-modules.
525
         .tdi_o(debug_tdi),
526
 
527
         // TDI signals from sub-modules
528
         .debug_tdo_i(debug_tdo),    // from debug module
529
         .bs_chain_tdo_i(1'b0), // from Boundary Scan Chain
530
         .mbist_tdo_i(1'b0)     // from Mbist Chain
531
);
532
`elsif FPGA_TAP
533
`ifdef ALTERA_FPGA
534
altera_virtual_jtag tap_top(
535
        .tck_o(jtag_tck),
536
        .debug_tdo_o(debug_tdo),
537
        .tdi_o(debug_tdi),
538
        .test_logic_reset_o(test_logic_reset),
539
        .run_test_idle_o(),
540
        .shift_dr_o(shift_dr),
541
        .capture_dr_o(capture_dr),
542
        .pause_dr_o(pause_dr),
543
        .update_dr_o(update_dr),
544
        .debug_select_o(debug_select)
545
);
546
`elsif XILINX_FPGA
547
minsoc_xilinx_internal_jtag tap_top(
548
        .tck_o( jtag_tck ),
549
        .debug_tdo_i( debug_tdo ),
550
        .tdi_o( debug_tdi ),
551
 
552
        .test_logic_reset_o( test_logic_reset ),
553
        .run_test_idle_o( ),
554
 
555
        .shift_dr_o( shift_dr ),
556
        .capture_dr_o( capture_dr ),
557
        .pause_dr_o( pause_dr ),
558
        .update_dr_o( update_dr ),
559
        .debug_select_o( debug_select )
560
);
561
`endif // !FPGA_TAP
562
 
563
`endif // !GENERIC_TAP
564
 
565
//
566
// Instantiation of the OR1200 RISC
567
//
568
or1200_top or1200_top (
569
 
570
        // Common
571
        .rst_i          ( wb_rst ),
572
        .clk_i          ( wb_clk ),
573
`ifdef OR1200_CLMODE_1TO2
574
        .clmode_i       ( 2'b01 ),
575
`else
576
`ifdef OR1200_CLMODE_1TO4
577
        .clmode_i       ( 2'b11 ),
578
`else
579
        .clmode_i       ( 2'b00 ),
580
`endif
581
`endif
582
 
583
        // WISHBONE Instruction Master
584
        .iwb_clk_i      ( wb_clk ),
585
        .iwb_rst_i      ( wb_rst ),
586
        .iwb_cyc_o      ( wb_rim_cyc_o ),
587
        .iwb_adr_o      ( wb_rim_adr_o ),
588
        .iwb_dat_i      ( wb_rif_dat_i ),
589
        .iwb_dat_o      ( wb_rim_dat_o ),
590
        .iwb_sel_o      ( wb_rim_sel_o ),
591
        .iwb_ack_i      ( wb_rif_ack_i ),
592
        .iwb_err_i      ( wb_rim_err_i ),
593
        .iwb_rty_i      ( wb_rim_rty_i ),
594
        .iwb_we_o       ( wb_rim_we_o  ),
595
        .iwb_stb_o      ( wb_rim_stb_o ),
596
 
597
        // WISHBONE Data Master
598
        .dwb_clk_i      ( wb_clk ),
599
        .dwb_rst_i      ( wb_rst ),
600
        .dwb_cyc_o      ( wb_rdm_cyc_o ),
601
        .dwb_adr_o      ( wb_rdm_adr_o ),
602
        .dwb_dat_i      ( wb_rdm_dat_i ),
603
        .dwb_dat_o      ( wb_rdm_dat_o ),
604
        .dwb_sel_o      ( wb_rdm_sel_o ),
605
        .dwb_ack_i      ( wb_rdm_ack_i ),
606
        .dwb_err_i      ( wb_rdm_err_i ),
607
        .dwb_rty_i      ( wb_rdm_rty_i ),
608
        .dwb_we_o       ( wb_rdm_we_o  ),
609
        .dwb_stb_o      ( wb_rdm_stb_o ),
610
 
611
        // Debug
612
        .dbg_stall_i    ( dbg_stall ),
613
        .dbg_dat_i      ( dbg_dat_dbg ),
614
        .dbg_adr_i      ( dbg_adr ),
615
        .dbg_ewt_i      ( 1'b0 ),
616
        .dbg_lss_o      ( dbg_lss ),
617
        .dbg_is_o       ( dbg_is ),
618
        .dbg_wp_o       ( dbg_wp ),
619
        .dbg_bp_o       ( dbg_bp ),
620
        .dbg_dat_o      ( dbg_dat_risc ),
621
        .dbg_ack_o      ( dbg_ack ),
622
        .dbg_stb_i      ( dbg_op[2] ),
623
        .dbg_we_i       ( dbg_op[0] ),
624
 
625
        // Power Management
626
        .pm_clksd_o     ( ),
627
        .pm_cpustall_i  ( 1'b0 ),
628
        .pm_dc_gate_o   ( ),
629
        .pm_ic_gate_o   ( ),
630
        .pm_dmmu_gate_o ( ),
631
        .pm_immu_gate_o ( ),
632
        .pm_tt_gate_o   ( ),
633
        .pm_cpu_gate_o  ( ),
634
        .pm_wakeup_o    ( ),
635
        .pm_lvolt_o     ( ),
636
 
637
        // Interrupts
638
        .pic_ints_i     ( pic_ints )
639
);
640
 
641
//
642
// Startup OR1k
643
//
644
`ifdef START_UP
645
OR1K_startup OR1K_startup0
646
(
647
    .wb_adr_i(wb_fs_adr_i[6:2]),
648
    .wb_stb_i(wb_fs_stb_i),
649
    .wb_cyc_i(wb_fs_cyc_i),
650
    .wb_dat_o(wb_fs_dat_o),
651
    .wb_ack_o(wb_fs_ack_o),
652
    .wb_clk(wb_clk),
653
    .wb_rst(wb_rst)
654
);
655
 
656
spi_flash_top #
657
(
658
   .divider(0),
659
   .divider_len(2)
660
)
661
spi_flash_top0
662
(
663
   .wb_clk_i(wb_clk),
664
   .wb_rst_i(wb_rst),
665
   .wb_adr_i(wb_sp_adr_i[4:2]),
666
   .wb_dat_i(wb_sp_dat_i),
667
   .wb_dat_o(wb_sp_dat_o),
668
   .wb_sel_i(wb_sp_sel_i),
669
   .wb_we_i(wb_sp_we_i),
670
   .wb_stb_i(wb_sp_stb_i),
671
   .wb_cyc_i(wb_sp_cyc_i),
672
   .wb_ack_o(wb_sp_ack_o),
673
 
674
   .mosi_pad_o(spi_flash_mosi),
675
   .miso_pad_i(spi_flash_miso),
676
   .sclk_pad_o(spi_flash_sclk),
677
   .ss_pad_o(spi_flash_ss)
678
);
679
`else
680
assign wb_fs_dat_o = 32'h0000_0000;
681
assign wb_fs_ack_o = 1'b0;
682
assign wb_sp_dat_o = 32'h0000_0000;
683
assign wb_sp_ack_o = 1'b0;
684
`endif
685
 
686
//
687
// Instantiation of the SRAM controller
688
//
689
minsoc_onchip_ram_top #
690
(
691
    .adr_width(`MEMORY_ADR_WIDTH)     //16 blocks of 2048 bytes memory 32768
692
)
693
onchip_ram_top (
694
 
695
        // WISHBONE common
696
        .wb_clk_i       ( wb_clk ),
697
        .wb_rst_i       ( wb_rst ),
698
 
699
        // WISHBONE slave
700
        .wb_dat_i       ( wb_ss_dat_i ),
701
        .wb_dat_o       ( wb_ss_dat_o ),
702
        .wb_adr_i       ( wb_ss_adr_i ),
703
        .wb_sel_i       ( wb_ss_sel_i ),
704
        .wb_we_i        ( wb_ss_we_i  ),
705
        .wb_cyc_i       ( wb_ss_cyc_i ),
706
        .wb_stb_i       ( wb_ss_stb_i ),
707
        .wb_ack_o       ( wb_ss_ack_o ),
708
        .wb_err_o       ( wb_ss_err_o )
709
);
710
 
711
//
712
// Instantiation of the UART16550
713
//
714
`ifdef UART
715
uart_top uart_top (
716
 
717
        // WISHBONE common
718
        .wb_clk_i       ( wb_clk ),
719
        .wb_rst_i       ( wb_rst ),
720
 
721
        // WISHBONE slave
722
        .wb_adr_i       ( wb_us_adr_i[4:0] ),
723
        .wb_dat_i       ( wb_us_dat_i ),
724
        .wb_dat_o       ( wb_us_dat_o ),
725
        .wb_we_i        ( wb_us_we_i  ),
726
        .wb_stb_i       ( wb_us_stb_i ),
727
        .wb_cyc_i       ( wb_us_cyc_i ),
728
        .wb_ack_o       ( wb_us_ack_o ),
729
        .wb_sel_i       ( wb_us_sel_i ),
730
 
731
        // Interrupt request
732
        .int_o          ( pic_ints[`APP_INT_UART] ),
733
 
734
        // UART signals
735
        // serial input/output
736
        .stx_pad_o      ( uart_stx ),
737
        .srx_pad_i      ( uart_srx ),
738
 
739
        // modem signals
740
        .rts_pad_o      ( ),
741
        .cts_pad_i      ( 1'b0 ),
742
        .dtr_pad_o      ( ),
743
        .dsr_pad_i      ( 1'b0 ),
744
        .ri_pad_i       ( 1'b0 ),
745
        .dcd_pad_i      ( 1'b0 )
746
);
747
`else
748
assign wb_us_dat_o = 32'h0000_0000;
749
assign wb_us_ack_o = 1'b0;
750
`endif
751
 
752
 
753
//
754
// Instantiation of the GPIO
755
//
756
`ifdef GPIO
757
gpio_top #( .gw(`GPIO_IOS + 1) )
758
gpio_top_inst (
759
 
760
        // WISHBONE common
761
        .wb_clk_i       ( wb_clk ),
762
        .wb_rst_i       ( wb_rst ),
763
 
764
        // WISHBONE slave
765
        .wb_adr_i       ( wb_gpio_adr_i[4:0] ),
766
        .wb_dat_i       ( wb_gpio_dat_i ),
767
        .wb_dat_o       ( wb_gpio_dat_o ),
768
        .wb_we_i           ( wb_gpio_we_i  ),
769
        .wb_stb_i       ( wb_gpio_stb_i ),
770
        .wb_cyc_i       ( wb_gpio_cyc_i ),
771
        .wb_ack_o       ( wb_gpio_ack_o ),
772
        .wb_sel_i       ( wb_gpio_sel_i ),
773
 
774
        // Interrupt request
775
        .wb_inta_o              ( pic_ints[`APP_INT_GPIO] ),
776
 
777
        // GPIO external signals
778
        .ext_pad_o      ( ext_pad_o ),
779
        .ext_pad_i      ( ext_pad_i ),
780
        .ext_padoe_o( ext_pad_oe_o )
781
 
782
);
783
 
784
minsoc_spartan_3a_starter_kit_ios #( .gpio_num(`GPIO_IOS + 1),
785
         `ifdef GPIO_HAS_INPUT_PINS
786
             .i_line_num(`GPIO_NUM_INPUT),
787
         `endif
788
         `ifdef GPIO_HAS_OUTPUT_PINS
789
        .o_line_num(`GPIO_NUM_OUTPUT),
790
         `endif
791
         `ifdef GPIO_HAS_BIDIR_PINS
792
             .io_line_num(`GPIO_NUM_BIDIR)
793
         `endif
794
) minsoc_spartan_3a_starter_kit_ios_inst_0 (
795
    .ext_pad_o( ext_pad_o ),
796
    .ext_pad_oe( ext_pad_oe_o ),
797
    .ext_pad_i( ext_pad_i ),
798
         `ifdef GPIO_HAS_INPUT_PINS
799
             .i_pins( i_pins ),
800
         `else
801
             .i_pins( ),
802
         `endif
803
         `ifdef GPIO_HAS_OUTPUT_PINS
804
             .o_pins( o_pins ),
805
         `else
806
             .o_pins( ),
807
         `endif
808
         `ifdef GPIO_HAS_BIDIR_PINS
809
             .io_pins( io_pins )
810
         `else
811
             .io_pins( )
812
         `endif
813
);
814
 
815
`else
816
assign wb_gpio_dat_o = 32'h0000_0000;
817
assign wb_gpio_ack_o = 1'b0;
818
`endif
819
 
820
 
821
 
822
//
823
// Instantiation of the Ethernet 10/100 MAC
824
//
825
`ifdef ETHERNET
826
eth_top eth_top (
827
 
828
        // WISHBONE common
829
        .wb_clk_i       ( wb_clk ),
830
        .wb_rst_i       ( wb_rst ),
831
 
832
        // WISHBONE slave
833
        .wb_dat_i       ( wb_es_dat_i ),
834
        .wb_dat_o       ( wb_es_dat_o ),
835
        .wb_adr_i       ( wb_es_adr_i[11:2] ),
836
        .wb_sel_i       ( wb_es_sel_i ),
837
        .wb_we_i        ( wb_es_we_i  ),
838
        .wb_cyc_i       ( wb_es_cyc_i ),
839
        .wb_stb_i       ( wb_es_stb_i ),
840
        .wb_ack_o       ( wb_es_ack_o ),
841
        .wb_err_o       ( wb_es_err_o ),
842
 
843
        // WISHBONE master
844
        .m_wb_adr_o     ( wb_em_adr_o ),
845
        .m_wb_sel_o     ( wb_em_sel_o ),
846
        .m_wb_we_o      ( wb_em_we_o  ),
847
        .m_wb_dat_o     ( wb_em_dat_o ),
848
        .m_wb_dat_i     ( wb_em_dat_i ),
849
        .m_wb_cyc_o     ( wb_em_cyc_o ),
850
        .m_wb_stb_o     ( wb_em_stb_o ),
851
        .m_wb_ack_i     ( wb_em_ack_i ),
852
        .m_wb_err_i     ( wb_em_err_i ),
853
 
854
        // TX
855
        .mtx_clk_pad_i  ( eth_tx_clk ),
856
        .mtxd_pad_o     ( eth_txd ),
857
        .mtxen_pad_o    ( eth_tx_en ),
858
        .mtxerr_pad_o   ( eth_tx_er ),
859
 
860
        // RX
861
        .mrx_clk_pad_i  ( eth_rx_clk ),
862
        .mrxd_pad_i     ( eth_rxd ),
863
        .mrxdv_pad_i    ( eth_rx_dv ),
864
        .mrxerr_pad_i   ( eth_rx_er ),
865
        .mcoll_pad_i    ( eth_col ),
866
        .mcrs_pad_i     ( eth_crs ),
867
 
868
        // MIIM
869
        .mdc_pad_o      ( eth_mdc ),
870
        .md_pad_i       ( eth_mdio ),
871
        .md_pad_o       ( eth_mdo ),
872
        .md_padoe_o     ( eth_mdoe ),
873
 
874
        // Interrupt
875
        .int_o          ( pic_ints[`APP_INT_ETH] )
876
);
877
`else
878
assign wb_es_dat_o = 32'h0000_0000;
879
assign wb_es_ack_o = 1'b0;
880
 
881
assign wb_em_adr_o = 32'h0000_0000;
882
assign wb_em_sel_o = 4'h0;
883
assign wb_em_we_o = 1'b0;
884
assign wb_em_dat_o = 32'h0000_0000;
885
assign wb_em_cyc_o = 1'b0;
886
assign wb_em_stb_o = 1'b0;
887
`endif
888
 
889
//
890
// Instantiation of the Traffic COP
891
//
892
minsoc_tc_top #(`APP_ADDR_DEC_W,
893
         `APP_ADDR_SRAM,
894
         `APP_ADDR_DEC_W,
895
         `APP_ADDR_FLASH,
896
         `APP_ADDR_DECP_W,
897
         `APP_ADDR_PERIP,
898
         `APP_ADDR_DEC_W,
899
         `APP_ADDR_SPI,
900
         `APP_ADDR_ETH,
901
         `APP_ADDR_AUDIO,
902
         `APP_ADDR_UART,
903
         `APP_ADDR_PS2,
904
         `APP_ADDR_GPIO,
905
         `APP_ADDR_RES2
906
        ) tc_top (
907
 
908
        // WISHBONE common
909
        .wb_clk_i       ( wb_clk ),
910
        .wb_rst_i       ( wb_rst ),
911
 
912
        // WISHBONE Initiator 0
913
        .i0_wb_cyc_i    ( 1'b0 ),
914
        .i0_wb_stb_i    ( 1'b0 ),
915
        .i0_wb_adr_i    ( 32'h0000_0000 ),
916
        .i0_wb_sel_i    ( 4'b0000 ),
917
        .i0_wb_we_i     ( 1'b0 ),
918
        .i0_wb_dat_i    ( 32'h0000_0000 ),
919
        .i0_wb_dat_o    ( ),
920
        .i0_wb_ack_o    ( ),
921
        .i0_wb_err_o    ( ),
922
 
923
        // WISHBONE Initiator 1
924
        .i1_wb_cyc_i    ( wb_em_cyc_o ),
925
        .i1_wb_stb_i    ( wb_em_stb_o ),
926
        .i1_wb_adr_i    ( wb_em_adr_o ),
927
        .i1_wb_sel_i    ( wb_em_sel_o ),
928
        .i1_wb_we_i     ( wb_em_we_o  ),
929
        .i1_wb_dat_i    ( wb_em_dat_o ),
930
        .i1_wb_dat_o    ( wb_em_dat_i ),
931
        .i1_wb_ack_o    ( wb_em_ack_i ),
932
        .i1_wb_err_o    ( wb_em_err_i ),
933
 
934
        // WISHBONE Initiator 2
935
        .i2_wb_cyc_i    ( 1'b0 ),
936
        .i2_wb_stb_i    ( 1'b0 ),
937
        .i2_wb_adr_i    ( 32'h0000_0000 ),
938
        .i2_wb_sel_i    ( 4'b0000 ),
939
        .i2_wb_we_i     ( 1'b0 ),
940
        .i2_wb_dat_i    ( 32'h0000_0000 ),
941
        .i2_wb_dat_o    ( ),
942
        .i2_wb_ack_o    ( ),
943
        .i2_wb_err_o    ( ),
944
 
945
        // WISHBONE Initiator 3
946
        .i3_wb_cyc_i    ( wb_dm_cyc_o ),
947
        .i3_wb_stb_i    ( wb_dm_stb_o ),
948
        .i3_wb_adr_i    ( wb_dm_adr_o ),
949
        .i3_wb_sel_i    ( wb_dm_sel_o ),
950
        .i3_wb_we_i     ( wb_dm_we_o  ),
951
        .i3_wb_dat_i    ( wb_dm_dat_o ),
952
        .i3_wb_dat_o    ( wb_dm_dat_i ),
953
        .i3_wb_ack_o    ( wb_dm_ack_i ),
954
        .i3_wb_err_o    ( wb_dm_err_i ),
955
 
956
        // WISHBONE Initiator 4
957
        .i4_wb_cyc_i    ( wb_rdm_cyc_o ),
958
        .i4_wb_stb_i    ( wb_rdm_stb_o ),
959
        .i4_wb_adr_i    ( wb_rdm_adr_o ),
960
        .i4_wb_sel_i    ( wb_rdm_sel_o ),
961
        .i4_wb_we_i     ( wb_rdm_we_o  ),
962
        .i4_wb_dat_i    ( wb_rdm_dat_o ),
963
        .i4_wb_dat_o    ( wb_rdm_dat_i ),
964
        .i4_wb_ack_o    ( wb_rdm_ack_i ),
965
        .i4_wb_err_o    ( wb_rdm_err_i ),
966
 
967
        // WISHBONE Initiator 5
968
        .i5_wb_cyc_i    ( wb_rim_cyc_o ),
969
        .i5_wb_stb_i    ( wb_rim_stb_o ),
970
        .i5_wb_adr_i    ( wb_rim_adr_o ),
971
        .i5_wb_sel_i    ( wb_rim_sel_o ),
972
        .i5_wb_we_i     ( wb_rim_we_o  ),
973
        .i5_wb_dat_i    ( wb_rim_dat_o ),
974
        .i5_wb_dat_o    ( wb_rim_dat_i ),
975
        .i5_wb_ack_o    ( wb_rim_ack_i ),
976
        .i5_wb_err_o    ( wb_rim_err_i ),
977
 
978
        // WISHBONE Initiator 6
979
        .i6_wb_cyc_i    ( 1'b0 ),
980
        .i6_wb_stb_i    ( 1'b0 ),
981
        .i6_wb_adr_i    ( 32'h0000_0000 ),
982
        .i6_wb_sel_i    ( 4'b0000 ),
983
        .i6_wb_we_i     ( 1'b0 ),
984
        .i6_wb_dat_i    ( 32'h0000_0000 ),
985
        .i6_wb_dat_o    ( ),
986
        .i6_wb_ack_o    ( ),
987
        .i6_wb_err_o    ( ),
988
 
989
        // WISHBONE Initiator 7
990
        .i7_wb_cyc_i    ( 1'b0 ),
991
        .i7_wb_stb_i    ( 1'b0 ),
992
        .i7_wb_adr_i    ( 32'h0000_0000 ),
993
        .i7_wb_sel_i    ( 4'b0000 ),
994
        .i7_wb_we_i     ( 1'b0 ),
995
        .i7_wb_dat_i    ( 32'h0000_0000 ),
996
        .i7_wb_dat_o    ( ),
997
        .i7_wb_ack_o    ( ),
998
        .i7_wb_err_o    ( ),
999
 
1000
        // WISHBONE Target 0
1001
        .t0_wb_cyc_o    ( wb_ss_cyc_i ),
1002
        .t0_wb_stb_o    ( wb_ss_stb_i ),
1003
        .t0_wb_adr_o    ( wb_ss_adr_i ),
1004
        .t0_wb_sel_o    ( wb_ss_sel_i ),
1005
        .t0_wb_we_o     ( wb_ss_we_i  ),
1006
        .t0_wb_dat_o    ( wb_ss_dat_i ),
1007
        .t0_wb_dat_i    ( wb_ss_dat_o ),
1008
        .t0_wb_ack_i    ( wb_ss_ack_o ),
1009
        .t0_wb_err_i    ( wb_ss_err_o ),
1010
 
1011
        // WISHBONE Target 1
1012
        .t1_wb_cyc_o    ( wb_fs_cyc_i ),
1013
        .t1_wb_stb_o    ( wb_fs_stb_i ),
1014
        .t1_wb_adr_o    ( wb_fs_adr_i ),
1015
        .t1_wb_sel_o    ( wb_fs_sel_i ),
1016
        .t1_wb_we_o     ( wb_fs_we_i  ),
1017
        .t1_wb_dat_o    ( wb_fs_dat_i ),
1018
        .t1_wb_dat_i    ( wb_fs_dat_o ),
1019
        .t1_wb_ack_i    ( wb_fs_ack_o ),
1020
        .t1_wb_err_i    ( wb_fs_err_o ),
1021
 
1022
        // WISHBONE Target 2
1023
        .t2_wb_cyc_o    ( wb_sp_cyc_i ),
1024
        .t2_wb_stb_o    ( wb_sp_stb_i ),
1025
        .t2_wb_adr_o    ( wb_sp_adr_i ),
1026
        .t2_wb_sel_o    ( wb_sp_sel_i ),
1027
        .t2_wb_we_o     ( wb_sp_we_i  ),
1028
        .t2_wb_dat_o    ( wb_sp_dat_i ),
1029
        .t2_wb_dat_i    ( wb_sp_dat_o ),
1030
        .t2_wb_ack_i    ( wb_sp_ack_o ),
1031
        .t2_wb_err_i    ( wb_sp_err_o ),
1032
 
1033
        // WISHBONE Target 3
1034
        .t3_wb_cyc_o    ( wb_es_cyc_i ),
1035
        .t3_wb_stb_o    ( wb_es_stb_i ),
1036
        .t3_wb_adr_o    ( wb_es_adr_i ),
1037
        .t3_wb_sel_o    ( wb_es_sel_i ),
1038
        .t3_wb_we_o     ( wb_es_we_i  ),
1039
        .t3_wb_dat_o    ( wb_es_dat_i ),
1040
        .t3_wb_dat_i    ( wb_es_dat_o ),
1041
        .t3_wb_ack_i    ( wb_es_ack_o ),
1042
        .t3_wb_err_i    ( wb_es_err_o ),
1043
 
1044
        // WISHBONE Target 4
1045
        .t4_wb_cyc_o    ( ),
1046
        .t4_wb_stb_o    ( ),
1047
        .t4_wb_adr_o    ( ),
1048
        .t4_wb_sel_o    ( ),
1049
        .t4_wb_we_o     ( ),
1050
        .t4_wb_dat_o    ( ),
1051
        .t4_wb_dat_i    ( 32'h0000_0000 ),
1052
        .t4_wb_ack_i    ( 1'b0 ),
1053
        .t4_wb_err_i    ( 1'b1 ),
1054
 
1055
        // WISHBONE Target 5
1056
        .t5_wb_cyc_o    ( wb_us_cyc_i ),
1057
        .t5_wb_stb_o    ( wb_us_stb_i ),
1058
        .t5_wb_adr_o    ( wb_us_adr_i ),
1059
        .t5_wb_sel_o    ( wb_us_sel_i ),
1060
        .t5_wb_we_o     ( wb_us_we_i  ),
1061
        .t5_wb_dat_o    ( wb_us_dat_i ),
1062
        .t5_wb_dat_i    ( wb_us_dat_o ),
1063
        .t5_wb_ack_i    ( wb_us_ack_o ),
1064
        .t5_wb_err_i    ( wb_us_err_o ),
1065
 
1066
        // WISHBONE Target 6
1067
        .t6_wb_cyc_o    ( ),
1068
        .t6_wb_stb_o    ( ),
1069
        .t6_wb_adr_o    ( ),
1070
        .t6_wb_sel_o    ( ),
1071
        .t6_wb_we_o     ( ),
1072
        .t6_wb_dat_o    ( ),
1073
        .t6_wb_dat_i    ( 32'h0000_0000 ),
1074
        .t6_wb_ack_i    ( 1'b0 ),
1075
        .t6_wb_err_i    ( 1'b1 ),
1076
 
1077
        // WISHBONE Target 7
1078
        .t7_wb_cyc_o    ( wb_gpio_cyc_i ),
1079
        .t7_wb_stb_o    ( wb_gpio_stb_i ),
1080
        .t7_wb_adr_o    ( wb_gpio_adr_i ),
1081
        .t7_wb_sel_o    ( wb_gpio_sel_i ),
1082
        .t7_wb_we_o        ( wb_gpio_we_i  ),
1083
        .t7_wb_dat_o    ( wb_gpio_dat_i ),
1084
        .t7_wb_dat_i    ( wb_gpio_dat_o ),
1085
        .t7_wb_ack_i    ( wb_gpio_ack_o ),
1086
        .t7_wb_err_i    ( wb_gpio_err_o ),
1087
 
1088
        // WISHBONE Target 8
1089
        .t8_wb_cyc_o    ( ),
1090
        .t8_wb_stb_o    ( ),
1091
        .t8_wb_adr_o    ( ),
1092
        .t8_wb_sel_o    ( ),
1093
        .t8_wb_we_o     ( ),
1094
        .t8_wb_dat_o    ( ),
1095
        .t8_wb_dat_i    ( 32'h0000_0000 ),
1096
        .t8_wb_ack_i    ( 1'b0 ),
1097
        .t8_wb_err_i    ( 1'b1 )
1098
);
1099
 
1100
//initial begin
1101
//  $dumpvars(0);
1102
//  $dumpfile("dump.vcd");
1103
//end
1104
 
1105
endmodule

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