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1 40 rfajardo
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Xess Traffic Cop                                            ////
4
////                                                              ////
5
////  This file is part of the OR1K test application              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
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////  Description                                                 ////
9
////  This block connectes the RISC and peripheral controller     ////
10
////  cores together.                                             ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - nothing really                                           ////
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////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2002 OpenCores                                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: tc_top.v,v $
48
// Revision 1.4  2004/04/05 08:44:34  lampret
49
// Merged branch_qmem into main tree.
50
//
51
// Revision 1.2  2002/03/29 20:57:30  lampret
52
// Removed unused ports wb_clki and wb_rst_i
53
//
54
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
55
// First import of the "new" XESS XSV environment.
56
//
57
//
58
//
59
 
60
// synopsys translate_off
61
`include "timescale.v"
62
// synopsys translate_on
63
 
64
//
65
// Width of address bus
66
//
67
`define TC_AW           32
68
 
69
//
70
// Width of data bus
71
//
72
`define TC_DW           32
73
 
74
//
75
// Width of byte select bus
76
//
77
`define TC_BSW          4
78
 
79
//
80
// Width of WB target inputs (coming from WB slave)
81
//
82
// data bus width + ack + err
83
//
84
`define TC_TIN_W        `TC_DW+1+1
85
 
86
//
87
// Width of WB initiator inputs (coming from WB masters)
88
//
89
// cyc + stb + address bus width +
90
// byte select bus width + we + data bus width
91
//
92
`define TC_IIN_W        1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
93
 
94
//
95
// Traffic Cop Top
96
//
97
module minsoc_tc_top (
98
        wb_clk_i,
99
        wb_rst_i,
100
 
101
        i0_wb_cyc_i,
102
        i0_wb_stb_i,
103
        i0_wb_adr_i,
104
        i0_wb_sel_i,
105
        i0_wb_we_i,
106
        i0_wb_dat_i,
107
        i0_wb_dat_o,
108
        i0_wb_ack_o,
109
        i0_wb_err_o,
110
        i0_wb_cti_i,
111
        i0_wb_bte_i,
112
 
113
        i1_wb_cyc_i,
114
        i1_wb_stb_i,
115
        i1_wb_adr_i,
116
        i1_wb_sel_i,
117
        i1_wb_we_i,
118
        i1_wb_dat_i,
119
        i1_wb_dat_o,
120
        i1_wb_ack_o,
121
        i1_wb_err_o,
122
        i1_wb_cti_i,
123
        i1_wb_bte_i,
124
 
125
        i2_wb_cyc_i,
126
        i2_wb_stb_i,
127
        i2_wb_adr_i,
128
        i2_wb_sel_i,
129
        i2_wb_we_i,
130
        i2_wb_dat_i,
131
        i2_wb_dat_o,
132
        i2_wb_ack_o,
133
        i2_wb_err_o,
134
        i2_wb_cti_i,
135
        i2_wb_bte_i,
136
 
137
        i3_wb_cyc_i,
138
        i3_wb_stb_i,
139
        i3_wb_adr_i,
140
        i3_wb_sel_i,
141
        i3_wb_we_i,
142
        i3_wb_dat_i,
143
        i3_wb_dat_o,
144
        i3_wb_ack_o,
145
        i3_wb_err_o,
146
        i3_wb_cti_i,
147
        i3_wb_bte_i,
148
 
149
        i4_wb_cyc_i,
150
        i4_wb_stb_i,
151
        i4_wb_adr_i,
152
        i4_wb_sel_i,
153
        i4_wb_we_i,
154
        i4_wb_dat_i,
155
        i4_wb_dat_o,
156
        i4_wb_ack_o,
157
        i4_wb_err_o,
158
        i4_wb_cti_i,
159
        i4_wb_bte_i,
160
 
161
        i5_wb_cyc_i,
162
        i5_wb_stb_i,
163
        i5_wb_adr_i,
164
        i5_wb_sel_i,
165
        i5_wb_we_i,
166
        i5_wb_dat_i,
167
        i5_wb_dat_o,
168
        i5_wb_ack_o,
169
        i5_wb_err_o,
170
        i5_wb_cti_i,
171
        i5_wb_bte_i,
172
 
173
        i6_wb_cyc_i,
174
        i6_wb_stb_i,
175
        i6_wb_adr_i,
176
        i6_wb_sel_i,
177
        i6_wb_we_i,
178
        i6_wb_dat_i,
179
        i6_wb_dat_o,
180
        i6_wb_ack_o,
181
        i6_wb_err_o,
182
        i6_wb_cti_i,
183
        i6_wb_bte_i,
184
 
185
        i7_wb_cyc_i,
186
        i7_wb_stb_i,
187
        i7_wb_adr_i,
188
        i7_wb_sel_i,
189
        i7_wb_we_i,
190
        i7_wb_dat_i,
191
        i7_wb_dat_o,
192
        i7_wb_ack_o,
193
        i7_wb_err_o,
194
        i7_wb_cti_i,
195
        i7_wb_bte_i,
196
 
197
        t0_wb_cyc_o,
198
        t0_wb_stb_o,
199
        t0_wb_adr_o,
200
        t0_wb_sel_o,
201
        t0_wb_we_o,
202
        t0_wb_dat_o,
203
        t0_wb_dat_i,
204
        t0_wb_ack_i,
205
        t0_wb_err_i,
206
        t0_wb_cti_o,
207
        t0_wb_bte_o,
208
 
209
        t1_wb_cyc_o,
210
        t1_wb_stb_o,
211
        t1_wb_adr_o,
212
        t1_wb_sel_o,
213
        t1_wb_we_o,
214
        t1_wb_dat_o,
215
        t1_wb_dat_i,
216
        t1_wb_ack_i,
217
        t1_wb_err_i,
218
        t1_wb_cti_o,
219
        t1_wb_bte_o,
220
 
221
        t2_wb_cyc_o,
222
        t2_wb_stb_o,
223
        t2_wb_adr_o,
224
        t2_wb_sel_o,
225
        t2_wb_we_o,
226
        t2_wb_dat_o,
227
        t2_wb_dat_i,
228
        t2_wb_ack_i,
229
        t2_wb_err_i,
230
        t2_wb_cti_o,
231
        t2_wb_bte_o,
232
 
233
        t3_wb_cyc_o,
234
        t3_wb_stb_o,
235
        t3_wb_adr_o,
236
        t3_wb_sel_o,
237
        t3_wb_we_o,
238
        t3_wb_dat_o,
239
        t3_wb_dat_i,
240
        t3_wb_ack_i,
241
        t3_wb_err_i,
242
        t3_wb_cti_o,
243
        t3_wb_bte_o,
244
 
245
        t4_wb_cyc_o,
246
        t4_wb_stb_o,
247
        t4_wb_adr_o,
248
        t4_wb_sel_o,
249
        t4_wb_we_o,
250
        t4_wb_dat_o,
251
        t4_wb_dat_i,
252
        t4_wb_ack_i,
253
        t4_wb_err_i,
254
        t4_wb_cti_o,
255
        t4_wb_bte_o,
256
 
257
        t5_wb_cyc_o,
258
        t5_wb_stb_o,
259
        t5_wb_adr_o,
260
        t5_wb_sel_o,
261
        t5_wb_we_o,
262
        t5_wb_dat_o,
263
        t5_wb_dat_i,
264
        t5_wb_ack_i,
265
        t5_wb_err_i,
266
        t5_wb_cti_o,
267
        t5_wb_bte_o,
268
 
269
        t6_wb_cyc_o,
270
        t6_wb_stb_o,
271
        t6_wb_adr_o,
272
        t6_wb_sel_o,
273
        t6_wb_we_o,
274
        t6_wb_dat_o,
275
        t6_wb_dat_i,
276
        t6_wb_ack_i,
277
        t6_wb_err_i,
278
        t6_wb_cti_o,
279
        t6_wb_bte_o,
280
 
281
        t7_wb_cyc_o,
282
        t7_wb_stb_o,
283
        t7_wb_adr_o,
284
        t7_wb_sel_o,
285
        t7_wb_we_o,
286
        t7_wb_dat_o,
287
        t7_wb_dat_i,
288
        t7_wb_ack_i,
289
        t7_wb_err_i,
290
        t7_wb_cti_o,
291
        t7_wb_bte_o,
292
 
293
        t8_wb_cyc_o,
294
        t8_wb_stb_o,
295
        t8_wb_adr_o,
296
        t8_wb_sel_o,
297
        t8_wb_we_o,
298
        t8_wb_dat_o,
299
        t8_wb_dat_i,
300
        t8_wb_ack_i,
301
        t8_wb_err_i,
302
        t8_wb_cti_o,
303
        t8_wb_bte_o
304
 
305
 
306
);
307
 
308
//
309
// Parameters
310
//
311
parameter               t0_addr_w = 4;
312
parameter               t0_addr = 4'd8;
313
parameter               t1_addr_w = 4;
314
parameter               t1_addr = 4'd0;
315
parameter               t28c_addr_w = 4;
316
parameter               t28_addr = 4'd0;
317
parameter               t28i_addr_w = 4;
318
parameter               t2_addr = 4'd1;
319
parameter               t3_addr = 4'd2;
320
parameter               t4_addr = 4'd3;
321
parameter               t5_addr = 4'd4;
322
parameter               t6_addr = 4'd5;
323
parameter               t7_addr = 4'd6;
324
parameter               t8_addr = 4'd7;
325
 
326
//
327
// I/O Ports
328
//
329
input                   wb_clk_i;
330
input                   wb_rst_i;
331
//
332
// WB slave i/f connecting initiator 0
333
//
334
input                   i0_wb_cyc_i;
335
input                   i0_wb_stb_i;
336
input   [`TC_AW-1:0]     i0_wb_adr_i;
337
input   [`TC_BSW-1:0]    i0_wb_sel_i;
338
input                   i0_wb_we_i;
339
input   [`TC_DW-1:0]     i0_wb_dat_i;
340
output  [`TC_DW-1:0]     i0_wb_dat_o;
341
output                  i0_wb_ack_o;
342
output                  i0_wb_err_o;
343
input   [2:0]            i0_wb_cti_i;
344
input   [1:0]            i0_wb_bte_i;
345
 
346
//
347
// WB slave i/f connecting initiator 1
348
//
349
input                   i1_wb_cyc_i;
350
input                   i1_wb_stb_i;
351
input   [`TC_AW-1:0]     i1_wb_adr_i;
352
input   [`TC_BSW-1:0]    i1_wb_sel_i;
353
input                   i1_wb_we_i;
354
input   [`TC_DW-1:0]     i1_wb_dat_i;
355
output  [`TC_DW-1:0]     i1_wb_dat_o;
356
output                  i1_wb_ack_o;
357
output                  i1_wb_err_o;
358
input   [2:0]            i1_wb_cti_i;
359
input   [1:0]            i1_wb_bte_i;
360
 
361
//
362
// WB slave i/f connecting initiator 2
363
//
364
input                   i2_wb_cyc_i;
365
input                   i2_wb_stb_i;
366
input   [`TC_AW-1:0]     i2_wb_adr_i;
367
input   [`TC_BSW-1:0]    i2_wb_sel_i;
368
input                   i2_wb_we_i;
369
input   [`TC_DW-1:0]     i2_wb_dat_i;
370
output  [`TC_DW-1:0]     i2_wb_dat_o;
371
output                  i2_wb_ack_o;
372
output                  i2_wb_err_o;
373
input   [2:0]            i2_wb_cti_i;
374
input   [1:0]            i2_wb_bte_i;
375
 
376
//
377
// WB slave i/f connecting initiator 3
378
//
379
input                   i3_wb_cyc_i;
380
input                   i3_wb_stb_i;
381
input   [`TC_AW-1:0]     i3_wb_adr_i;
382
input   [`TC_BSW-1:0]    i3_wb_sel_i;
383
input                   i3_wb_we_i;
384
input   [`TC_DW-1:0]     i3_wb_dat_i;
385
output  [`TC_DW-1:0]     i3_wb_dat_o;
386
output                  i3_wb_ack_o;
387
output                  i3_wb_err_o;
388
input   [2:0]            i3_wb_cti_i;
389
input   [1:0]            i3_wb_bte_i;
390
 
391
//
392
// WB slave i/f connecting initiator 4
393
//
394
input                   i4_wb_cyc_i;
395
input                   i4_wb_stb_i;
396
input   [`TC_AW-1:0]     i4_wb_adr_i;
397
input   [`TC_BSW-1:0]    i4_wb_sel_i;
398
input                   i4_wb_we_i;
399
input   [`TC_DW-1:0]     i4_wb_dat_i;
400
output  [`TC_DW-1:0]     i4_wb_dat_o;
401
output                  i4_wb_ack_o;
402
output                  i4_wb_err_o;
403
input   [2:0]            i4_wb_cti_i;
404
input   [1:0]            i4_wb_bte_i;
405
 
406
//
407
// WB slave i/f connecting initiator 5
408
//
409
input                   i5_wb_cyc_i;
410
input                   i5_wb_stb_i;
411
input   [`TC_AW-1:0]     i5_wb_adr_i;
412
input   [`TC_BSW-1:0]    i5_wb_sel_i;
413
input                   i5_wb_we_i;
414
input   [`TC_DW-1:0]     i5_wb_dat_i;
415
output  [`TC_DW-1:0]     i5_wb_dat_o;
416
output                  i5_wb_ack_o;
417
output                  i5_wb_err_o;
418
input   [2:0]            i5_wb_cti_i;
419
input   [1:0]            i5_wb_bte_i;
420
 
421
//
422
// WB slave i/f connecting initiator 6
423
//
424
input                   i6_wb_cyc_i;
425
input                   i6_wb_stb_i;
426
input   [`TC_AW-1:0]     i6_wb_adr_i;
427
input   [`TC_BSW-1:0]    i6_wb_sel_i;
428
input                   i6_wb_we_i;
429
input   [`TC_DW-1:0]     i6_wb_dat_i;
430
output  [`TC_DW-1:0]     i6_wb_dat_o;
431
output                  i6_wb_ack_o;
432
output                  i6_wb_err_o;
433
input   [2:0]            i6_wb_cti_i;
434
input   [1:0]            i6_wb_bte_i;
435
 
436
//
437
// WB slave i/f connecting initiator 7
438
//
439
input                   i7_wb_cyc_i;
440
input                   i7_wb_stb_i;
441
input   [`TC_AW-1:0]     i7_wb_adr_i;
442
input   [`TC_BSW-1:0]    i7_wb_sel_i;
443
input                   i7_wb_we_i;
444
input   [`TC_DW-1:0]     i7_wb_dat_i;
445
output  [`TC_DW-1:0]     i7_wb_dat_o;
446
output                  i7_wb_ack_o;
447
output                  i7_wb_err_o;
448
input   [2:0]            i7_wb_cti_i;
449
input   [1:0]            i7_wb_bte_i;
450
 
451
//
452
// WB master i/f connecting target 0
453
//
454
output                  t0_wb_cyc_o;
455
output                  t0_wb_stb_o;
456
output  [`TC_AW-1:0]     t0_wb_adr_o;
457
output  [`TC_BSW-1:0]    t0_wb_sel_o;
458
output                  t0_wb_we_o;
459
output  [`TC_DW-1:0]     t0_wb_dat_o;
460
input   [`TC_DW-1:0]     t0_wb_dat_i;
461
input                   t0_wb_ack_i;
462
input                   t0_wb_err_i;
463
output  [2:0]            t0_wb_cti_o;
464
output  [1:0]            t0_wb_bte_o;
465
 
466
//
467
// WB master i/f connecting target 1
468
//
469
output                  t1_wb_cyc_o;
470
output                  t1_wb_stb_o;
471
output  [`TC_AW-1:0]     t1_wb_adr_o;
472
output  [`TC_BSW-1:0]    t1_wb_sel_o;
473
output                  t1_wb_we_o;
474
output  [`TC_DW-1:0]     t1_wb_dat_o;
475
input   [`TC_DW-1:0]     t1_wb_dat_i;
476
input                   t1_wb_ack_i;
477
input                   t1_wb_err_i;
478
output  [2:0]            t1_wb_cti_o;
479
output  [1:0]            t1_wb_bte_o;
480
 
481
//
482
// WB master i/f connecting target 2
483
//
484
output                  t2_wb_cyc_o;
485
output                  t2_wb_stb_o;
486
output  [`TC_AW-1:0]     t2_wb_adr_o;
487
output  [`TC_BSW-1:0]    t2_wb_sel_o;
488
output                  t2_wb_we_o;
489
output  [`TC_DW-1:0]     t2_wb_dat_o;
490
input   [`TC_DW-1:0]     t2_wb_dat_i;
491
input                   t2_wb_ack_i;
492
input                   t2_wb_err_i;
493
output  [2:0]            t2_wb_cti_o;
494
output  [1:0]            t2_wb_bte_o;
495
 
496
//
497
// WB master i/f connecting target 3
498
//
499
output                  t3_wb_cyc_o;
500
output                  t3_wb_stb_o;
501
output  [`TC_AW-1:0]     t3_wb_adr_o;
502
output  [`TC_BSW-1:0]    t3_wb_sel_o;
503
output                  t3_wb_we_o;
504
output  [`TC_DW-1:0]     t3_wb_dat_o;
505
input   [`TC_DW-1:0]     t3_wb_dat_i;
506
input                   t3_wb_ack_i;
507
input                   t3_wb_err_i;
508
output  [2:0]            t3_wb_cti_o;
509
output  [1:0]            t3_wb_bte_o;
510
 
511
//
512
// WB master i/f connecting target 4
513
//
514
output                  t4_wb_cyc_o;
515
output                  t4_wb_stb_o;
516
output  [`TC_AW-1:0]     t4_wb_adr_o;
517
output  [`TC_BSW-1:0]    t4_wb_sel_o;
518
output                  t4_wb_we_o;
519
output  [`TC_DW-1:0]     t4_wb_dat_o;
520
input   [`TC_DW-1:0]     t4_wb_dat_i;
521
input                   t4_wb_ack_i;
522
input                   t4_wb_err_i;
523
output  [2:0]            t4_wb_cti_o;
524
output  [1:0]            t4_wb_bte_o;
525
 
526
//
527
// WB master i/f connecting target 5
528
//
529
output                  t5_wb_cyc_o;
530
output                  t5_wb_stb_o;
531
output  [`TC_AW-1:0]     t5_wb_adr_o;
532
output  [`TC_BSW-1:0]    t5_wb_sel_o;
533
output                  t5_wb_we_o;
534
output  [`TC_DW-1:0]     t5_wb_dat_o;
535
input   [`TC_DW-1:0]     t5_wb_dat_i;
536
input                   t5_wb_ack_i;
537
input                   t5_wb_err_i;
538
output  [2:0]            t5_wb_cti_o;
539
output  [1:0]            t5_wb_bte_o;
540
 
541
//
542
// WB master i/f connecting target 6
543
//
544
output                  t6_wb_cyc_o;
545
output                  t6_wb_stb_o;
546
output  [`TC_AW-1:0]     t6_wb_adr_o;
547
output  [`TC_BSW-1:0]    t6_wb_sel_o;
548
output                  t6_wb_we_o;
549
output  [`TC_DW-1:0]     t6_wb_dat_o;
550
input   [`TC_DW-1:0]     t6_wb_dat_i;
551
input                   t6_wb_ack_i;
552
input                   t6_wb_err_i;
553
output  [2:0]            t6_wb_cti_o;
554
output  [1:0]            t6_wb_bte_o;
555
 
556
//
557
// WB master i/f connecting target 7
558
//
559
output                  t7_wb_cyc_o;
560
output                  t7_wb_stb_o;
561
output  [`TC_AW-1:0]     t7_wb_adr_o;
562
output  [`TC_BSW-1:0]    t7_wb_sel_o;
563
output                  t7_wb_we_o;
564
output  [`TC_DW-1:0]     t7_wb_dat_o;
565
input   [`TC_DW-1:0]     t7_wb_dat_i;
566
input                   t7_wb_ack_i;
567
input                   t7_wb_err_i;
568
output  [2:0]            t7_wb_cti_o;
569
output  [1:0]            t7_wb_bte_o;
570
 
571
//
572
// WB master i/f connecting target 8
573
//
574
output                  t8_wb_cyc_o;
575
output                  t8_wb_stb_o;
576
output  [`TC_AW-1:0]     t8_wb_adr_o;
577
output  [`TC_BSW-1:0]    t8_wb_sel_o;
578
output                  t8_wb_we_o;
579
output  [`TC_DW-1:0]     t8_wb_dat_o;
580
input   [`TC_DW-1:0]     t8_wb_dat_i;
581
input                   t8_wb_ack_i;
582
input                   t8_wb_err_i;
583
output  [2:0]            t8_wb_cti_o;
584
output  [1:0]            t8_wb_bte_o;
585
 
586
 
587
//
588
// Internal wires & registers
589
//
590
 
591
//
592
// Outputs for initiators from both mi_to_st blocks
593
//
594
wire    [`TC_DW-1:0]     xi0_wb_dat_o;
595
wire                    xi0_wb_ack_o;
596
wire                    xi0_wb_err_o;
597
wire    [`TC_DW-1:0]     xi1_wb_dat_o;
598
wire                    xi1_wb_ack_o;
599
wire                    xi1_wb_err_o;
600
wire    [`TC_DW-1:0]     xi2_wb_dat_o;
601
wire                    xi2_wb_ack_o;
602
wire                    xi2_wb_err_o;
603
wire    [`TC_DW-1:0]     xi3_wb_dat_o;
604
wire                    xi3_wb_ack_o;
605
wire                    xi3_wb_err_o;
606
wire    [`TC_DW-1:0]     xi4_wb_dat_o;
607
wire                    xi4_wb_ack_o;
608
wire                    xi4_wb_err_o;
609
wire    [`TC_DW-1:0]     xi5_wb_dat_o;
610
wire                    xi5_wb_ack_o;
611
wire                    xi5_wb_err_o;
612
wire    [`TC_DW-1:0]     xi6_wb_dat_o;
613
wire                    xi6_wb_ack_o;
614
wire                    xi6_wb_err_o;
615
wire    [`TC_DW-1:0]     xi7_wb_dat_o;
616
wire                    xi7_wb_ack_o;
617
wire                    xi7_wb_err_o;
618
wire    [`TC_DW-1:0]     yi0_wb_dat_o;
619
wire                    yi0_wb_ack_o;
620
wire                    yi0_wb_err_o;
621
wire    [`TC_DW-1:0]     yi1_wb_dat_o;
622
wire                    yi1_wb_ack_o;
623
wire                    yi1_wb_err_o;
624
wire    [`TC_DW-1:0]     yi2_wb_dat_o;
625
wire                    yi2_wb_ack_o;
626
wire                    yi2_wb_err_o;
627
wire    [`TC_DW-1:0]     yi3_wb_dat_o;
628
wire                    yi3_wb_ack_o;
629
wire                    yi3_wb_err_o;
630
wire    [`TC_DW-1:0]     yi4_wb_dat_o;
631
wire                    yi4_wb_ack_o;
632
wire                    yi4_wb_err_o;
633
wire    [`TC_DW-1:0]     yi5_wb_dat_o;
634
wire                    yi5_wb_ack_o;
635
wire                    yi5_wb_err_o;
636
wire    [`TC_DW-1:0]     yi6_wb_dat_o;
637
wire                    yi6_wb_ack_o;
638
wire                    yi6_wb_err_o;
639
wire    [`TC_DW-1:0]     yi7_wb_dat_o;
640
wire                    yi7_wb_ack_o;
641
wire                    yi7_wb_err_o;
642
 
643
//
644
// Intermediate signals connecting peripheral channel's
645
// mi_to_st and si_to_mt blocks.
646
//
647
wire                    z_wb_cyc_i;
648
wire                    z_wb_stb_i;
649
wire    [`TC_AW-1:0]     z_wb_adr_i;
650
wire    [`TC_BSW-1:0]    z_wb_sel_i;
651
wire                    z_wb_we_i;
652
wire    [`TC_DW-1:0]     z_wb_dat_i;
653
wire    [`TC_DW-1:0]     z_wb_dat_t;
654
wire                    z_wb_ack_t;
655
wire                    z_wb_err_t;
656
wire    [2:0]            z_wb_cti_i;
657
wire    [1:0]            z_wb_bte_i;
658
 
659
//
660
// Outputs for initiators are ORed from both mi_to_st blocks
661
//
662
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
663
assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
664
assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o;
665
assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o;
666
assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o;
667
assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o;
668
assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o;
669
assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o;
670
assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o;
671
assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o;
672
assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o;
673
assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o;
674
assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o;
675
assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o;
676
assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o;
677
assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o;
678
assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o;
679
assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o;
680
assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o;
681
assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o;
682
assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o;
683
assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o;
684
assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o;
685
assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o;
686
 
687
//
688
// From initiators to target 0
689
//
690
tc_mi_to_st #(t0_addr_w, t0_addr,
691
        0, t0_addr_w, t0_addr) t0_ch(
692
        .wb_clk_i(wb_clk_i),
693
        .wb_rst_i(wb_rst_i),
694
        .i0_wb_cyc_i(i0_wb_cyc_i),
695
        .i0_wb_stb_i(i0_wb_stb_i),
696
        .i0_wb_adr_i(i0_wb_adr_i),
697
        .i0_wb_sel_i(i0_wb_sel_i),
698
        .i0_wb_we_i(i0_wb_we_i),
699
        .i0_wb_dat_i(i0_wb_dat_i),
700
        .i0_wb_dat_o(xi0_wb_dat_o),
701
        .i0_wb_ack_o(xi0_wb_ack_o),
702
        .i0_wb_err_o(xi0_wb_err_o),
703
        .i0_wb_cti_i(i0_wb_cti_i),
704
        .i0_wb_bte_i(i0_wb_bte_i),
705
 
706
        .i1_wb_cyc_i(i1_wb_cyc_i),
707
        .i1_wb_stb_i(i1_wb_stb_i),
708
        .i1_wb_adr_i(i1_wb_adr_i),
709
        .i1_wb_sel_i(i1_wb_sel_i),
710
        .i1_wb_we_i(i1_wb_we_i),
711
        .i1_wb_dat_i(i1_wb_dat_i),
712
        .i1_wb_dat_o(xi1_wb_dat_o),
713
        .i1_wb_ack_o(xi1_wb_ack_o),
714
        .i1_wb_err_o(xi1_wb_err_o),
715
        .i1_wb_cti_i(i1_wb_cti_i),
716
        .i1_wb_bte_i(i1_wb_bte_i),
717
 
718
        .i2_wb_cyc_i(i2_wb_cyc_i),
719
        .i2_wb_stb_i(i2_wb_stb_i),
720
        .i2_wb_adr_i(i2_wb_adr_i),
721
        .i2_wb_sel_i(i2_wb_sel_i),
722
        .i2_wb_we_i(i2_wb_we_i),
723
        .i2_wb_dat_i(i2_wb_dat_i),
724
        .i2_wb_dat_o(xi2_wb_dat_o),
725
        .i2_wb_ack_o(xi2_wb_ack_o),
726
        .i2_wb_err_o(xi2_wb_err_o),
727
        .i2_wb_cti_i(i2_wb_cti_i),
728
        .i2_wb_bte_i(i2_wb_bte_i),
729
 
730
        .i3_wb_cyc_i(i3_wb_cyc_i),
731
        .i3_wb_stb_i(i3_wb_stb_i),
732
        .i3_wb_adr_i(i3_wb_adr_i),
733
        .i3_wb_sel_i(i3_wb_sel_i),
734
        .i3_wb_we_i(i3_wb_we_i),
735
        .i3_wb_dat_i(i3_wb_dat_i),
736
        .i3_wb_dat_o(xi3_wb_dat_o),
737
        .i3_wb_ack_o(xi3_wb_ack_o),
738
        .i3_wb_err_o(xi3_wb_err_o),
739
        .i3_wb_cti_i(i3_wb_cti_i),
740
        .i3_wb_bte_i(i3_wb_bte_i),
741
 
742
        .i4_wb_cyc_i(i4_wb_cyc_i),
743
        .i4_wb_stb_i(i4_wb_stb_i),
744
        .i4_wb_adr_i(i4_wb_adr_i),
745
        .i4_wb_sel_i(i4_wb_sel_i),
746
        .i4_wb_we_i(i4_wb_we_i),
747
        .i4_wb_dat_i(i4_wb_dat_i),
748
        .i4_wb_dat_o(xi4_wb_dat_o),
749
        .i4_wb_ack_o(xi4_wb_ack_o),
750
        .i4_wb_err_o(xi4_wb_err_o),
751
        .i4_wb_cti_i(i4_wb_cti_i),
752
        .i4_wb_bte_i(i4_wb_bte_i),
753
 
754
        .i5_wb_cyc_i(i5_wb_cyc_i),
755
        .i5_wb_stb_i(i5_wb_stb_i),
756
        .i5_wb_adr_i(i5_wb_adr_i),
757
        .i5_wb_sel_i(i5_wb_sel_i),
758
        .i5_wb_we_i(i5_wb_we_i),
759
        .i5_wb_dat_i(i5_wb_dat_i),
760
        .i5_wb_dat_o(xi5_wb_dat_o),
761
        .i5_wb_ack_o(xi5_wb_ack_o),
762
        .i5_wb_err_o(xi5_wb_err_o),
763
        .i5_wb_cti_i(i5_wb_cti_i),
764
        .i5_wb_bte_i(i5_wb_bte_i),
765
 
766
        .i6_wb_cyc_i(i6_wb_cyc_i),
767
        .i6_wb_stb_i(i6_wb_stb_i),
768
        .i6_wb_adr_i(i6_wb_adr_i),
769
        .i6_wb_sel_i(i6_wb_sel_i),
770
        .i6_wb_we_i(i6_wb_we_i),
771
        .i6_wb_dat_i(i6_wb_dat_i),
772
        .i6_wb_dat_o(xi6_wb_dat_o),
773
        .i6_wb_ack_o(xi6_wb_ack_o),
774
        .i6_wb_err_o(xi6_wb_err_o),
775
        .i6_wb_cti_i(i6_wb_cti_i),
776
        .i6_wb_bte_i(i6_wb_bte_i),
777
 
778
        .i7_wb_cyc_i(i7_wb_cyc_i),
779
        .i7_wb_stb_i(i7_wb_stb_i),
780
        .i7_wb_adr_i(i7_wb_adr_i),
781
        .i7_wb_sel_i(i7_wb_sel_i),
782
        .i7_wb_we_i(i7_wb_we_i),
783
        .i7_wb_dat_i(i7_wb_dat_i),
784
        .i7_wb_dat_o(xi7_wb_dat_o),
785
        .i7_wb_ack_o(xi7_wb_ack_o),
786
        .i7_wb_err_o(xi7_wb_err_o),
787
        .i7_wb_cti_i(i7_wb_cti_i),
788
        .i7_wb_bte_i(i7_wb_bte_i),
789
 
790
 
791
        .t0_wb_cyc_o(t0_wb_cyc_o),
792
        .t0_wb_stb_o(t0_wb_stb_o),
793
        .t0_wb_adr_o(t0_wb_adr_o),
794
        .t0_wb_sel_o(t0_wb_sel_o),
795
        .t0_wb_we_o(t0_wb_we_o),
796
        .t0_wb_dat_o(t0_wb_dat_o),
797
        .t0_wb_dat_i(t0_wb_dat_i),
798
        .t0_wb_ack_i(t0_wb_ack_i),
799
        .t0_wb_err_i(t0_wb_err_i),
800
        .t0_wb_cti_o(t0_wb_cti_o),
801
        .t0_wb_bte_o(t0_wb_bte_o)
802
 
803
);
804
 
805
//
806
// From initiators to targets 1-8 (upper part)
807
//
808
tc_mi_to_st #(t1_addr_w, t1_addr,
809
        1, t28c_addr_w, t28_addr) t18_ch_upper(
810
        .wb_clk_i(wb_clk_i),
811
        .wb_rst_i(wb_rst_i),
812
        .i0_wb_cyc_i(i0_wb_cyc_i),
813
        .i0_wb_stb_i(i0_wb_stb_i),
814
        .i0_wb_adr_i(i0_wb_adr_i),
815
        .i0_wb_sel_i(i0_wb_sel_i),
816
        .i0_wb_we_i(i0_wb_we_i),
817
        .i0_wb_dat_i(i0_wb_dat_i),
818
        .i0_wb_dat_o(yi0_wb_dat_o),
819
        .i0_wb_ack_o(yi0_wb_ack_o),
820
        .i0_wb_err_o(yi0_wb_err_o),
821
        .i0_wb_cti_i(i0_wb_cti_i),
822
        .i0_wb_bte_i(i0_wb_bte_i),
823
 
824
        .i1_wb_cyc_i(i1_wb_cyc_i),
825
        .i1_wb_stb_i(i1_wb_stb_i),
826
        .i1_wb_adr_i(i1_wb_adr_i),
827
        .i1_wb_sel_i(i1_wb_sel_i),
828
        .i1_wb_we_i(i1_wb_we_i),
829
        .i1_wb_dat_i(i1_wb_dat_i),
830
        .i1_wb_dat_o(yi1_wb_dat_o),
831
        .i1_wb_ack_o(yi1_wb_ack_o),
832
        .i1_wb_err_o(yi1_wb_err_o),
833
        .i1_wb_cti_i(i1_wb_cti_i),
834
        .i1_wb_bte_i(i1_wb_bte_i),
835
 
836
        .i2_wb_cyc_i(i2_wb_cyc_i),
837
        .i2_wb_stb_i(i2_wb_stb_i),
838
        .i2_wb_adr_i(i2_wb_adr_i),
839
        .i2_wb_sel_i(i2_wb_sel_i),
840
        .i2_wb_we_i(i2_wb_we_i),
841
        .i2_wb_dat_i(i2_wb_dat_i),
842
        .i2_wb_dat_o(yi2_wb_dat_o),
843
        .i2_wb_ack_o(yi2_wb_ack_o),
844
        .i2_wb_err_o(yi2_wb_err_o),
845
        .i2_wb_cti_i(i2_wb_cti_i),
846
        .i2_wb_bte_i(i2_wb_bte_i),
847
 
848
        .i3_wb_cyc_i(i3_wb_cyc_i),
849
        .i3_wb_stb_i(i3_wb_stb_i),
850
        .i3_wb_adr_i(i3_wb_adr_i),
851
        .i3_wb_sel_i(i3_wb_sel_i),
852
        .i3_wb_we_i(i3_wb_we_i),
853
        .i3_wb_dat_i(i3_wb_dat_i),
854
        .i3_wb_dat_o(yi3_wb_dat_o),
855
        .i3_wb_ack_o(yi3_wb_ack_o),
856
        .i3_wb_err_o(yi3_wb_err_o),
857
        .i3_wb_cti_i(i3_wb_cti_i),
858
        .i3_wb_bte_i(i3_wb_bte_i),
859
 
860
        .i4_wb_cyc_i(i4_wb_cyc_i),
861
        .i4_wb_stb_i(i4_wb_stb_i),
862
        .i4_wb_adr_i(i4_wb_adr_i),
863
        .i4_wb_sel_i(i4_wb_sel_i),
864
        .i4_wb_we_i(i4_wb_we_i),
865
        .i4_wb_dat_i(i4_wb_dat_i),
866
        .i4_wb_dat_o(yi4_wb_dat_o),
867
        .i4_wb_ack_o(yi4_wb_ack_o),
868
        .i4_wb_err_o(yi4_wb_err_o),
869
        .i4_wb_cti_i(i4_wb_cti_i),
870
        .i4_wb_bte_i(i4_wb_bte_i),
871
 
872
        .i5_wb_cyc_i(i5_wb_cyc_i),
873
        .i5_wb_stb_i(i5_wb_stb_i),
874
        .i5_wb_adr_i(i5_wb_adr_i),
875
        .i5_wb_sel_i(i5_wb_sel_i),
876
        .i5_wb_we_i(i5_wb_we_i),
877
        .i5_wb_dat_i(i5_wb_dat_i),
878
        .i5_wb_dat_o(yi5_wb_dat_o),
879
        .i5_wb_ack_o(yi5_wb_ack_o),
880
        .i5_wb_err_o(yi5_wb_err_o),
881
        .i5_wb_cti_i(i5_wb_cti_i),
882
        .i5_wb_bte_i(i5_wb_bte_i),
883
 
884
        .i6_wb_cyc_i(i6_wb_cyc_i),
885
        .i6_wb_stb_i(i6_wb_stb_i),
886
        .i6_wb_adr_i(i6_wb_adr_i),
887
        .i6_wb_sel_i(i6_wb_sel_i),
888
        .i6_wb_we_i(i6_wb_we_i),
889
        .i6_wb_dat_i(i6_wb_dat_i),
890
        .i6_wb_dat_o(yi6_wb_dat_o),
891
        .i6_wb_ack_o(yi6_wb_ack_o),
892
        .i6_wb_err_o(yi6_wb_err_o),
893
        .i6_wb_cti_i(i6_wb_cti_i),
894
        .i6_wb_bte_i(i6_wb_bte_i),
895
 
896
        .i7_wb_cyc_i(i7_wb_cyc_i),
897
        .i7_wb_stb_i(i7_wb_stb_i),
898
        .i7_wb_adr_i(i7_wb_adr_i),
899
        .i7_wb_sel_i(i7_wb_sel_i),
900
        .i7_wb_we_i(i7_wb_we_i),
901
        .i7_wb_dat_i(i7_wb_dat_i),
902
        .i7_wb_dat_o(yi7_wb_dat_o),
903
        .i7_wb_ack_o(yi7_wb_ack_o),
904
        .i7_wb_err_o(yi7_wb_err_o),
905
        .i7_wb_cti_i(i7_wb_cti_i),
906
        .i7_wb_bte_i(i7_wb_bte_i),
907
 
908
 
909
        .t0_wb_cyc_o(z_wb_cyc_i),
910
        .t0_wb_stb_o(z_wb_stb_i),
911
        .t0_wb_adr_o(z_wb_adr_i),
912
        .t0_wb_sel_o(z_wb_sel_i),
913
        .t0_wb_we_o(z_wb_we_i),
914
        .t0_wb_dat_o(z_wb_dat_i),
915
        .t0_wb_dat_i(z_wb_dat_t),
916
        .t0_wb_ack_i(z_wb_ack_t),
917
        .t0_wb_err_i(z_wb_err_t),
918
        .t0_wb_cti_o(z_wb_cti_i),
919
        .t0_wb_bte_o(z_wb_bte_i)
920
 
921
);
922
 
923
//
924
// From initiators to targets 1-8 (lower part)
925
//
926
tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,
927
        t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(
928
 
929
 
930
        .i0_wb_cyc_i(z_wb_cyc_i),
931
        .i0_wb_stb_i(z_wb_stb_i),
932
        .i0_wb_adr_i(z_wb_adr_i),
933
        .i0_wb_sel_i(z_wb_sel_i),
934
        .i0_wb_we_i(z_wb_we_i),
935
        .i0_wb_dat_i(z_wb_dat_i),
936
        .i0_wb_dat_o(z_wb_dat_t),
937
        .i0_wb_ack_o(z_wb_ack_t),
938
        .i0_wb_err_o(z_wb_err_t),
939
        .i0_wb_cti_i(z_wb_cti_i),
940
        .i0_wb_bte_i(z_wb_bte_i),
941
 
942
        .t0_wb_cyc_o(t1_wb_cyc_o),
943
        .t0_wb_stb_o(t1_wb_stb_o),
944
        .t0_wb_adr_o(t1_wb_adr_o),
945
        .t0_wb_sel_o(t1_wb_sel_o),
946
        .t0_wb_we_o(t1_wb_we_o),
947
        .t0_wb_dat_o(t1_wb_dat_o),
948
        .t0_wb_dat_i(t1_wb_dat_i),
949
        .t0_wb_ack_i(t1_wb_ack_i),
950
        .t0_wb_err_i(t1_wb_err_i),
951
        .t0_wb_cti_o(t1_wb_cti_o),
952
        .t0_wb_bte_o(t1_wb_bte_o),
953
 
954
        .t1_wb_cyc_o(t2_wb_cyc_o),
955
        .t1_wb_stb_o(t2_wb_stb_o),
956
        .t1_wb_adr_o(t2_wb_adr_o),
957
        .t1_wb_sel_o(t2_wb_sel_o),
958
        .t1_wb_we_o(t2_wb_we_o),
959
        .t1_wb_dat_o(t2_wb_dat_o),
960
        .t1_wb_dat_i(t2_wb_dat_i),
961
        .t1_wb_ack_i(t2_wb_ack_i),
962
        .t1_wb_err_i(t2_wb_err_i),
963
        .t1_wb_cti_o(t2_wb_cti_o),
964
        .t1_wb_bte_o(t2_wb_bte_o),
965
 
966
        .t2_wb_cyc_o(t3_wb_cyc_o),
967
        .t2_wb_stb_o(t3_wb_stb_o),
968
        .t2_wb_adr_o(t3_wb_adr_o),
969
        .t2_wb_sel_o(t3_wb_sel_o),
970
        .t2_wb_we_o(t3_wb_we_o),
971
        .t2_wb_dat_o(t3_wb_dat_o),
972
        .t2_wb_dat_i(t3_wb_dat_i),
973
        .t2_wb_ack_i(t3_wb_ack_i),
974
        .t2_wb_err_i(t3_wb_err_i),
975
        .t2_wb_cti_o(t3_wb_cti_o),
976
        .t2_wb_bte_o(t3_wb_bte_o),
977
 
978
        .t3_wb_cyc_o(t4_wb_cyc_o),
979
        .t3_wb_stb_o(t4_wb_stb_o),
980
        .t3_wb_adr_o(t4_wb_adr_o),
981
        .t3_wb_sel_o(t4_wb_sel_o),
982
        .t3_wb_we_o(t4_wb_we_o),
983
        .t3_wb_dat_o(t4_wb_dat_o),
984
        .t3_wb_dat_i(t4_wb_dat_i),
985
        .t3_wb_ack_i(t4_wb_ack_i),
986
        .t3_wb_err_i(t4_wb_err_i),
987
        .t3_wb_cti_o(t4_wb_cti_o),
988
        .t3_wb_bte_o(t4_wb_bte_o),
989
 
990
        .t4_wb_cyc_o(t5_wb_cyc_o),
991
        .t4_wb_stb_o(t5_wb_stb_o),
992
        .t4_wb_adr_o(t5_wb_adr_o),
993
        .t4_wb_sel_o(t5_wb_sel_o),
994
        .t4_wb_we_o(t5_wb_we_o),
995
        .t4_wb_dat_o(t5_wb_dat_o),
996
        .t4_wb_dat_i(t5_wb_dat_i),
997
        .t4_wb_ack_i(t5_wb_ack_i),
998
        .t4_wb_err_i(t5_wb_err_i),
999
        .t4_wb_cti_o(t5_wb_cti_o),
1000
        .t4_wb_bte_o(t5_wb_bte_o),
1001
 
1002
        .t5_wb_cyc_o(t6_wb_cyc_o),
1003
        .t5_wb_stb_o(t6_wb_stb_o),
1004
        .t5_wb_adr_o(t6_wb_adr_o),
1005
        .t5_wb_sel_o(t6_wb_sel_o),
1006
        .t5_wb_we_o(t6_wb_we_o),
1007
        .t5_wb_dat_o(t6_wb_dat_o),
1008
        .t5_wb_dat_i(t6_wb_dat_i),
1009
        .t5_wb_ack_i(t6_wb_ack_i),
1010
        .t5_wb_err_i(t6_wb_err_i),
1011
        .t5_wb_cti_o(t6_wb_cti_o),
1012
        .t5_wb_bte_o(t6_wb_bte_o),
1013
 
1014
        .t6_wb_cyc_o(t7_wb_cyc_o),
1015
        .t6_wb_stb_o(t7_wb_stb_o),
1016
        .t6_wb_adr_o(t7_wb_adr_o),
1017
        .t6_wb_sel_o(t7_wb_sel_o),
1018
        .t6_wb_we_o(t7_wb_we_o),
1019
        .t6_wb_dat_o(t7_wb_dat_o),
1020
        .t6_wb_dat_i(t7_wb_dat_i),
1021
        .t6_wb_ack_i(t7_wb_ack_i),
1022
        .t6_wb_err_i(t7_wb_err_i),
1023
        .t6_wb_cti_o(t7_wb_cti_o),
1024
        .t6_wb_bte_o(t7_wb_bte_o),
1025
 
1026
        .t7_wb_cyc_o(t8_wb_cyc_o),
1027
        .t7_wb_stb_o(t8_wb_stb_o),
1028
        .t7_wb_adr_o(t8_wb_adr_o),
1029
        .t7_wb_sel_o(t8_wb_sel_o),
1030
        .t7_wb_we_o(t8_wb_we_o),
1031
        .t7_wb_dat_o(t8_wb_dat_o),
1032
        .t7_wb_dat_i(t8_wb_dat_i),
1033
        .t7_wb_ack_i(t8_wb_ack_i),
1034
        .t7_wb_err_i(t8_wb_err_i),
1035
        .t7_wb_cti_o(t8_wb_cti_o),
1036
        .t7_wb_bte_o(t8_wb_bte_o),
1037
 
1038
 
1039
);
1040
 
1041
endmodule
1042
 
1043
//
1044
// Multiple initiator to single target
1045
//
1046
module tc_mi_to_st (
1047
        wb_clk_i,
1048
        wb_rst_i,
1049
        i0_wb_cyc_i,
1050
        i0_wb_stb_i,
1051
        i0_wb_adr_i,
1052
        i0_wb_sel_i,
1053
        i0_wb_we_i,
1054
        i0_wb_dat_i,
1055
        i0_wb_dat_o,
1056
        i0_wb_ack_o,
1057
        i0_wb_err_o,
1058
        i0_wb_cti_i,
1059
        i0_wb_bte_i,
1060
 
1061
        i1_wb_cyc_i,
1062
        i1_wb_stb_i,
1063
        i1_wb_adr_i,
1064
        i1_wb_sel_i,
1065
        i1_wb_we_i,
1066
        i1_wb_dat_i,
1067
        i1_wb_dat_o,
1068
        i1_wb_ack_o,
1069
        i1_wb_err_o,
1070
        i1_wb_cti_i,
1071
        i1_wb_bte_i,
1072
 
1073
        i2_wb_cyc_i,
1074
        i2_wb_stb_i,
1075
        i2_wb_adr_i,
1076
        i2_wb_sel_i,
1077
        i2_wb_we_i,
1078
        i2_wb_dat_i,
1079
        i2_wb_dat_o,
1080
        i2_wb_ack_o,
1081
        i2_wb_err_o,
1082
        i2_wb_cti_i,
1083
        i2_wb_bte_i,
1084
 
1085
        i3_wb_cyc_i,
1086
        i3_wb_stb_i,
1087
        i3_wb_adr_i,
1088
        i3_wb_sel_i,
1089
        i3_wb_we_i,
1090
        i3_wb_dat_i,
1091
        i3_wb_dat_o,
1092
        i3_wb_ack_o,
1093
        i3_wb_err_o,
1094
        i3_wb_cti_i,
1095
        i3_wb_bte_i,
1096
 
1097
        i4_wb_cyc_i,
1098
        i4_wb_stb_i,
1099
        i4_wb_adr_i,
1100
        i4_wb_sel_i,
1101
        i4_wb_we_i,
1102
        i4_wb_dat_i,
1103
        i4_wb_dat_o,
1104
        i4_wb_ack_o,
1105
        i4_wb_err_o,
1106
        i4_wb_cti_i,
1107
        i4_wb_bte_i,
1108
 
1109
        i5_wb_cyc_i,
1110
        i5_wb_stb_i,
1111
        i5_wb_adr_i,
1112
        i5_wb_sel_i,
1113
        i5_wb_we_i,
1114
        i5_wb_dat_i,
1115
        i5_wb_dat_o,
1116
        i5_wb_ack_o,
1117
        i5_wb_err_o,
1118
        i5_wb_cti_i,
1119
        i5_wb_bte_i,
1120
 
1121
        i6_wb_cyc_i,
1122
        i6_wb_stb_i,
1123
        i6_wb_adr_i,
1124
        i6_wb_sel_i,
1125
        i6_wb_we_i,
1126
        i6_wb_dat_i,
1127
        i6_wb_dat_o,
1128
        i6_wb_ack_o,
1129
        i6_wb_err_o,
1130
        i6_wb_cti_i,
1131
        i6_wb_bte_i,
1132
 
1133
        i7_wb_cyc_i,
1134
        i7_wb_stb_i,
1135
        i7_wb_adr_i,
1136
        i7_wb_sel_i,
1137
        i7_wb_we_i,
1138
        i7_wb_dat_i,
1139
        i7_wb_dat_o,
1140
        i7_wb_ack_o,
1141
        i7_wb_err_o,
1142
        i7_wb_cti_i,
1143
        i7_wb_bte_i,
1144
 
1145
 
1146
        t0_wb_cyc_o,
1147
        t0_wb_stb_o,
1148
        t0_wb_adr_o,
1149
        t0_wb_sel_o,
1150
        t0_wb_we_o,
1151
        t0_wb_dat_o,
1152
        t0_wb_dat_i,
1153
        t0_wb_ack_i,
1154
        t0_wb_err_i,
1155
        t0_wb_cti_o,
1156
        t0_wb_bte_o
1157
 
1158
);
1159
 
1160
//
1161
// Parameters
1162
//
1163
parameter               t0_addr_w = 2;
1164
parameter               t0_addr = 2'b00;
1165
parameter               multitarg = 1'b0;
1166
parameter               t17_addr_w = 2;
1167
parameter               t17_addr = 2'b00;
1168
 
1169
//
1170
// I/O Ports
1171
//
1172
input                   wb_clk_i;
1173
input                   wb_rst_i;
1174
//
1175
// WB slave i/f connecting initiator 0
1176
//
1177
input                   i0_wb_cyc_i;
1178
input                   i0_wb_stb_i;
1179
input   [`TC_AW-1:0]     i0_wb_adr_i;
1180
input   [`TC_BSW-1:0]    i0_wb_sel_i;
1181
input                   i0_wb_we_i;
1182
input   [`TC_DW-1:0]     i0_wb_dat_i;
1183
output  [`TC_DW-1:0]     i0_wb_dat_o;
1184
output                  i0_wb_ack_o;
1185
output                  i0_wb_err_o;
1186
input   [2:0]            i0_wb_cti_i;
1187
input   [1:0]            i0_wb_bte_i;
1188
 
1189
//
1190
// WB slave i/f connecting initiator 1
1191
//
1192
input                   i1_wb_cyc_i;
1193
input                   i1_wb_stb_i;
1194
input   [`TC_AW-1:0]     i1_wb_adr_i;
1195
input   [`TC_BSW-1:0]    i1_wb_sel_i;
1196
input                   i1_wb_we_i;
1197
input   [`TC_DW-1:0]     i1_wb_dat_i;
1198
output  [`TC_DW-1:0]     i1_wb_dat_o;
1199
output                  i1_wb_ack_o;
1200
output                  i1_wb_err_o;
1201
input   [2:0]            i1_wb_cti_i;
1202
input   [1:0]            i1_wb_bte_i;
1203
 
1204
//
1205
// WB slave i/f connecting initiator 2
1206
//
1207
input                   i2_wb_cyc_i;
1208
input                   i2_wb_stb_i;
1209
input   [`TC_AW-1:0]     i2_wb_adr_i;
1210
input   [`TC_BSW-1:0]    i2_wb_sel_i;
1211
input                   i2_wb_we_i;
1212
input   [`TC_DW-1:0]     i2_wb_dat_i;
1213
output  [`TC_DW-1:0]     i2_wb_dat_o;
1214
output                  i2_wb_ack_o;
1215
output                  i2_wb_err_o;
1216
input   [2:0]            i2_wb_cti_i;
1217
input   [1:0]            i2_wb_bte_i;
1218
 
1219
//
1220
// WB slave i/f connecting initiator 3
1221
//
1222
input                   i3_wb_cyc_i;
1223
input                   i3_wb_stb_i;
1224
input   [`TC_AW-1:0]     i3_wb_adr_i;
1225
input   [`TC_BSW-1:0]    i3_wb_sel_i;
1226
input                   i3_wb_we_i;
1227
input   [`TC_DW-1:0]     i3_wb_dat_i;
1228
output  [`TC_DW-1:0]     i3_wb_dat_o;
1229
output                  i3_wb_ack_o;
1230
output                  i3_wb_err_o;
1231
input   [2:0]            i3_wb_cti_i;
1232
input   [1:0]            i3_wb_bte_i;
1233
 
1234
//
1235
// WB slave i/f connecting initiator 4
1236
//
1237
input                   i4_wb_cyc_i;
1238
input                   i4_wb_stb_i;
1239
input   [`TC_AW-1:0]     i4_wb_adr_i;
1240
input   [`TC_BSW-1:0]    i4_wb_sel_i;
1241
input                   i4_wb_we_i;
1242
input   [`TC_DW-1:0]     i4_wb_dat_i;
1243
output  [`TC_DW-1:0]     i4_wb_dat_o;
1244
output                  i4_wb_ack_o;
1245
output                  i4_wb_err_o;
1246
input   [2:0]            i4_wb_cti_i;
1247
input   [1:0]            i4_wb_bte_i;
1248
 
1249
//
1250
// WB slave i/f connecting initiator 5
1251
//
1252
input                   i5_wb_cyc_i;
1253
input                   i5_wb_stb_i;
1254
input   [`TC_AW-1:0]     i5_wb_adr_i;
1255
input   [`TC_BSW-1:0]    i5_wb_sel_i;
1256
input                   i5_wb_we_i;
1257
input   [`TC_DW-1:0]     i5_wb_dat_i;
1258
output  [`TC_DW-1:0]     i5_wb_dat_o;
1259
output                  i5_wb_ack_o;
1260
output                  i5_wb_err_o;
1261
input   [2:0]            i5_wb_cti_i;
1262
input   [1:0]            i5_wb_bte_i;
1263
 
1264
//
1265
// WB slave i/f connecting initiator 6
1266
//
1267
input                   i6_wb_cyc_i;
1268
input                   i6_wb_stb_i;
1269
input   [`TC_AW-1:0]     i6_wb_adr_i;
1270
input   [`TC_BSW-1:0]    i6_wb_sel_i;
1271
input                   i6_wb_we_i;
1272
input   [`TC_DW-1:0]     i6_wb_dat_i;
1273
output  [`TC_DW-1:0]     i6_wb_dat_o;
1274
output                  i6_wb_ack_o;
1275
output                  i6_wb_err_o;
1276
input   [2:0]            i6_wb_cti_i;
1277
input   [1:0]            i6_wb_bte_i;
1278
 
1279
//
1280
// WB slave i/f connecting initiator 7
1281
//
1282
input                   i7_wb_cyc_i;
1283
input                   i7_wb_stb_i;
1284
input   [`TC_AW-1:0]     i7_wb_adr_i;
1285
input   [`TC_BSW-1:0]    i7_wb_sel_i;
1286
input                   i7_wb_we_i;
1287
input   [`TC_DW-1:0]     i7_wb_dat_i;
1288
output  [`TC_DW-1:0]     i7_wb_dat_o;
1289
output                  i7_wb_ack_o;
1290
output                  i7_wb_err_o;
1291
input   [2:0]            i7_wb_cti_i;
1292
input   [1:0]            i7_wb_bte_i;
1293
 
1294
 
1295
//
1296
// WB master i/f connecting target
1297
//
1298
output                  t0_wb_cyc_o;
1299
output                  t0_wb_stb_o;
1300
output  [`TC_AW-1:0]     t0_wb_adr_o;
1301
output  [`TC_BSW-1:0]    t0_wb_sel_o;
1302
output                  t0_wb_we_o;
1303
output  [`TC_DW-1:0]     t0_wb_dat_o;
1304
input   [`TC_DW-1:0]     t0_wb_dat_i;
1305
input                   t0_wb_ack_i;
1306
input                   t0_wb_err_i;
1307
output  [2:0]            t0_wb_cti_o;
1308
output  [1:0]            t0_wb_bte_o;
1309
 
1310
//
1311
// Internal wires & registers
1312
//
1313
wire    [`TC_IIN_W-1:0]  i0_in, i1_in,
1314
                        i2_in, i3_in,
1315
                        i4_in, i5_in,
1316
                        i6_in, i7_in;
1317
wire    [`TC_TIN_W-1:0]  i0_out, i1_out,
1318
                        i2_out, i3_out,
1319
                        i4_out, i5_out,
1320
                        i6_out, i7_out;
1321
wire    [`TC_IIN_W-1:0]  t0_out;
1322
wire    [`TC_TIN_W-1:0]  t0_in;
1323
wire    [7:0]            req_i;
1324
wire    [2:0]            req_won;
1325
reg                     req_cont;
1326
reg     [2:0]            req_r;
1327
//
1328
// Group WB initiator 0 i/f inputs and outputs
1329
//
1330
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
1331
        i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i};
1332
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
1333
 
1334
//
1335
// Group WB initiator 1 i/f inputs and outputs
1336
//
1337
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i,
1338
        i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i, i1_wb_cti_i, i1_wb_bte_i};
1339
assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out;
1340
 
1341
//
1342
// Group WB initiator 2 i/f inputs and outputs
1343
//
1344
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i,
1345
        i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i, i2_wb_cti_i, i2_wb_bte_i};
1346
assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out;
1347
 
1348
//
1349
// Group WB initiator 3 i/f inputs and outputs
1350
//
1351
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i,
1352
        i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i, i3_wb_cti_i, i3_wb_bte_i};
1353
assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out;
1354
 
1355
//
1356
// Group WB initiator 4 i/f inputs and outputs
1357
//
1358
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i,
1359
        i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i, i4_wb_cti_i, i4_wb_bte_i};
1360
assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out;
1361
 
1362
//
1363
// Group WB initiator 5 i/f inputs and outputs
1364
//
1365
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i,
1366
        i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i, i5_wb_cti_i, i5_wb_bte_i};
1367
assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out;
1368
 
1369
//
1370
// Group WB initiator 6 i/f inputs and outputs
1371
//
1372
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i,
1373
        i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i, i6_wb_cti_i, i6_wb_bte_i};
1374
assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out;
1375
 
1376
//
1377
// Group WB initiator 7 i/f inputs and outputs
1378
//
1379
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i,
1380
        i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i, i7_wb_cti_i, i7_wb_bte_i};
1381
assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out;
1382
 
1383
 
1384
//
1385
// Group WB target 0 i/f inputs and outputs
1386
//
1387
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
1388
                t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out;
1389
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
1390
 
1391
//
1392
// Assign to WB initiator i/f outputs
1393
//
1394
// Either inputs from the target are assigned or zeros.
1395
//
1396
assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}};
1397
assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}};
1398
assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}};
1399
assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}};
1400
assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}};
1401
assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}};
1402
assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}};
1403
assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}};
1404
 
1405
//
1406
// Assign to WB target i/f outputs
1407
//
1408
// Assign inputs from initiator to target outputs according to
1409
// which initiator has won. If there is no request for the target,
1410
// assign zeros.
1411
//
1412
assign t0_out = (req_won == 3'd0) ? i0_in :
1413
                (req_won == 3'd1) ? i1_in :
1414
                (req_won == 3'd2) ? i2_in :
1415
                (req_won == 3'd3) ? i3_in :
1416
                (req_won == 3'd4) ? i4_in :
1417
                (req_won == 3'd5) ? i5_in :
1418
                (req_won == 3'd6) ? i6_in :
1419
                (req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}};
1420
 
1421
//
1422
// Determine if an initiator has address of the target.
1423
//
1424
assign req_i[0] = i0_wb_cyc_i &
1425
        ((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1426
         multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1427
assign req_i[1] = i1_wb_cyc_i &
1428
        ((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1429
         multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1430
assign req_i[2] = i2_wb_cyc_i &
1431
        ((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1432
         multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1433
assign req_i[3] = i3_wb_cyc_i &
1434
        ((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1435
         multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1436
assign req_i[4] = i4_wb_cyc_i &
1437
        ((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1438
         multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1439
assign req_i[5] = i5_wb_cyc_i &
1440
        ((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1441
         multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1442
assign req_i[6] = i6_wb_cyc_i &
1443
        ((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1444
         multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1445
assign req_i[7] = i7_wb_cyc_i &
1446
        ((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
1447
         multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
1448
 
1449
//
1450
// Determine who gets current access to the target.
1451
//
1452
// If current initiator still asserts request, do nothing
1453
// (keep current initiator).
1454
// Otherwise check each initiator's request, starting from initiator 0
1455
// (highest priority).
1456
// If there is no requests from initiators, park initiator 0.
1457
//
1458
assign req_won = req_cont ? req_r :
1459
                 req_i[0] ? 3'd0 :
1460
                 req_i[1] ? 3'd1 :
1461
                 req_i[2] ? 3'd2 :
1462
                 req_i[3] ? 3'd3 :
1463
                 req_i[4] ? 3'd4 :
1464
                 req_i[5] ? 3'd5 :
1465
                 req_i[6] ? 3'd6 :
1466
                 req_i[7] ? 3'd7 : 3'd0;
1467
 
1468
//
1469
// Check if current initiator still wants access to the target and if
1470
// it does, assert req_cont.
1471
//
1472
always @(req_r or req_i)
1473
        case (req_r)    // synopsys parallel_case
1474
                3'd0: req_cont = req_i[0];
1475
                3'd1: req_cont = req_i[1];
1476
                3'd2: req_cont = req_i[2];
1477
                3'd3: req_cont = req_i[3];
1478
                3'd4: req_cont = req_i[4];
1479
                3'd5: req_cont = req_i[5];
1480
                3'd6: req_cont = req_i[6];
1481
                3'd7: req_cont = req_i[7];
1482
        endcase
1483
 
1484
//
1485
// Register who has current access to the target.
1486
//
1487
always @(posedge wb_clk_i or posedge wb_rst_i)
1488
        if (wb_rst_i)
1489
                req_r <= #1 3'd0;
1490
        else
1491
                req_r <= #1 req_won;
1492
 
1493
endmodule
1494
 
1495
//
1496
// Single initiator to multiple targets
1497
//
1498
module tc_si_to_mt (
1499
 
1500
        i0_wb_cyc_i,
1501
        i0_wb_stb_i,
1502
        i0_wb_adr_i,
1503
        i0_wb_sel_i,
1504
        i0_wb_we_i,
1505
        i0_wb_dat_i,
1506
        i0_wb_dat_o,
1507
        i0_wb_ack_o,
1508
        i0_wb_err_o,
1509
        i0_wb_cti_i,
1510
        i0_wb_bte_i,
1511
 
1512
        t0_wb_cyc_o,
1513
        t0_wb_stb_o,
1514
        t0_wb_adr_o,
1515
        t0_wb_sel_o,
1516
        t0_wb_we_o,
1517
        t0_wb_dat_o,
1518
        t0_wb_dat_i,
1519
        t0_wb_ack_i,
1520
        t0_wb_err_i,
1521
        t0_wb_cti_o,
1522
        t0_wb_bte_o,
1523
 
1524
        t1_wb_cyc_o,
1525
        t1_wb_stb_o,
1526
        t1_wb_adr_o,
1527
        t1_wb_sel_o,
1528
        t1_wb_we_o,
1529
        t1_wb_dat_o,
1530
        t1_wb_dat_i,
1531
        t1_wb_ack_i,
1532
        t1_wb_err_i,
1533
        t1_wb_cti_o,
1534
        t1_wb_bte_o,
1535
 
1536
        t2_wb_cyc_o,
1537
        t2_wb_stb_o,
1538
        t2_wb_adr_o,
1539
        t2_wb_sel_o,
1540
        t2_wb_we_o,
1541
        t2_wb_dat_o,
1542
        t2_wb_dat_i,
1543
        t2_wb_ack_i,
1544
        t2_wb_err_i,
1545
        t2_wb_cti_o,
1546
        t2_wb_bte_o,
1547
 
1548
        t3_wb_cyc_o,
1549
        t3_wb_stb_o,
1550
        t3_wb_adr_o,
1551
        t3_wb_sel_o,
1552
        t3_wb_we_o,
1553
        t3_wb_dat_o,
1554
        t3_wb_dat_i,
1555
        t3_wb_ack_i,
1556
        t3_wb_err_i,
1557
        t3_wb_cti_o,
1558
        t3_wb_bte_o,
1559
 
1560
        t4_wb_cyc_o,
1561
        t4_wb_stb_o,
1562
        t4_wb_adr_o,
1563
        t4_wb_sel_o,
1564
        t4_wb_we_o,
1565
        t4_wb_dat_o,
1566
        t4_wb_dat_i,
1567
        t4_wb_ack_i,
1568
        t4_wb_err_i,
1569
        t4_wb_cti_o,
1570
        t4_wb_bte_o,
1571
 
1572
        t5_wb_cyc_o,
1573
        t5_wb_stb_o,
1574
        t5_wb_adr_o,
1575
        t5_wb_sel_o,
1576
        t5_wb_we_o,
1577
        t5_wb_dat_o,
1578
        t5_wb_dat_i,
1579
        t5_wb_ack_i,
1580
        t5_wb_err_i,
1581
        t5_wb_cti_o,
1582
        t5_wb_bte_o,
1583
 
1584
        t6_wb_cyc_o,
1585
        t6_wb_stb_o,
1586
        t6_wb_adr_o,
1587
        t6_wb_sel_o,
1588
        t6_wb_we_o,
1589
        t6_wb_dat_o,
1590
        t6_wb_dat_i,
1591
        t6_wb_ack_i,
1592
        t6_wb_err_i,
1593
        t6_wb_cti_o,
1594
        t6_wb_bte_o,
1595
 
1596
        t7_wb_cyc_o,
1597
        t7_wb_stb_o,
1598
        t7_wb_adr_o,
1599
        t7_wb_sel_o,
1600
        t7_wb_we_o,
1601
        t7_wb_dat_o,
1602
        t7_wb_dat_i,
1603
        t7_wb_ack_i,
1604
        t7_wb_err_i,
1605
        t7_wb_cti_o,
1606
        t7_wb_bte_o
1607
 
1608
 
1609
);
1610
 
1611
//
1612
// Parameters
1613
//
1614
parameter               t0_addr_w = 3;
1615
parameter               t0_addr = 3'd0;
1616
parameter               t17_addr_w = 3;
1617
parameter               t1_addr = 3'd1;
1618
parameter               t2_addr = 3'd2;
1619
parameter               t3_addr = 3'd3;
1620
parameter               t4_addr = 3'd4;
1621
parameter               t5_addr = 3'd5;
1622
parameter               t6_addr = 3'd6;
1623
parameter               t7_addr = 3'd7;
1624
 
1625
//
1626
// I/O Ports
1627
//
1628
 
1629
//
1630
// WB slave i/f connecting initiator 0
1631
//
1632
input                   i0_wb_cyc_i;
1633
input                   i0_wb_stb_i;
1634
input   [`TC_AW-1:0]     i0_wb_adr_i;
1635
input   [`TC_BSW-1:0]    i0_wb_sel_i;
1636
input                   i0_wb_we_i;
1637
input   [`TC_DW-1:0]     i0_wb_dat_i;
1638
output  [`TC_DW-1:0]     i0_wb_dat_o;
1639
output                  i0_wb_ack_o;
1640
output                  i0_wb_err_o;
1641
input   [2:0]            i0_wb_cti_i;
1642
input   [1:0]            i0_wb_bte_i;
1643
//
1644
// WB master i/f connecting target 0
1645
//
1646
output                  t0_wb_cyc_o;
1647
output                  t0_wb_stb_o;
1648
output  [`TC_AW-1:0]     t0_wb_adr_o;
1649
output  [`TC_BSW-1:0]    t0_wb_sel_o;
1650
output                  t0_wb_we_o;
1651
output  [`TC_DW-1:0]     t0_wb_dat_o;
1652
input   [`TC_DW-1:0]     t0_wb_dat_i;
1653
input                   t0_wb_ack_i;
1654
input                   t0_wb_err_i;
1655
output  [2:0]            t0_wb_cti_o;
1656
output  [1:0]            t0_wb_bte_o;
1657
 
1658
//
1659
// WB master i/f connecting target 1
1660
//
1661
output                  t1_wb_cyc_o;
1662
output                  t1_wb_stb_o;
1663
output  [`TC_AW-1:0]     t1_wb_adr_o;
1664
output  [`TC_BSW-1:0]    t1_wb_sel_o;
1665
output                  t1_wb_we_o;
1666
output  [`TC_DW-1:0]     t1_wb_dat_o;
1667
input   [`TC_DW-1:0]     t1_wb_dat_i;
1668
input                   t1_wb_ack_i;
1669
input                   t1_wb_err_i;
1670
output  [2:0]            t1_wb_cti_o;
1671
output  [1:0]            t1_wb_bte_o;
1672
 
1673
//
1674
// WB master i/f connecting target 2
1675
//
1676
output                  t2_wb_cyc_o;
1677
output                  t2_wb_stb_o;
1678
output  [`TC_AW-1:0]     t2_wb_adr_o;
1679
output  [`TC_BSW-1:0]    t2_wb_sel_o;
1680
output                  t2_wb_we_o;
1681
output  [`TC_DW-1:0]     t2_wb_dat_o;
1682
input   [`TC_DW-1:0]     t2_wb_dat_i;
1683
input                   t2_wb_ack_i;
1684
input                   t2_wb_err_i;
1685
output  [2:0]            t2_wb_cti_o;
1686
output  [1:0]            t2_wb_bte_o;
1687
 
1688
//
1689
// WB master i/f connecting target 3
1690
//
1691
output                  t3_wb_cyc_o;
1692
output                  t3_wb_stb_o;
1693
output  [`TC_AW-1:0]     t3_wb_adr_o;
1694
output  [`TC_BSW-1:0]    t3_wb_sel_o;
1695
output                  t3_wb_we_o;
1696
output  [`TC_DW-1:0]     t3_wb_dat_o;
1697
input   [`TC_DW-1:0]     t3_wb_dat_i;
1698
input                   t3_wb_ack_i;
1699
input                   t3_wb_err_i;
1700
output  [2:0]            t3_wb_cti_o;
1701
output  [1:0]            t3_wb_bte_o;
1702
 
1703
//
1704
// WB master i/f connecting target 4
1705
//
1706
output                  t4_wb_cyc_o;
1707
output                  t4_wb_stb_o;
1708
output  [`TC_AW-1:0]     t4_wb_adr_o;
1709
output  [`TC_BSW-1:0]    t4_wb_sel_o;
1710
output                  t4_wb_we_o;
1711
output  [`TC_DW-1:0]     t4_wb_dat_o;
1712
input   [`TC_DW-1:0]     t4_wb_dat_i;
1713
input                   t4_wb_ack_i;
1714
input                   t4_wb_err_i;
1715
output  [2:0]            t4_wb_cti_o;
1716
output  [1:0]            t4_wb_bte_o;
1717
 
1718
//
1719
// WB master i/f connecting target 5
1720
//
1721
output                  t5_wb_cyc_o;
1722
output                  t5_wb_stb_o;
1723
output  [`TC_AW-1:0]     t5_wb_adr_o;
1724
output  [`TC_BSW-1:0]    t5_wb_sel_o;
1725
output                  t5_wb_we_o;
1726
output  [`TC_DW-1:0]     t5_wb_dat_o;
1727
input   [`TC_DW-1:0]     t5_wb_dat_i;
1728
input                   t5_wb_ack_i;
1729
input                   t5_wb_err_i;
1730
output  [2:0]            t5_wb_cti_o;
1731
output  [1:0]            t5_wb_bte_o;
1732
 
1733
//
1734
// WB master i/f connecting target 6
1735
//
1736
output                  t6_wb_cyc_o;
1737
output                  t6_wb_stb_o;
1738
output  [`TC_AW-1:0]     t6_wb_adr_o;
1739
output  [`TC_BSW-1:0]    t6_wb_sel_o;
1740
output                  t6_wb_we_o;
1741
output  [`TC_DW-1:0]     t6_wb_dat_o;
1742
input   [`TC_DW-1:0]     t6_wb_dat_i;
1743
input                   t6_wb_ack_i;
1744
input                   t6_wb_err_i;
1745
output  [2:0]            t6_wb_cti_o;
1746
output  [1:0]            t6_wb_bte_o;
1747
 
1748
//
1749
// WB master i/f connecting target 7
1750
//
1751
output                  t7_wb_cyc_o;
1752
output                  t7_wb_stb_o;
1753
output  [`TC_AW-1:0]     t7_wb_adr_o;
1754
output  [`TC_BSW-1:0]    t7_wb_sel_o;
1755
output                  t7_wb_we_o;
1756
output  [`TC_DW-1:0]     t7_wb_dat_o;
1757
input   [`TC_DW-1:0]     t7_wb_dat_i;
1758
input                   t7_wb_ack_i;
1759
input                   t7_wb_err_i;
1760
output  [2:0]            t7_wb_cti_o;
1761
output  [1:0]            t7_wb_bte_o;
1762
 
1763
 
1764
//
1765
// Internal wires & registers
1766
//
1767
wire    [`TC_IIN_W-1:0]  i0_in;
1768
wire    [`TC_TIN_W-1:0]  i0_out;
1769
wire    [`TC_IIN_W-1:0]  t0_out, t1_out,
1770
                        t2_out, t3_out,
1771
                        t4_out, t5_out,
1772
                        t6_out, t7_out;
1773
wire    [`TC_TIN_W-1:0]  t0_in, t1_in,
1774
                        t2_in, t3_in,
1775
                        t4_in, t5_in,
1776
                        t6_in, t7_in;
1777
wire    [7:0]            req_t;
1778
 
1779
//
1780
// Group WB initiator 0 i/f inputs and outputs
1781
//
1782
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
1783
                i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i};
1784
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
1785
//
1786
// Group WB target 0 i/f inputs and outputs
1787
//
1788
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
1789
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out;
1790
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
1791
 
1792
//
1793
// Group WB target 1 i/f inputs and outputs
1794
//
1795
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o,
1796
t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o, t1_wb_cti_o, t1_wb_bte_o} = t1_out;
1797
assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i};
1798
 
1799
//
1800
// Group WB target 2 i/f inputs and outputs
1801
//
1802
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o,
1803
t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o, t2_wb_cti_o, t2_wb_bte_o} = t2_out;
1804
assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i};
1805
 
1806
//
1807
// Group WB target 3 i/f inputs and outputs
1808
//
1809
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o,
1810
t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o, t3_wb_cti_o, t3_wb_bte_o} = t3_out;
1811
assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i};
1812
 
1813
//
1814
// Group WB target 4 i/f inputs and outputs
1815
//
1816
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o,
1817
t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o, t4_wb_cti_o, t4_wb_bte_o} = t4_out;
1818
assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i};
1819
 
1820
//
1821
// Group WB target 5 i/f inputs and outputs
1822
//
1823
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o,
1824
t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o, t5_wb_cti_o, t5_wb_bte_o} = t5_out;
1825
assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i};
1826
 
1827
//
1828
// Group WB target 6 i/f inputs and outputs
1829
//
1830
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o,
1831
t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o, t6_wb_cti_o, t6_wb_bte_o} = t6_out;
1832
assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i};
1833
 
1834
//
1835
// Group WB target 7 i/f inputs and outputs
1836
//
1837
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o,
1838
t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o, t7_wb_cti_o, t7_wb_bte_o} = t7_out;
1839
assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i};
1840
 
1841
//
1842
// Assign to WB target i/f outputs
1843
//
1844
// Either inputs from the initiator are assigned or zeros.
1845
//
1846
assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}};
1847
assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}};
1848
assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}};
1849
assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}};
1850
assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}};
1851
assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}};
1852
assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}};
1853
assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}};
1854
 
1855
//
1856
// Assign to WB initiator i/f outputs
1857
//
1858
// Assign inputs from target to initiator outputs according to
1859
// which target is accessed. If there is no request for a target,
1860
// assign zeros.
1861
//
1862
assign i0_out = req_t[0] ? t0_in :
1863
                req_t[1] ? t1_in :
1864
                req_t[2] ? t2_in :
1865
                req_t[3] ? t3_in :
1866
                req_t[4] ? t4_in :
1867
                req_t[5] ? t5_in :
1868
                req_t[6] ? t6_in :
1869
                req_t[7] ? t7_in : {`TC_TIN_W{1'b0}};
1870
 
1871
//
1872
// Determine which target is being accessed.
1873
//
1874
assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr);
1875
assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr);
1876
assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr);
1877
assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr);
1878
assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr);
1879
assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr);
1880
assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr);
1881
assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr);
1882
 
1883
endmodule

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