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ayersg |
`timescale 1ns / 1ps
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/*
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* File : uart_rx.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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* Modification History:
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* Rev Date Initials Description of Change
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* 1.0 26-May-2010 GEA Initial design.
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*
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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*
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* Description:
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* Recovers received data from the serial port with 16x clock over-sampling.
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* 'data_ready' is a synchronous pulse indicator. 8N1.
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*/
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module uart_rx(
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input clock,
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input reset,
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input RxD,
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input uart_tick_16x,
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output reg [7:0] RxD_data = 0,
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output data_ready
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);
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/* Synchronize incoming RxD */
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reg [1:0] RxD_sync = 2'b11; //0;
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always @(posedge clock) RxD_sync <= (uart_tick_16x) ? {RxD_sync[0], RxD} : RxD_sync;
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/* Filter Input */
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reg [1:0] RxD_cnt = 0;
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reg RxD_bit = 1; //0;
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always @(posedge clock) begin
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if (uart_tick_16x) begin
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case (RxD_sync[1])
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0: RxD_cnt <= (RxD_cnt == 2'b11) ? RxD_cnt : RxD_cnt + 1;
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1: RxD_cnt <= (RxD_cnt == 2'b00) ? RxD_cnt : RxD_cnt - 1;
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endcase
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RxD_bit <= (RxD_cnt == 2'b11) ? 0 : ((RxD_cnt == 2'b00) ? 1 : RxD_bit);
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end
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else begin
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RxD_cnt <= RxD_cnt;
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RxD_bit <= RxD_bit;
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end
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end
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/* State Definitions */
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localparam [3:0] IDLE=0, BIT_0=1, BIT_1=2, BIT_2=3, BIT_3=4, BIT_4=5, BIT_5=6,
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BIT_6=7, BIT_7=8, STOP=9;
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reg [3:0] state = IDLE;
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/* Next-bit spacing and clock locking */
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reg clock_lock = 0;
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reg [3:0] bit_spacing = 4'b1110; // Enable quick jumping from IDLE to BIT_0 when line was idle.
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always @(posedge clock) begin
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if (uart_tick_16x) begin
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if (~clock_lock) clock_lock <= ~RxD_bit; // We lock on when we detect a filtered 0 from idle
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else clock_lock <= ((state == IDLE) && (RxD_bit == 1'b1)) ? 0 : clock_lock;
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bit_spacing <= (clock_lock) ? bit_spacing + 1 : 4'b1110;
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end
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else begin
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clock_lock <= clock_lock;
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bit_spacing <= bit_spacing;
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end
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end
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wire next_bit = (bit_spacing == 4'b1111);
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/* State Machine */
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always @(posedge clock) begin
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if (reset) state <= IDLE;
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else if (uart_tick_16x) begin
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case (state)
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IDLE: state <= (next_bit & (RxD_bit == 1'b0)) ? BIT_0 : IDLE; // Start bit is 0
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BIT_0: state <= (next_bit) ? BIT_1 : BIT_0;
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BIT_1: state <= (next_bit) ? BIT_2 : BIT_1;
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BIT_2: state <= (next_bit) ? BIT_3 : BIT_2;
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BIT_3: state <= (next_bit) ? BIT_4 : BIT_3;
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BIT_4: state <= (next_bit) ? BIT_5 : BIT_4;
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BIT_5: state <= (next_bit) ? BIT_6 : BIT_5;
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BIT_6: state <= (next_bit) ? BIT_7 : BIT_6;
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BIT_7: state <= (next_bit) ? STOP : BIT_7;
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STOP: state <= (next_bit) ? IDLE : STOP;
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default: state <= 4'bxxxx;
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endcase
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end
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else state <= state;
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end
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/* Shift Register to Collect Rx bits as they come */
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wire capture = (uart_tick_16x & next_bit & (state!=IDLE) & (state!=STOP));
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always @(posedge clock) RxD_data <= (capture) ? {RxD_bit, RxD_data[7:1]} : RxD_data[7:0];
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assign data_ready = (uart_tick_16x & next_bit & (state==STOP));
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endmodule
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3 |
ayersg |
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