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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [gr-cpci-ax/] [config.h] - Blame information for rev 2

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/*
 * Automatically generated C config: don't edit
 */
#define AUTOCONF_INCLUDED
#define CONFIG_MCTRL_RMW 1
/*
 * Synthesis
 */
#undef  CONFIG_SYN_INFERRED
#define CONFIG_SYN_AXCEL 1
#undef  CONFIG_SYN_INFER_RAM
#undef  CONFIG_SYN_INFER_PADS
/*
 * Clock generation
 */
#undef  CONFIG_CLK_INFERRED
#define CONFIG_CLK_HCLKBUF 1
#define CONFIG_PROC_NUM (1)
/*
 * Processor
 */
/*
 * Integer unit
 */
#define CONFIG_IU_NWINDOWS (8)
#undef  CONFIG_IU_V8MULDIV
#define CONFIG_IU_LDELAY (1)
#define CONFIG_IU_WATCHPOINTS (0)
#undef  CONFIG_PWD
/*
 * Floating-point unit
 */
#undef  CONFIG_FPU_ENABLE
/*
 * Cache system
 */
#define CONFIG_ICACHE_ENABLE 1
#define CONFIG_ICACHE_ASSO1 1
#undef  CONFIG_ICACHE_ASSO2
#undef  CONFIG_ICACHE_ASSO3
#undef  CONFIG_ICACHE_ASSO4
#undef  CONFIG_ICACHE_SZ1
#undef  CONFIG_ICACHE_SZ2
#define CONFIG_ICACHE_SZ4 1
#undef  CONFIG_ICACHE_SZ8
#undef  CONFIG_ICACHE_SZ16
#undef  CONFIG_ICACHE_SZ32
#undef  CONFIG_ICACHE_SZ64
#undef  CONFIG_ICACHE_LZ16
#define CONFIG_ICACHE_LZ32 1
#undef  CONFIG_ICACHE_LRAM
#define CONFIG_DCACHE_ENABLE 1
#define CONFIG_DCACHE_ASSO1 1
#undef  CONFIG_DCACHE_ASSO2
#undef  CONFIG_DCACHE_ASSO3
#undef  CONFIG_DCACHE_ASSO4
#undef  CONFIG_DCACHE_SZ1
#undef  CONFIG_DCACHE_SZ2
#define CONFIG_DCACHE_SZ4 1
#undef  CONFIG_DCACHE_SZ8
#undef  CONFIG_DCACHE_SZ16
#undef  CONFIG_DCACHE_SZ32
#undef  CONFIG_DCACHE_SZ64
#undef  CONFIG_DCACHE_LZ16
#define CONFIG_DCACHE_LZ32 1
#undef  CONFIG_DCACHE_LRAM
/*
 * MMU
 */
#undef  CONFIG_MMU_ENABLE
/*
 * Debug Support Unit
 */
#define CONFIG_DSU_ENABLE 1
#undef  CONFIG_DSU_ITRACE
#undef  CONFIG_DSU_ATRACE
/*
 * AMBA configuration
 */
#define CONFIG_AHB_DEFMST (0)
#undef  CONFIG_AHB_RROBIN
#undef  CONFIG_AHB_SPLIT
#define CONFIG_AHB_IOADDR FFF
#define CONFIG_APB_HADDR 800
/*
 * Debug Link
 */
#define CONFIG_DSU_UART 1
/*
 * Peripherals
 */
/*
 * Memory controllers
 */
#undef  CONFIG_MCTRL_NONE
#define CONFIG_MCTRL_SMALL 1
#undef  CONFIG_MCTRL_LEON2
#define CONFIG_MCTRL_PROMWS (3)
#define CONFIG_MCTRL_RAMWS (0)
#define CONFIG_MCTRL_SDRAM 1
#define CONFIG_MCTRL_SDRAM_BUS64 1
/*
 * On-chip RAM
 */
#undef  CONFIG_AHBRAM_ENABLE
/*
 * PCI
 */
#define CONFIG_PCI_ENABLE 1
#define CONFIG_PCI_SIMPLE_TARGET 1
#undef  CONFIG_PCI_MASTER_TAGET
#undef  CONFIG_PCI_MASTER_TAGET_DMA
#define CONFIG_PCI_VENDORID 16E3
#define CONFIG_PCI_DEVICEID 0210
#undef  CONFIG_PCI_ARBITER
#undef  CONFIG_PCI_TRACE
/*
 * UARTs, timers and irq control
 */
#define CONFIG_UART1_ENABLE 1
#define CONFIG_UA1_FIFO1 1
#undef  CONFIG_UA1_FIFO2
#undef  CONFIG_UA1_FIFO4
#undef  CONFIG_UA1_FIFO8
#undef  CONFIG_UA1_FIFO16
#undef  CONFIG_UA1_FIFO32
#define CONFIG_UART2_ENABLE 1
#define CONFIG_UA2_FIFO1 1
#undef  CONFIG_UA2_FIFO2
#undef  CONFIG_UA2_FIFO4
#undef  CONFIG_UA2_FIFO8
#undef  CONFIG_UA2_FIFO16
#undef  CONFIG_UA2_FIFO32
#define CONFIG_IRQ3_ENABLE 1
#define CONFIG_GPT_ENABLE 1
#define CONFIG_GPT_NTIM (2)
#define CONFIG_GPT_SW (8)
#define CONFIG_GPT_TW (32)
#define CONFIG_GPT_IRQ (8)
#define CONFIG_GPT_SEPIRQ 1
/*
 * VHDL Debugging
 */
#undef  CONFIG_IU_DISAS
#define CONFIG_DEBUG_UART 1
#undef  CONFIG_DEBUG_PC32

Line No.	Rev	Author	Line
1	2	dimamali	`/*`
2			`* Automatically generated C config: don't edit`
3			`*/`
4			`#define AUTOCONF_INCLUDED`
5			`#define CONFIG_MCTRL_RMW 1`
6			`/*`
7			`* Synthesis`
8			`*/`
9			`#undef CONFIG_SYN_INFERRED`
10			`#define CONFIG_SYN_AXCEL 1`
11			`#undef CONFIG_SYN_INFER_RAM`
12			`#undef CONFIG_SYN_INFER_PADS`
13			`/*`
14			`* Clock generation`
15			`*/`
16			`#undef CONFIG_CLK_INFERRED`
17			`#define CONFIG_CLK_HCLKBUF 1`
18			`#define CONFIG_PROC_NUM (1)`
19			`/*`
20			`* Processor`
21			`*/`
22			`/*`
23			`* Integer unit`
24			`*/`
25			`#define CONFIG_IU_NWINDOWS (8)`
26			`#undef CONFIG_IU_V8MULDIV`
27			`#define CONFIG_IU_LDELAY (1)`
28			`#define CONFIG_IU_WATCHPOINTS (0)`
29			`#undef CONFIG_PWD`
30			`/*`
31			`* Floating-point unit`
32			`*/`
33			`#undef CONFIG_FPU_ENABLE`
34			`/*`
35			`* Cache system`
36			`*/`
37			`#define CONFIG_ICACHE_ENABLE 1`
38			`#define CONFIG_ICACHE_ASSO1 1`
39			`#undef CONFIG_ICACHE_ASSO2`
40			`#undef CONFIG_ICACHE_ASSO3`
41			`#undef CONFIG_ICACHE_ASSO4`
42			`#undef CONFIG_ICACHE_SZ1`
43			`#undef CONFIG_ICACHE_SZ2`
44			`#define CONFIG_ICACHE_SZ4 1`
45			`#undef CONFIG_ICACHE_SZ8`
46			`#undef CONFIG_ICACHE_SZ16`
47			`#undef CONFIG_ICACHE_SZ32`
48			`#undef CONFIG_ICACHE_SZ64`
49			`#undef CONFIG_ICACHE_LZ16`
50			`#define CONFIG_ICACHE_LZ32 1`
51			`#undef CONFIG_ICACHE_LRAM`
52			`#define CONFIG_DCACHE_ENABLE 1`
53			`#define CONFIG_DCACHE_ASSO1 1`
54			`#undef CONFIG_DCACHE_ASSO2`
55			`#undef CONFIG_DCACHE_ASSO3`
56			`#undef CONFIG_DCACHE_ASSO4`
57			`#undef CONFIG_DCACHE_SZ1`
58			`#undef CONFIG_DCACHE_SZ2`
59			`#define CONFIG_DCACHE_SZ4 1`
60			`#undef CONFIG_DCACHE_SZ8`
61			`#undef CONFIG_DCACHE_SZ16`
62			`#undef CONFIG_DCACHE_SZ32`
63			`#undef CONFIG_DCACHE_SZ64`
64			`#undef CONFIG_DCACHE_LZ16`
65			`#define CONFIG_DCACHE_LZ32 1`
66			`#undef CONFIG_DCACHE_LRAM`
67			`/*`
68			`* MMU`
69			`*/`
70			`#undef CONFIG_MMU_ENABLE`
71			`/*`
72			`* Debug Support Unit`
73			`*/`
74			`#define CONFIG_DSU_ENABLE 1`
75			`#undef CONFIG_DSU_ITRACE`
76			`#undef CONFIG_DSU_ATRACE`
77			`/*`
78			`* AMBA configuration`
79			`*/`
80			`#define CONFIG_AHB_DEFMST (0)`
81			`#undef CONFIG_AHB_RROBIN`
82			`#undef CONFIG_AHB_SPLIT`
83			`#define CONFIG_AHB_IOADDR FFF`
84			`#define CONFIG_APB_HADDR 800`
85			`/*`
86			`* Debug Link`
87			`*/`
88			`#define CONFIG_DSU_UART 1`
89			`/*`
90			`* Peripherals`
91			`*/`
92			`/*`
93			`* Memory controllers`
94			`*/`
95			`#undef CONFIG_MCTRL_NONE`
96			`#define CONFIG_MCTRL_SMALL 1`
97			`#undef CONFIG_MCTRL_LEON2`
98			`#define CONFIG_MCTRL_PROMWS (3)`
99			`#define CONFIG_MCTRL_RAMWS (0)`
100			`#define CONFIG_MCTRL_SDRAM 1`
101			`#define CONFIG_MCTRL_SDRAM_BUS64 1`
102			`/*`
103			`* On-chip RAM`
104			`*/`
105			`#undef CONFIG_AHBRAM_ENABLE`
106			`/*`
107			`* PCI`
108			`*/`
109			`#define CONFIG_PCI_ENABLE 1`
110			`#define CONFIG_PCI_SIMPLE_TARGET 1`
111			`#undef CONFIG_PCI_MASTER_TAGET`
112			`#undef CONFIG_PCI_MASTER_TAGET_DMA`
113			`#define CONFIG_PCI_VENDORID 16E3`
114			`#define CONFIG_PCI_DEVICEID 0210`
115			`#undef CONFIG_PCI_ARBITER`
116			`#undef CONFIG_PCI_TRACE`
117			`/*`
118			`* UARTs, timers and irq control`
119			`*/`
120			`#define CONFIG_UART1_ENABLE 1`
121			`#define CONFIG_UA1_FIFO1 1`
122			`#undef CONFIG_UA1_FIFO2`
123			`#undef CONFIG_UA1_FIFO4`
124			`#undef CONFIG_UA1_FIFO8`
125			`#undef CONFIG_UA1_FIFO16`
126			`#undef CONFIG_UA1_FIFO32`
127			`#define CONFIG_UART2_ENABLE 1`
128			`#define CONFIG_UA2_FIFO1 1`
129			`#undef CONFIG_UA2_FIFO2`
130			`#undef CONFIG_UA2_FIFO4`
131			`#undef CONFIG_UA2_FIFO8`
132			`#undef CONFIG_UA2_FIFO16`
133			`#undef CONFIG_UA2_FIFO32`
134			`#define CONFIG_IRQ3_ENABLE 1`
135			`#define CONFIG_GPT_ENABLE 1`
136			`#define CONFIG_GPT_NTIM (2)`
137			`#define CONFIG_GPT_SW (8)`
138			`#define CONFIG_GPT_TW (32)`
139			`#define CONFIG_GPT_IRQ (8)`
140			`#define CONFIG_GPT_SEPIRQ 1`
141			`/*`
142			`* VHDL Debugging`
143			`*/`
144			`#undef CONFIG_IU_DISAS`
145			`#define CONFIG_DEBUG_UART 1`
146			`#undef CONFIG_DEBUG_PC32`

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [gr-cpci-ax/] [config.h] - Blame information for rev 2