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dimamali |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.ata.all;
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use gaisler.jtag.all;
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library esa;
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use esa.memoryctrl.all;
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use work.config.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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ncpu : integer := CFG_NCPU;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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freq : integer := 50000 -- frequency of main clock (used for PLLs)
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);
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port (
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resetn : in std_ulogic;
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clk : in std_ulogic;
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errorn : out std_ulogic;
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-- flash/ethernet bus
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address : out std_logic_vector(23 downto 0);
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data : inout std_logic_vector(31 downto 0);
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romsn : out std_ulogic;
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oen : out std_logic;
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writen : out std_logic;
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byten : out std_logic;
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wpn : out std_logic;
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-- SSRAM
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ssram_ce1n : out std_logic;
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ssram_ce2 : out std_logic;
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ssram_ce3n : out std_logic;
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ssram_wen : out std_logic;
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ssram_bw : out std_logic_vector (0 to 3);
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ssram_oen : out std_ulogic;
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ssaddr : out std_logic_vector(20 downto 2);
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ssdata : inout std_logic_vector(31 downto 0);
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ssram_clk : out std_ulogic;
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ssram_adscn : out std_ulogic;
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ssram_adsp_n : out std_ulogic;
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ssram_adv_n : out std_ulogic;
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-- pragma translate_off
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iosn : out std_ulogic;
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-- pragma translate_on
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ddr_clkin : in std_logic;
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ddr_clk : out std_logic;
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ddr_clkn : out std_logic;
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ddr_cke : out std_logic;
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ddr_csb : out std_logic;
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
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-- debug support unit
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dsubren : in std_ulogic;
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dsuact : out std_ulogic;
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-- console/debug UART
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rxd1 : in std_logic;
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txd1 : out std_logic;
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-- ATA signals
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ata_data : inout std_logic_vector(15 downto 0);
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ata_da : out std_logic_vector(2 downto 0);
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ata_cs0 : out std_logic;
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ata_cs1 : out std_logic;
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ata_dior : out std_logic;
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ata_diow : out std_logic;
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ata_iordy : in std_logic;
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ata_intrq : in std_logic;
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ata_dmarq : in std_logic;
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ata_dmack : out std_logic;
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-- Signals nedded to use CompactFlash with ATA controller
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cf_power : out std_logic; -- To turn on power to the CompactFlash
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cf_gnd_da : out std_logic_vector(10 downto 3); -- grounded address lines
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cf_atasel : out std_logic; -- grounded to select true IDE mode
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cf_we : out std_logic; -- should be connected to VCC in true IDE mode
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-- cf_csel : out std_logic;
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-- for smsc lan chip
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eth_aen : out std_logic;
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eth_readn : out std_logic;
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eth_writen: out std_logic;
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eth_nbe : out std_logic_vector(3 downto 0);
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eth_lclk : out std_ulogic;
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eth_nads : out std_logic;
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eth_ncycle : out std_logic;
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eth_wnr : out std_logic;
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eth_nvlbus : out std_logic;
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eth_nrdyrtn : out std_logic;
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eth_ndatacs : out std_logic;
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gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
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);
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end;
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architecture rtl of leon3mp is
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_ATA;
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signal vcc, gnd : std_logic_vector(7 downto 0);
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signal memi, smemi : memory_in_type;
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signal memo, smemo : memory_out_type;
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signal wpo : wprot_out_type;
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signal ddsi : ddrmem_in_type;
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signal ddso : ddrmem_out_type;
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signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
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signal ddr_clkv : std_logic_vector(2 downto 0);
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signal ddr_clkbv : std_logic_vector(2 downto 0);
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signal ddr_ckev : std_logic_vector(1 downto 0);
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signal ddr_csbv : std_logic_vector(1 downto 0);
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signal ddr_adl : std_logic_vector (13 downto 0);
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signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
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signal tck, tckn, tms, tdi, tdo : std_ulogic;
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signal ddrclk, ddrrst : std_ulogic;
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-- attribute syn_keep : boolean;
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-- attribute syn_preserve : boolean;
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-- attribute syn_keep of clkml : signal is true;
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-- attribute syn_preserve of clkml : signal is true;
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--for smc lan chip
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signal s_eth_aen : std_logic;
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signal s_eth_readn : std_logic;
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signal s_eth_writen: std_logic;
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signal s_eth_nbe : std_logic_vector(3 downto 0);
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signal ssd, prd : std_logic_vector(31 downto 0);
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector;
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signal clkm, rstn, ssram_clkl : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal u1i, dui : uart_in_type;
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signal u1o, duo : uart_out_type;
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signal irqi : irq_in_vector(0 to NCPU-1);
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signal irqo : irq_out_vector(0 to NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal cf : cf_out_type;
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signal atai : ata_in_type;
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signal atao : ata_out_type;
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signal gpti : gptimer_in_type;
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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constant IOAEN : integer := 1;
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constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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signal dsubre : std_ulogic;
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component smc_mctrl
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generic (
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hindex : integer := 0;
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pindex : integer := 0;
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romaddr : integer := 16#000#;
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rommask : integer := 16#E00#;
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ioaddr : integer := 16#200#;
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iomask : integer := 16#E00#;
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ramaddr : integer := 16#400#;
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rammask : integer := 16#C00#;
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paddr : integer := 0;
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pmask : integer := 16#fff#;
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wprot : integer := 0;
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invclk : integer := 0;
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fast : integer := 0;
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romasel : integer := 28;
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sdrasel : integer := 29;
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srbanks : integer := 4;
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ram8 : integer := 0;
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ram16 : integer := 0;
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sden : integer := 0;
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sepbus : integer := 0;
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sdbits : integer := 32;
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sdlsb : integer := 2;
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oepol : integer := 0;
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syncrst : integer := 0
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);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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memi : in memory_in_type;
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memo : out memory_out_type;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type;
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apbi : in apb_slv_in_type;
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apbo : out apb_slv_out_type;
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wpo : in wprot_out_type;
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sdo : out sdram_out_type;
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eth_aen : out std_ulogic; -- for smsc lan chip
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eth_readn : out std_ulogic; -- for smsc lan chip
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eth_writen: out std_ulogic; -- for smsc lan chip
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eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
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);
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end component;
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begin
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
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clklock <= cgo.clklock and lock;
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clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
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generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
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clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
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freq => freq)
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port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open,
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clk2x => open, sdclk => ssram_clkl, pciclk => open,
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cgi => cgi, cgo => cgo);
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ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
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port map (ssram_clk, ssram_clkl);
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rst0 : rstgen -- reset generator
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port map (resetn, clkm, clklock, rstn);
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- LEON3 processor and DSU -----------------------------------------
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----------------------------------------------------------------------
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l3 : if CFG_LEON3 = 1 generate
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cpu : for i in 0 to NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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end generate;
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errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
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dsugen : if CFG_DSU = 1 generate
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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|
|
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
|
319 |
|
|
|
320 |
|
|
dsui.enable <= '1';
|
321 |
|
|
|
322 |
|
|
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
|
323 |
|
|
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
|
324 |
|
|
end generate;
|
325 |
|
|
end generate;
|
326 |
|
|
nodcom : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; end generate;
|
327 |
|
|
|
328 |
|
|
dcomgen : if CFG_AHB_UART = 1 generate
|
329 |
|
|
dcom0 : ahbuart -- Debug UART
|
330 |
|
|
generic map (hindex => NCPU, pindex => 4, paddr => 7)
|
331 |
|
|
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
|
332 |
|
|
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
|
333 |
|
|
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
|
334 |
|
|
end generate;
|
335 |
|
|
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
|
336 |
|
|
|
337 |
|
|
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
|
338 |
|
|
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
|
339 |
|
|
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
|
340 |
|
|
open, open, open, open, open, open, open, gnd(0));
|
341 |
|
|
end generate;
|
342 |
|
|
|
343 |
|
|
----------------------------------------------------------------------
|
344 |
|
|
--- Memory controllers ----------------------------------------------
|
345 |
|
|
----------------------------------------------------------------------
|
346 |
|
|
|
347 |
|
|
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
|
348 |
|
|
sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
|
349 |
|
|
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
|
350 |
|
|
sden => 0, ram8 => 1)
|
351 |
|
|
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open,
|
352 |
|
|
s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
|
353 |
|
|
end generate;
|
354 |
|
|
|
355 |
|
|
wpn <= '1'; byten <= '0';
|
356 |
|
|
|
357 |
|
|
memi.brdyn <= '1'; memi.bexcn <= '1';
|
358 |
|
|
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
|
359 |
|
|
|
360 |
|
|
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
|
361 |
|
|
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
|
362 |
|
|
roms_pad : outpad generic map (tech => padtech)
|
363 |
|
|
port map (romsn, vcc(0));
|
364 |
|
|
end generate;
|
365 |
|
|
|
366 |
|
|
mgpads : if CFG_MCTRL_LEON2 = 1 generate -- prom/sram pads
|
367 |
|
|
addr_pad : outpadv generic map (width => 24, tech => padtech)
|
368 |
|
|
port map (address, memo.address(23 downto 0));
|
369 |
|
|
roms_pad : outpad generic map (tech => padtech)
|
370 |
|
|
port map (romsn, memo.romsn(0));
|
371 |
|
|
oen_pad : outpad generic map (tech => padtech)
|
372 |
|
|
port map (oen, memo.oen);
|
373 |
|
|
wri_pad : outpad generic map (tech => padtech)
|
374 |
|
|
port map (writen, memo.writen);
|
375 |
|
|
-- pragma translate_off
|
376 |
|
|
iosn_pad : outpad generic map (tech => padtech)
|
377 |
|
|
port map (iosn, memo.iosn);
|
378 |
|
|
-- pragma translate_on
|
379 |
|
|
|
380 |
|
|
ssram_adv_n_pad : outpad generic map (tech => padtech)
|
381 |
|
|
port map (ssram_adv_n, vcc(0));
|
382 |
|
|
ssram_adsp_n_pad : outpad generic map (tech => padtech)
|
383 |
|
|
port map (ssram_adsp_n, gnd(0));
|
384 |
|
|
ssaddr_pad : outpadv generic map (width => 19, tech => padtech)
|
385 |
|
|
port map (ssaddr, memo.address(20 downto 2));
|
386 |
|
|
ssram_adscn_pad : outpad generic map (tech => padtech)
|
387 |
|
|
port map (ssram_adscn, vcc(0));
|
388 |
|
|
ssram_ce1n_pad : outpad generic map (tech => padtech)
|
389 |
|
|
port map (ssram_ce1n, gnd(0));
|
390 |
|
|
ssram_ce2_pad : outpad generic map (tech => padtech)
|
391 |
|
|
port map (ssram_ce2, vcc(0));
|
392 |
|
|
ssrams_pad : outpad generic map ( tech => padtech)
|
393 |
|
|
port map (ssram_ce3n, memo.ramsn(0));
|
394 |
|
|
ssram_oen_pad : outpad generic map (tech => padtech)
|
395 |
|
|
port map (ssram_oen, memo.oen);
|
396 |
|
|
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
|
397 |
|
|
port map (ssram_bw, memo.wrn);
|
398 |
|
|
ssram_wri_pad : outpad generic map (tech => padtech)
|
399 |
|
|
port map (ssram_wen, memo.writen);
|
400 |
|
|
ssram_data_pads : iopadvv generic map (tech => padtech, width => 32)
|
401 |
|
|
port map (ssdata, memo.data, memo.vbdrive, ssd);
|
402 |
|
|
|
403 |
|
|
memi.data(31 downto 0) <= ssd when memo.ramsn(0) = '0' else prd;
|
404 |
|
|
|
405 |
|
|
-- for smc lan chip
|
406 |
|
|
eth_aen_pad : outpad generic map (tech => padtech)
|
407 |
|
|
port map (eth_aen, s_eth_aen);
|
408 |
|
|
eth_readn_pad : outpad generic map (tech => padtech)
|
409 |
|
|
port map (eth_readn, s_eth_readn);
|
410 |
|
|
eth_writen_pad : outpad generic map (tech => padtech)
|
411 |
|
|
port map (eth_writen, s_eth_writen);
|
412 |
|
|
eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
|
413 |
|
|
port map (eth_nbe, s_eth_nbe);
|
414 |
|
|
|
415 |
|
|
data_pad : iopadvv generic map (tech => padtech, width => 32)
|
416 |
|
|
port map (data(31 downto 0), memo.data(31 downto 0),
|
417 |
|
|
memo.vbdrive, prd);
|
418 |
|
|
end generate;
|
419 |
|
|
|
420 |
|
|
ddrsp0 : if (CFG_DDRSP /= 0) generate
|
421 |
|
|
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
|
422 |
|
|
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
|
423 |
|
|
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
|
424 |
|
|
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
|
425 |
|
|
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16)
|
426 |
|
|
port map (
|
427 |
|
|
resetn, rstn, ddr_clkin, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
|
428 |
|
|
ddr_clkv, ddr_clkbv, open, gnd(0),
|
429 |
|
|
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
|
430 |
|
|
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
|
431 |
|
|
ddr_ad <= ddr_adl(12 downto 0);
|
432 |
|
|
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
|
433 |
|
|
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
|
434 |
|
|
end generate;
|
435 |
|
|
|
436 |
|
|
ddrsp1 : if (CFG_DDRSP = 0) generate
|
437 |
|
|
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
|
438 |
|
|
end generate;
|
439 |
|
|
|
440 |
|
|
----------------------------------------------------------------------
|
441 |
|
|
--- APB Bridge and various periherals -------------------------------
|
442 |
|
|
----------------------------------------------------------------------
|
443 |
|
|
|
444 |
|
|
apb0 : apbctrl -- AHB/APB bridge
|
445 |
|
|
generic map (hindex => 1, haddr => CFG_APBADDR)
|
446 |
|
|
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
|
447 |
|
|
|
448 |
|
|
ua1 : if CFG_UART1_ENABLE /= 0 generate
|
449 |
|
|
uart1 : apbuart -- UART 1
|
450 |
|
|
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
|
451 |
|
|
fifosize => CFG_UART1_FIFO)
|
452 |
|
|
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
|
453 |
|
|
u1i.ctsn <= '0'; u1i.extclk <= '0';
|
454 |
|
|
upads : if CFG_AHB_UART = 0 generate
|
455 |
|
|
u1i.rxd <= rxd1; txd1 <= u1o.txd;
|
456 |
|
|
end generate;
|
457 |
|
|
end generate;
|
458 |
|
|
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
|
459 |
|
|
|
460 |
|
|
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
|
461 |
|
|
irqctrl0 : irqmp -- interrupt controller
|
462 |
|
|
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
|
463 |
|
|
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
|
464 |
|
|
end generate;
|
465 |
|
|
irq3 : if CFG_IRQ3_ENABLE = 0 generate
|
466 |
|
|
x : for i in 0 to NCPU-1 generate
|
467 |
|
|
irqi(i).irl <= "0000";
|
468 |
|
|
end generate;
|
469 |
|
|
apbo(2) <= apb_none;
|
470 |
|
|
end generate;
|
471 |
|
|
|
472 |
|
|
gpt : if CFG_GPT_ENABLE /= 0 generate
|
473 |
|
|
timer0 : gptimer -- timer unit
|
474 |
|
|
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
|
475 |
|
|
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
|
476 |
|
|
nbits => CFG_GPT_TW)
|
477 |
|
|
port map (rstn, clkm, apbi, apbo(3), gpti, open);
|
478 |
|
|
gpti.dhalt <= dsuo.active; gpti.extclk <= '0';
|
479 |
|
|
end generate;
|
480 |
|
|
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
481 |
|
|
|
482 |
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
|
483 |
|
|
grgpio0: grgpio
|
484 |
|
|
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
|
485 |
|
|
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
|
486 |
|
|
gpioi => gpioi, gpioo => gpioo);
|
487 |
|
|
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
|
488 |
|
|
pio_pad : iopad generic map (tech => padtech)
|
489 |
|
|
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
|
490 |
|
|
end generate;
|
491 |
|
|
end generate;
|
492 |
|
|
|
493 |
|
|
|
494 |
|
|
-----------------------------------------------------------------------
|
495 |
|
|
--- ATA Controller ---------------------------------------------------
|
496 |
|
|
-----------------------------------------------------------------------
|
497 |
|
|
|
498 |
|
|
atac : if CFG_ATA = 1 generate
|
499 |
|
|
atac0 : atactrl generic map(tech => 0, fdepth => CFG_ATAFIFO,
|
500 |
|
|
mhindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
|
501 |
|
|
shindex => 5, haddr => CFG_ATAIO, hmask => 16#fff#, pirq => CFG_ATAIRQ,
|
502 |
|
|
mwdma => CFG_ATADMA, TWIDTH => 8, -- counter width
|
503 |
|
|
-- PIO mode 0 settings (@100MHz clock)
|
504 |
|
|
PIO_mode0_T1 => 6, -- 70ns
|
505 |
|
|
PIO_mode0_T2 => 28, -- 290ns
|
506 |
|
|
PIO_mode0_T4 => 2, -- 30ns
|
507 |
|
|
PIO_mode0_Teoc => 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
|
508 |
|
|
)
|
509 |
|
|
port map( rst => rstn, arst => vcc(0), clk => clkm, ahbsi => ahbsi,
|
510 |
|
|
ahbso => ahbso(5), ahbmi => ahbmi, ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
|
511 |
|
|
cfo => cf, atai => atai, atao => atao);
|
512 |
|
|
|
513 |
|
|
ata_data_pad : iopadv generic map (tech => padtech, width => 16, oepol => 1)
|
514 |
|
|
port map (ata_data, atao.ddo, atao.oen, atai.ddi);
|
515 |
|
|
ata_da_pad : outpadv generic map (tech => padtech, width => 3)
|
516 |
|
|
port map (ata_da, atao.da);
|
517 |
|
|
ata_cs0_pad : outpad generic map (tech => padtech)
|
518 |
|
|
port map (ata_cs0, atao.cs0);
|
519 |
|
|
ata_cs1_pad : outpad generic map (tech => padtech)
|
520 |
|
|
port map (ata_cs1, atao.cs1);
|
521 |
|
|
ata_dior_pad : outpad generic map (tech => padtech)
|
522 |
|
|
port map (ata_dior, atao.dior);
|
523 |
|
|
ata_diow_pad : outpad generic map (tech => padtech)
|
524 |
|
|
port map (ata_diow, atao.diow);
|
525 |
|
|
iordy_pad : inpad generic map (tech => padtech)
|
526 |
|
|
port map (ata_iordy, atai.iordy);
|
527 |
|
|
intrq_pad : inpad generic map (tech => padtech)
|
528 |
|
|
port map (ata_intrq, atai.intrq);
|
529 |
|
|
dmarq_pad : inpad generic map (tech => padtech)
|
530 |
|
|
port map (ata_dmarq, atai.dmarq);
|
531 |
|
|
dmack_pad : outpad generic map (tech => padtech)
|
532 |
|
|
port map (ata_dmack, atao.dmack);
|
533 |
|
|
|
534 |
|
|
-- for CompactFlach mode selection
|
535 |
|
|
cf_gnd_da_pad : outpadv generic map (tech => padtech, width => 8)
|
536 |
|
|
port map (cf_gnd_da, cf.da);
|
537 |
|
|
cf_atasel_pad : outpad generic map (tech => padtech)
|
538 |
|
|
port map (cf_atasel, cf.atasel);
|
539 |
|
|
cf_we_pad : outpad generic map (tech => padtech)
|
540 |
|
|
port map (cf_we, cf.we);
|
541 |
|
|
cf_power_pad : outpad generic map (tech => padtech)
|
542 |
|
|
port map (cf_power, cf.power);
|
543 |
|
|
-- cf_csel_pad : outpad generic map (tech => padtech)
|
544 |
|
|
-- port map (cf_csel, cf.csel);
|
545 |
|
|
|
546 |
|
|
end generate;
|
547 |
|
|
|
548 |
|
|
-----------------------------------------------------------------------
|
549 |
|
|
--- AHB ROM ----------------------------------------------------------
|
550 |
|
|
-----------------------------------------------------------------------
|
551 |
|
|
|
552 |
|
|
bpromgen : if CFG_AHBROMEN /= 0 generate
|
553 |
|
|
brom : entity work.ahbrom
|
554 |
|
|
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
|
555 |
|
|
port map ( rstn, clkm, ahbsi, ahbso(6));
|
556 |
|
|
end generate;
|
557 |
|
|
nobpromgen : if CFG_AHBROMEN = 0 generate
|
558 |
|
|
ahbso(6) <= ahbs_none;
|
559 |
|
|
end generate;
|
560 |
|
|
|
561 |
|
|
-----------------------------------------------------------------------
|
562 |
|
|
--- AHB RAM ----------------------------------------------------------
|
563 |
|
|
-----------------------------------------------------------------------
|
564 |
|
|
|
565 |
|
|
ahbramgen : if CFG_AHBRAMEN = 1 generate
|
566 |
|
|
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
|
567 |
|
|
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
|
568 |
|
|
port map (rstn, clkm, ahbsi, ahbso(7));
|
569 |
|
|
end generate;
|
570 |
|
|
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
|
571 |
|
|
|
572 |
|
|
-----------------------------------------------------------------------
|
573 |
|
|
--- Drive unused bus elements ---------------------------------------
|
574 |
|
|
-----------------------------------------------------------------------
|
575 |
|
|
|
576 |
|
|
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_ATA) to NAHBMST-1 generate
|
577 |
|
|
ahbmo(i) <= ahbm_none;
|
578 |
|
|
end generate;
|
579 |
|
|
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
|
580 |
|
|
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
|
581 |
|
|
|
582 |
|
|
-- invert signal for input via a key
|
583 |
|
|
dsubre <= not dsubren;
|
584 |
|
|
|
585 |
|
|
-- for smc lan chip
|
586 |
|
|
eth_lclk <= vcc(0);
|
587 |
|
|
eth_nads <= gnd(0);
|
588 |
|
|
eth_ncycle <= vcc(0);
|
589 |
|
|
eth_wnr <= vcc(0);
|
590 |
|
|
eth_nvlbus <= vcc(0);
|
591 |
|
|
eth_nrdyrtn <= vcc(0);
|
592 |
|
|
eth_ndatacs <= vcc(0);
|
593 |
|
|
|
594 |
|
|
-----------------------------------------------------------------------
|
595 |
|
|
--- Boot message ----------------------------------------------------
|
596 |
|
|
-----------------------------------------------------------------------
|
597 |
|
|
|
598 |
|
|
-- pragma translate_off
|
599 |
|
|
x : report_version
|
600 |
|
|
generic map (
|
601 |
|
|
msg1 => "LEON3 Altera EP2C60 SSRAM/DDR Demonstration design",
|
602 |
|
|
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
|
603 |
|
|
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
|
604 |
|
|
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
|
605 |
|
|
mdel => 1
|
606 |
|
|
);
|
607 |
|
|
-- pragma translate_on
|
608 |
|
|
|
609 |
|
|
end;
|