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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-altera-ep2s60-ddr/] [tkconfig.h] - Blame information for rev 2

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#if defined CONFIG_SYN_INFERRED
#define CONFIG_SYN_TECH inferred
#elif defined CONFIG_SYN_UMC
#define CONFIG_SYN_TECH umc
#elif defined CONFIG_SYN_RHUMC
#define CONFIG_SYN_TECH rhumc
#elif defined CONFIG_SYN_ATC18
#define CONFIG_SYN_TECH atc18s
#elif defined CONFIG_SYN_ATC18RHA
#define CONFIG_SYN_TECH atc18rha
#elif defined CONFIG_SYN_AXCEL
#define CONFIG_SYN_TECH axcel
#elif defined CONFIG_SYN_PROASICPLUS
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_ALTERA
#define CONFIG_SYN_TECH altera
#elif defined CONFIG_SYN_STRATIX
#define CONFIG_SYN_TECH stratix1
#elif defined CONFIG_SYN_STRATIXII
#define CONFIG_SYN_TECH stratix2
#elif defined CONFIG_SYN_STRATIXIII
#define CONFIG_SYN_TECH stratix3
#elif defined CONFIG_SYN_CYCLONEIII
#define CONFIG_SYN_TECH cyclone3
#elif defined CONFIG_SYN_EASIC90
#define CONFIG_SYN_TECH easic90
#elif defined CONFIG_SYN_IHP25
#define CONFIG_SYN_TECH ihp25
#elif defined CONFIG_SYN_IHP25RH
#define CONFIG_SYN_TECH ihp25rh
#elif defined CONFIG_SYN_LATTICE
#define CONFIG_SYN_TECH lattice
#elif defined CONFIG_SYN_ECLIPSE
#define CONFIG_SYN_TECH eclipse
#elif defined CONFIG_SYN_PEREGRINE
#define CONFIG_SYN_TECH peregrine
#elif defined CONFIG_SYN_PROASIC
#define CONFIG_SYN_TECH proasic
#elif defined CONFIG_SYN_PROASIC3
#define CONFIG_SYN_TECH apa3
#elif defined CONFIG_SYN_SPARTAN2
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEX
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_VIRTEXE
#define CONFIG_SYN_TECH virtex
#elif defined CONFIG_SYN_SPARTAN3
#define CONFIG_SYN_TECH spartan3
#elif defined CONFIG_SYN_SPARTAN3E
#define CONFIG_SYN_TECH spartan3e
#elif defined CONFIG_SYN_VIRTEX2
#define CONFIG_SYN_TECH virtex2
#elif defined CONFIG_SYN_VIRTEX4
#define CONFIG_SYN_TECH virtex4
#elif defined CONFIG_SYN_VIRTEX5
#define CONFIG_SYN_TECH virtex5
#elif defined CONFIG_SYN_RH_LIB18T
#define CONFIG_SYN_TECH rhlib18t
#elif defined CONFIG_SYN_UT025CRH
#define CONFIG_SYN_TECH ut25
#elif defined CONFIG_SYN_TSMC90
#define CONFIG_SYN_TECH tsmc90
#elif defined CONFIG_SYN_CUSTOM1
#define CONFIG_SYN_TECH custom1
#else
#error "unknown target technology"
#endif
 
#if defined CONFIG_SYN_INFER_RAM
#define CFG_RAM_TECH inferred
#elif defined CONFIG_MEM_UMC
#define CFG_RAM_TECH umc
#elif defined CONFIG_MEM_RHUMC
#define CFG_RAM_TECH rhumc
#elif defined CONFIG_MEM_VIRAGE
#define CFG_RAM_TECH memvirage
#elif defined CONFIG_MEM_ARTISAN
#define CFG_RAM_TECH memartisan
#elif defined CONFIG_MEM_CUSTOM1
#define CFG_RAM_TECH custom1
#elif defined CONFIG_MEM_VIRAGE90
#define CFG_RAM_TECH memvirage90
#elif defined CONFIG_MEM_INFERRED
#define CFG_RAM_TECH inferred
#else
#define CFG_RAM_TECH CONFIG_SYN_TECH
#endif
 
#if defined CONFIG_SYN_INFER_PADS
#define CFG_PAD_TECH inferred
#else
#define CFG_PAD_TECH CONFIG_SYN_TECH
#endif
 
#ifndef CONFIG_SYN_NO_ASYNC
#define CONFIG_SYN_NO_ASYNC 0
#endif
 
#ifndef CONFIG_SYN_SCAN
#define CONFIG_SYN_SCAN 0
#endif
 
 
#if defined CONFIG_CLK_ALTDLL
#define CFG_CLK_TECH CONFIG_SYN_TECH
#elif defined CONFIG_CLK_HCLKBUF
#define CFG_CLK_TECH axcel
#elif defined CONFIG_CLK_LATDLL
#define CFG_CLK_TECH lattice
#elif defined CONFIG_CLK_PRO3PLL
#define CFG_CLK_TECH apa3
#elif defined CONFIG_CLK_CLKDLL
#define CFG_CLK_TECH virtex
#elif defined CONFIG_CLK_DCM
#define CFG_CLK_TECH CONFIG_SYN_TECH
#elif defined CONFIG_CLK_LIB18T
#define CFG_CLK_TECH rhlib18t
#elif defined CONFIG_CLK_RHUMC
#define CFG_CLK_TECH rhumc
#else
#define CFG_CLK_TECH inferred
#endif
 
#ifndef CONFIG_CLK_MUL
#define CONFIG_CLK_MUL 2
#endif
 
#ifndef CONFIG_CLK_DIV
#define CONFIG_CLK_DIV 2
#endif
 
#ifndef CONFIG_OCLK_DIV
#define CONFIG_OCLK_DIV 2
#endif
 
#ifndef CONFIG_PCI_CLKDLL
#define CONFIG_PCI_CLKDLL 0
#endif
 
#ifndef CONFIG_PCI_SYSCLK
#define CONFIG_PCI_SYSCLK 0
#endif
 
#ifndef CONFIG_CLK_NOFB
#define CONFIG_CLK_NOFB 0
#endif
#ifndef CONFIG_LEON3
#define CONFIG_LEON3 0
#endif
 
#ifndef CONFIG_PROC_NUM
#define CONFIG_PROC_NUM 1
#endif
 
#ifndef CONFIG_IU_NWINDOWS
#define CONFIG_IU_NWINDOWS 8
#endif
 
#ifndef CONFIG_IU_RSTADDR
#define CONFIG_IU_RSTADDR 8
#endif
 
#ifndef CONFIG_IU_LDELAY
#define CONFIG_IU_LDELAY 1
#endif
 
#ifndef CONFIG_IU_WATCHPOINTS
#define CONFIG_IU_WATCHPOINTS 0
#endif
 
#ifdef CONFIG_IU_V8MULDIV
#ifdef CONFIG_IU_MUL_LATENCY_4
#define CFG_IU_V8 1
#elif defined CONFIG_IU_MUL_LATENCY_5
#define CFG_IU_V8 2
#elif defined CONFIG_IU_MUL_LATENCY_2
#define CFG_IU_V8 16#32#
#endif
#else
#define CFG_IU_V8 0
#endif
 
#ifndef CONFIG_PWD
#define CONFIG_PWD 0
#endif
 
#ifndef CONFIG_IU_MUL_MAC
#define CONFIG_IU_MUL_MAC 0
#endif
 
#ifndef CONFIG_IU_SVT
#define CONFIG_IU_SVT 0
#endif
 
#if defined CONFIG_FPU_GRFPC1
#define CONFIG_FPU_GRFPC 1
#elif defined CONFIG_FPU_GRFPC2
#define CONFIG_FPU_GRFPC 2
#else
#define CONFIG_FPU_GRFPC 0
#endif
 
#if defined CONFIG_FPU_GRFPU_INFMUL
#define CONFIG_FPU_GRFPU_MUL 0
#elif defined CONFIG_FPU_GRFPU_DWMUL
#define CONFIG_FPU_GRFPU_MUL 1
#elif defined CONFIG_FPU_GRFPU_MODGEN 
#define CONFIG_FPU_GRFPU_MUL 2
#else
#define CONFIG_FPU_GRFPU_MUL 0
#endif
 
#if defined CONFIG_FPU_GRFPU_SH
#define CONFIG_FPU_GRFPU_SHARED 1
#else
#define CONFIG_FPU_GRFPU_SHARED 0
#endif
 
#if defined CONFIG_FPU_GRFPU
#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)
#elif defined CONFIG_FPU_MEIKO
#define CONFIG_FPU 15
#elif defined CONFIG_FPU_GRFPULITE
#define CONFIG_FPU (8+CONFIG_FPU_GRFPC)
#else
#define CONFIG_FPU 0
#endif
 
#ifndef CONFIG_FPU_NETLIST
#define CONFIG_FPU_NETLIST 0
#endif
 
#ifndef CONFIG_ICACHE_ENABLE
#define CONFIG_ICACHE_ENABLE 0
#endif
 
#if defined CONFIG_ICACHE_ASSO1
#define CFG_IU_ISETS 1
#elif defined CONFIG_ICACHE_ASSO2
#define CFG_IU_ISETS 2
#elif defined CONFIG_ICACHE_ASSO3
#define CFG_IU_ISETS 3
#elif defined CONFIG_ICACHE_ASSO4
#define CFG_IU_ISETS 4
#else
#define CFG_IU_ISETS 1
#endif
 
#if defined CONFIG_ICACHE_SZ1
#define CFG_ICACHE_SZ 1
#elif defined CONFIG_ICACHE_SZ2
#define CFG_ICACHE_SZ 2
#elif defined CONFIG_ICACHE_SZ4
#define CFG_ICACHE_SZ 4
#elif defined CONFIG_ICACHE_SZ8
#define CFG_ICACHE_SZ 8
#elif defined CONFIG_ICACHE_SZ16
#define CFG_ICACHE_SZ 16
#elif defined CONFIG_ICACHE_SZ32
#define CFG_ICACHE_SZ 32
#elif defined CONFIG_ICACHE_SZ64
#define CFG_ICACHE_SZ 64
#elif defined CONFIG_ICACHE_SZ128
#define CFG_ICACHE_SZ 128
#elif defined CONFIG_ICACHE_SZ256
#define CFG_ICACHE_SZ 256
#else
#define CFG_ICACHE_SZ 1
#endif
 
#ifdef CONFIG_ICACHE_LZ16
#define CFG_ILINE_SZ 4
#else
#define CFG_ILINE_SZ 8
#endif
 
#if defined CONFIG_ICACHE_ALGORND
#define CFG_ICACHE_ALGORND 2
#elif defined CONFIG_ICACHE_ALGOLRR
#define CFG_ICACHE_ALGORND 1
#else
#define CFG_ICACHE_ALGORND 0
#endif
 
#ifndef CONFIG_ICACHE_LOCK
#define CONFIG_ICACHE_LOCK 0
#endif
 
#ifndef CONFIG_ICACHE_LRAM
#define CONFIG_ICACHE_LRAM 0
#endif
 
#ifndef CONFIG_ICACHE_LRSTART
#define CONFIG_ICACHE_LRSTART 8E
#endif
 
#if defined CONFIG_ICACHE_LRAM_SZ2
#define CFG_ILRAM_SIZE 2
#elif defined CONFIG_ICACHE_LRAM_SZ4
#define CFG_ILRAM_SIZE 4
#elif defined CONFIG_ICACHE_LRAM_SZ8
#define CFG_ILRAM_SIZE 8
#elif defined CONFIG_ICACHE_LRAM_SZ16
#define CFG_ILRAM_SIZE 16
#elif defined CONFIG_ICACHE_LRAM_SZ32
#define CFG_ILRAM_SIZE 32
#elif defined CONFIG_ICACHE_LRAM_SZ64
#define CFG_ILRAM_SIZE 64
#elif defined CONFIG_ICACHE_LRAM_SZ128
#define CFG_ILRAM_SIZE 128
#elif defined CONFIG_ICACHE_LRAM_SZ256
#define CFG_ILRAM_SIZE 256
#else
#define CFG_ILRAM_SIZE 1
#endif
 
 
#ifndef CONFIG_DCACHE_ENABLE
#define CONFIG_DCACHE_ENABLE 0
#endif
 
#if defined CONFIG_DCACHE_ASSO1
#define CFG_IU_DSETS 1
#elif defined CONFIG_DCACHE_ASSO2
#define CFG_IU_DSETS 2
#elif defined CONFIG_DCACHE_ASSO3
#define CFG_IU_DSETS 3
#elif defined CONFIG_DCACHE_ASSO4
#define CFG_IU_DSETS 4
#else
#define CFG_IU_DSETS 1
#endif
 
#if defined CONFIG_DCACHE_SZ1
#define CFG_DCACHE_SZ 1
#elif defined CONFIG_DCACHE_SZ2
#define CFG_DCACHE_SZ 2
#elif defined CONFIG_DCACHE_SZ4
#define CFG_DCACHE_SZ 4
#elif defined CONFIG_DCACHE_SZ8
#define CFG_DCACHE_SZ 8
#elif defined CONFIG_DCACHE_SZ16
#define CFG_DCACHE_SZ 16
#elif defined CONFIG_DCACHE_SZ32
#define CFG_DCACHE_SZ 32
#elif defined CONFIG_DCACHE_SZ64
#define CFG_DCACHE_SZ 64
#elif defined CONFIG_DCACHE_SZ128
#define CFG_DCACHE_SZ 128
#elif defined CONFIG_DCACHE_SZ256
#define CFG_DCACHE_SZ 256
#else
#define CFG_DCACHE_SZ 1
#endif
 
#ifdef CONFIG_DCACHE_LZ16
#define CFG_DLINE_SZ 4
#else
#define CFG_DLINE_SZ 8
#endif
 
#if defined CONFIG_DCACHE_ALGORND
#define CFG_DCACHE_ALGORND 2
#elif defined CONFIG_DCACHE_ALGOLRR
#define CFG_DCACHE_ALGORND 1
#else
#define CFG_DCACHE_ALGORND 0
#endif
 
#ifndef CONFIG_DCACHE_LOCK
#define CONFIG_DCACHE_LOCK 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP
#define CONFIG_DCACHE_SNOOP 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP_FAST
#define CONFIG_DCACHE_SNOOP_FAST 0
#endif
 
#ifndef CONFIG_DCACHE_SNOOP_SEPTAG
#define CONFIG_DCACHE_SNOOP_SEPTAG 0
#endif
 
#ifndef CONFIG_CACHE_FIXED
#define CONFIG_CACHE_FIXED 0
#endif
 
#ifndef CONFIG_DCACHE_LRAM
#define CONFIG_DCACHE_LRAM 0
#endif
 
#ifndef CONFIG_DCACHE_LRSTART
#define CONFIG_DCACHE_LRSTART 8F
#endif
 
#if defined CONFIG_DCACHE_LRAM_SZ2
#define CFG_DLRAM_SIZE 2
#elif defined CONFIG_DCACHE_LRAM_SZ4
#define CFG_DLRAM_SIZE 4
#elif defined CONFIG_DCACHE_LRAM_SZ8
#define CFG_DLRAM_SIZE 8
#elif defined CONFIG_DCACHE_LRAM_SZ16
#define CFG_DLRAM_SIZE 16
#elif defined CONFIG_DCACHE_LRAM_SZ32
#define CFG_DLRAM_SIZE 32
#elif defined CONFIG_DCACHE_LRAM_SZ64
#define CFG_DLRAM_SIZE 64
#elif defined CONFIG_DCACHE_LRAM_SZ128
#define CFG_DLRAM_SIZE 128
#elif defined CONFIG_DCACHE_LRAM_SZ256
#define CFG_DLRAM_SIZE 256
#else
#define CFG_DLRAM_SIZE 1
#endif
 
 
#ifdef CONFIG_MMU_ENABLE
#define CONFIG_MMUEN 1
 
#ifdef CONFIG_MMU_SPLIT
#define CONFIG_TLB_TYPE 0
#endif
#ifdef CONFIG_MMU_COMBINED
#define CONFIG_TLB_TYPE 1
#endif
 
#ifdef CONFIG_MMU_REPARRAY
#define CONFIG_TLB_REP 0
#endif
#ifdef CONFIG_MMU_REPINCREMENT
#define CONFIG_TLB_REP 1
#endif
 
#ifdef CONFIG_MMU_I2 
#define CONFIG_ITLBNUM 2
#endif
#ifdef CONFIG_MMU_I4 
#define CONFIG_ITLBNUM 4
#endif
#ifdef CONFIG_MMU_I8 
#define CONFIG_ITLBNUM 8
#endif
#ifdef CONFIG_MMU_I16 
#define CONFIG_ITLBNUM 16
#endif
#ifdef CONFIG_MMU_I32
#define CONFIG_ITLBNUM 32
#endif
 
#define CONFIG_DTLBNUM 2
#ifdef CONFIG_MMU_D2 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 2
#endif
#ifdef CONFIG_MMU_D4 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 4
#endif
#ifdef CONFIG_MMU_D8 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 8
#endif
#ifdef CONFIG_MMU_D16 
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 16
#endif
#ifdef CONFIG_MMU_D32
#undef CONFIG_DTLBNUM 
#define CONFIG_DTLBNUM 32
#endif
#ifdef CONFIG_MMU_FASTWB
#define CFG_MMU_FASTWB 1
#else
#define CFG_MMU_FASTWB 0
#endif
 
#else
#define CONFIG_MMUEN 0
#define CONFIG_ITLBNUM 2
#define CONFIG_DTLBNUM 2
#define CONFIG_TLB_TYPE 1
#define CONFIG_TLB_REP 1
#define CFG_MMU_FASTWB 0
#endif
 
#ifndef CONFIG_DSU_ENABLE
#define CONFIG_DSU_ENABLE 0
#endif
 
#if defined CONFIG_DSU_ITRACESZ1
#define CFG_DSU_ITB 1
#elif CONFIG_DSU_ITRACESZ2
#define CFG_DSU_ITB 2
#elif CONFIG_DSU_ITRACESZ4
#define CFG_DSU_ITB 4
#elif CONFIG_DSU_ITRACESZ8
#define CFG_DSU_ITB 8
#elif CONFIG_DSU_ITRACESZ16
#define CFG_DSU_ITB 16
#else
#define CFG_DSU_ITB 0
#endif
 
#if defined CONFIG_DSU_ATRACESZ1
#define CFG_DSU_ATB 1
#elif CONFIG_DSU_ATRACESZ2
#define CFG_DSU_ATB 2
#elif CONFIG_DSU_ATRACESZ4
#define CFG_DSU_ATB 4
#elif CONFIG_DSU_ATRACESZ8
#define CFG_DSU_ATB 8
#elif CONFIG_DSU_ATRACESZ16
#define CFG_DSU_ATB 16
#else
#define CFG_DSU_ATB 0
#endif
 
#ifndef CONFIG_LEON3FT_EN
#define CONFIG_LEON3FT_EN 0
#endif
 
#if defined CONFIG_IUFT_PAR
#define CONFIG_IUFT_EN 1
#elif defined CONFIG_IUFT_DMR
#define CONFIG_IUFT_EN 2
#elif defined CONFIG_IUFT_BCH
#define CONFIG_IUFT_EN 3
#elif defined CONFIG_IUFT_TMR
#define CONFIG_IUFT_EN 4
#else
#define CONFIG_IUFT_EN 0
#endif
#ifndef CONFIG_RF_ERRINJ
#define CONFIG_RF_ERRINJ 0
#endif
 
#ifndef CONFIG_FPUFT_EN
#define CONFIG_FPUFT 0
#else
#ifdef CONFIG_FPU_GRFPU
#define CONFIG_FPUFT 2
#else
#define CONFIG_FPUFT 1
#endif
#endif
 
#ifndef CONFIG_CACHE_FT_EN
#define CONFIG_CACHE_FT_EN 0
#endif
#ifndef CONFIG_CACHE_ERRINJ
#define CONFIG_CACHE_ERRINJ 0
#endif
 
#ifndef CONFIG_LEON3_NETLIST
#define CONFIG_LEON3_NETLIST 0
#endif
 
#ifdef CONFIG_DEBUG_PC32
#define CFG_DEBUG_PC32 0 
#else
#define CFG_DEBUG_PC32 2
#endif
#ifndef CONFIG_IU_DISAS
#define CONFIG_IU_DISAS 0
#endif
#ifndef CONFIG_IU_DISAS_NET
#define CONFIG_IU_DISAS_NET 0
#endif
 
 
#ifndef CONFIG_AHB_SPLIT
#define CONFIG_AHB_SPLIT 0
#endif
 
#ifndef CONFIG_AHB_RROBIN
#define CONFIG_AHB_RROBIN 0
#endif
 
#ifndef CONFIG_AHB_IOADDR
#define CONFIG_AHB_IOADDR FFF
#endif
 
#ifndef CONFIG_APB_HADDR
#define CONFIG_APB_HADDR 800
#endif
 
#ifndef CONFIG_AHB_MON
#define CONFIG_AHB_MON 0
#endif
 
#ifndef CONFIG_AHB_MONERR
#define CONFIG_AHB_MONERR 0
#endif
 
#ifndef CONFIG_AHB_MONWAR
#define CONFIG_AHB_MONWAR 0
#endif
 
#ifndef CONFIG_DSU_UART
#define CONFIG_DSU_UART 0
#endif
 
 
#ifndef CONFIG_DSU_JTAG
#define CONFIG_DSU_JTAG 0
#endif
 
#ifndef CONFIG_MCTRL_LEON2
#define CONFIG_MCTRL_LEON2 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM
#define CONFIG_MCTRL_SDRAM 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_SEPBUS
#define CONFIG_MCTRL_SDRAM_SEPBUS 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_INVCLK
#define CONFIG_MCTRL_SDRAM_INVCLK 0
#endif
 
#ifndef CONFIG_MCTRL_SDRAM_BUS64
#define CONFIG_MCTRL_SDRAM_BUS64 0
#endif
 
#ifndef CONFIG_MCTRL_8BIT
#define CONFIG_MCTRL_8BIT 0
#endif
 
#ifndef CONFIG_MCTRL_16BIT
#define CONFIG_MCTRL_16BIT 0
#endif
 
#ifndef CONFIG_MCTRL_5CS
#define CONFIG_MCTRL_5CS 0
#endif
 
#ifndef CONFIG_MCTRL_EDAC
#define CONFIG_MCTRL_EDAC 0
#endif
 
#ifndef CONFIG_MCTRL_PAGE
#define CONFIG_MCTRL_PAGE 0
#endif
 
#ifndef CONFIG_MCTRL_PROGPAGE
#define CONFIG_MCTRL_PROGPAGE 0
#endif
 
#ifndef CONFIG_DDRSP
#define CONFIG_DDRSP 0
#endif
 
#ifndef CONFIG_DDRSP_INIT
#define CONFIG_DDRSP_INIT 0
#endif
 
#ifndef CONFIG_DDRSP_FREQ
#define CONFIG_DDRSP_FREQ 100
#endif
 
#ifndef CONFIG_DDRSP_COL
#define CONFIG_DDRSP_COL 9
#endif
 
#ifndef CONFIG_DDRSP_MBYTE
#define CONFIG_DDRSP_MBYTE 8
#endif
 
#ifndef CONFIG_DDRSP_RSKEW
#define CONFIG_DDRSP_RSKEW 0
#endif
#ifndef CONFIG_AHBROM_ENABLE
#define CONFIG_AHBROM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBROM_START
#define CONFIG_AHBROM_START 000
#endif
 
#ifndef CONFIG_AHBROM_PIPE
#define CONFIG_AHBROM_PIPE 0
#endif
 
#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)
#define CONFIG_ROM_START 100
#else
#define CONFIG_ROM_START 000
#endif
 
 
#ifndef CONFIG_AHBRAM_ENABLE
#define CONFIG_AHBRAM_ENABLE 0
#endif
 
#ifndef CONFIG_AHBRAM_START
#define CONFIG_AHBRAM_START A00
#endif
 
#if defined CONFIG_AHBRAM_SZ1
#define CFG_AHBRAMSZ 1
#elif CONFIG_AHBRAM_SZ2
#define CFG_AHBRAMSZ 2
#elif CONFIG_AHBRAM_SZ4
#define CFG_AHBRAMSZ 4
#elif CONFIG_AHBRAM_SZ8
#define CFG_AHBRAMSZ 8
#elif CONFIG_AHBRAM_SZ16
#define CFG_AHBRAMSZ 16
#elif CONFIG_AHBRAM_SZ32
#define CFG_AHBRAMSZ 32
#elif CONFIG_AHBRAM_SZ64
#define CFG_AHBRAMSZ 64
#else
#define CFG_AHBRAMSZ 1
#endif
 
#ifndef CONFIG_UART1_ENABLE
#define CONFIG_UART1_ENABLE 0
#endif
 
#if defined CONFIG_UA1_FIFO1
#define CFG_UA1_FIFO 1
#elif defined CONFIG_UA1_FIFO2
#define CFG_UA1_FIFO 2
#elif defined CONFIG_UA1_FIFO4
#define CFG_UA1_FIFO 4
#elif defined CONFIG_UA1_FIFO8
#define CFG_UA1_FIFO 8
#elif defined CONFIG_UA1_FIFO16
#define CFG_UA1_FIFO 16
#elif defined CONFIG_UA1_FIFO32
#define CFG_UA1_FIFO 32
#else
#define CFG_UA1_FIFO 1
#endif
 
#ifndef CONFIG_IRQ3_ENABLE
#define CONFIG_IRQ3_ENABLE 0
#endif
#ifndef CONFIG_IRQ3_NSEC
#define CONFIG_IRQ3_NSEC 0
#endif
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif
 
#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif
 
#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif
 
#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif
 
#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
#ifndef CONFIG_GPT_ENABLE
#define CONFIG_GPT_ENABLE 0
#endif
 
#ifndef CONFIG_GPT_NTIM
#define CONFIG_GPT_NTIM 1
#endif
 
#ifndef CONFIG_GPT_SW
#define CONFIG_GPT_SW 8
#endif
 
#ifndef CONFIG_GPT_TW
#define CONFIG_GPT_TW 8
#endif
 
#ifndef CONFIG_GPT_IRQ
#define CONFIG_GPT_IRQ 8
#endif
 
#ifndef CONFIG_GPT_SEPIRQ
#define CONFIG_GPT_SEPIRQ 0
#endif
 
#ifndef CONFIG_GPT_WDOGEN
#define CONFIG_GPT_WDOGEN 0
#endif
 
#ifndef CONFIG_GPT_WDOG
#define CONFIG_GPT_WDOG 0
#endif
 
#ifndef CONFIG_GRGPIO_ENABLE
#define CONFIG_GRGPIO_ENABLE 0
#endif
#ifndef CONFIG_GRGPIO_IMASK
#define CONFIG_GRGPIO_IMASK 0000
#endif
#ifndef CONFIG_GRGPIO_WIDTH
#define CONFIG_GRGPIO_WIDTH 1
#endif
 
#ifndef CONFIG_ATA_ENABLE
#define CONFIG_ATA_ENABLE 0
#endif
 
#ifndef CONFIG_ATAIO
#define CONFIG_ATAIO 0
#endif
 
#ifndef CONFIG_ATAIRQ
#define CONFIG_ATAIRQ 0
#endif
 
#ifndef CONFIG_ATA_MWDMA
#define CONFIG_ATA_MWDMA 0
#endif
 
#ifndef CONFIG_ATA_FIFO
#define CONFIG_ATA_FIFO 8
#endif
 
#ifndef CONFIG_DEBUG_UART
#define CONFIG_DEBUG_UART 0
#endif

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-altera-ep2s60-ddr/] [tkconfig.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dimamali	`#if defined CONFIG_SYN_INFERRED`
2			`#define CONFIG_SYN_TECH inferred`
3			`#elif defined CONFIG_SYN_UMC`
4			`#define CONFIG_SYN_TECH umc`
5			`#elif defined CONFIG_SYN_RHUMC`
6			`#define CONFIG_SYN_TECH rhumc`
7			`#elif defined CONFIG_SYN_ATC18`
8			`#define CONFIG_SYN_TECH atc18s`
9			`#elif defined CONFIG_SYN_ATC18RHA`
10			`#define CONFIG_SYN_TECH atc18rha`
11			`#elif defined CONFIG_SYN_AXCEL`
12			`#define CONFIG_SYN_TECH axcel`
13			`#elif defined CONFIG_SYN_PROASICPLUS`
14			`#define CONFIG_SYN_TECH proasic`
15			`#elif defined CONFIG_SYN_ALTERA`
16			`#define CONFIG_SYN_TECH altera`
17			`#elif defined CONFIG_SYN_STRATIX`
18			`#define CONFIG_SYN_TECH stratix1`
19			`#elif defined CONFIG_SYN_STRATIXII`
20			`#define CONFIG_SYN_TECH stratix2`
21			`#elif defined CONFIG_SYN_STRATIXIII`
22			`#define CONFIG_SYN_TECH stratix3`
23			`#elif defined CONFIG_SYN_CYCLONEIII`
24			`#define CONFIG_SYN_TECH cyclone3`
25			`#elif defined CONFIG_SYN_EASIC90`
26			`#define CONFIG_SYN_TECH easic90`
27			`#elif defined CONFIG_SYN_IHP25`
28			`#define CONFIG_SYN_TECH ihp25`
29			`#elif defined CONFIG_SYN_IHP25RH`
30			`#define CONFIG_SYN_TECH ihp25rh`
31			`#elif defined CONFIG_SYN_LATTICE`
32			`#define CONFIG_SYN_TECH lattice`
33			`#elif defined CONFIG_SYN_ECLIPSE`
34			`#define CONFIG_SYN_TECH eclipse`
35			`#elif defined CONFIG_SYN_PEREGRINE`
36			`#define CONFIG_SYN_TECH peregrine`
37			`#elif defined CONFIG_SYN_PROASIC`
38			`#define CONFIG_SYN_TECH proasic`
39			`#elif defined CONFIG_SYN_PROASIC3`
40			`#define CONFIG_SYN_TECH apa3`
41			`#elif defined CONFIG_SYN_SPARTAN2`
42			`#define CONFIG_SYN_TECH virtex`
43			`#elif defined CONFIG_SYN_VIRTEX`
44			`#define CONFIG_SYN_TECH virtex`
45			`#elif defined CONFIG_SYN_VIRTEXE`
46			`#define CONFIG_SYN_TECH virtex`
47			`#elif defined CONFIG_SYN_SPARTAN3`
48			`#define CONFIG_SYN_TECH spartan3`
49			`#elif defined CONFIG_SYN_SPARTAN3E`
50			`#define CONFIG_SYN_TECH spartan3e`
51			`#elif defined CONFIG_SYN_VIRTEX2`
52			`#define CONFIG_SYN_TECH virtex2`
53			`#elif defined CONFIG_SYN_VIRTEX4`
54			`#define CONFIG_SYN_TECH virtex4`
55			`#elif defined CONFIG_SYN_VIRTEX5`
56			`#define CONFIG_SYN_TECH virtex5`
57			`#elif defined CONFIG_SYN_RH_LIB18T`
58			`#define CONFIG_SYN_TECH rhlib18t`
59			`#elif defined CONFIG_SYN_UT025CRH`
60			`#define CONFIG_SYN_TECH ut25`
61			`#elif defined CONFIG_SYN_TSMC90`
62			`#define CONFIG_SYN_TECH tsmc90`
63			`#elif defined CONFIG_SYN_CUSTOM1`
64			`#define CONFIG_SYN_TECH custom1`
65			`#else`
66			`#error "unknown target technology"`
67			`#endif`
68
69			`#if defined CONFIG_SYN_INFER_RAM`
70			`#define CFG_RAM_TECH inferred`
71			`#elif defined CONFIG_MEM_UMC`
72			`#define CFG_RAM_TECH umc`
73			`#elif defined CONFIG_MEM_RHUMC`
74			`#define CFG_RAM_TECH rhumc`
75			`#elif defined CONFIG_MEM_VIRAGE`
76			`#define CFG_RAM_TECH memvirage`
77			`#elif defined CONFIG_MEM_ARTISAN`
78			`#define CFG_RAM_TECH memartisan`
79			`#elif defined CONFIG_MEM_CUSTOM1`
80			`#define CFG_RAM_TECH custom1`
81			`#elif defined CONFIG_MEM_VIRAGE90`
82			`#define CFG_RAM_TECH memvirage90`
83			`#elif defined CONFIG_MEM_INFERRED`
84			`#define CFG_RAM_TECH inferred`
85			`#else`
86			`#define CFG_RAM_TECH CONFIG_SYN_TECH`
87			`#endif`
88
89			`#if defined CONFIG_SYN_INFER_PADS`
90			`#define CFG_PAD_TECH inferred`
91			`#else`
92			`#define CFG_PAD_TECH CONFIG_SYN_TECH`
93			`#endif`
94
95			`#ifndef CONFIG_SYN_NO_ASYNC`
96			`#define CONFIG_SYN_NO_ASYNC 0`
97			`#endif`
98
99			`#ifndef CONFIG_SYN_SCAN`
100			`#define CONFIG_SYN_SCAN 0`
101			`#endif`
102
103
104			`#if defined CONFIG_CLK_ALTDLL`
105			`#define CFG_CLK_TECH CONFIG_SYN_TECH`
106			`#elif defined CONFIG_CLK_HCLKBUF`
107			`#define CFG_CLK_TECH axcel`
108			`#elif defined CONFIG_CLK_LATDLL`
109			`#define CFG_CLK_TECH lattice`
110			`#elif defined CONFIG_CLK_PRO3PLL`
111			`#define CFG_CLK_TECH apa3`
112			`#elif defined CONFIG_CLK_CLKDLL`
113			`#define CFG_CLK_TECH virtex`
114			`#elif defined CONFIG_CLK_DCM`
115			`#define CFG_CLK_TECH CONFIG_SYN_TECH`
116			`#elif defined CONFIG_CLK_LIB18T`
117			`#define CFG_CLK_TECH rhlib18t`
118			`#elif defined CONFIG_CLK_RHUMC`
119			`#define CFG_CLK_TECH rhumc`
120			`#else`
121			`#define CFG_CLK_TECH inferred`
122			`#endif`
123
124			`#ifndef CONFIG_CLK_MUL`
125			`#define CONFIG_CLK_MUL 2`
126			`#endif`
127
128			`#ifndef CONFIG_CLK_DIV`
129			`#define CONFIG_CLK_DIV 2`
130			`#endif`
131
132			`#ifndef CONFIG_OCLK_DIV`
133			`#define CONFIG_OCLK_DIV 2`
134			`#endif`
135
136			`#ifndef CONFIG_PCI_CLKDLL`
137			`#define CONFIG_PCI_CLKDLL 0`
138			`#endif`
139
140			`#ifndef CONFIG_PCI_SYSCLK`
141			`#define CONFIG_PCI_SYSCLK 0`
142			`#endif`
143
144			`#ifndef CONFIG_CLK_NOFB`
145			`#define CONFIG_CLK_NOFB 0`
146			`#endif`
147			`#ifndef CONFIG_LEON3`
148			`#define CONFIG_LEON3 0`
149			`#endif`
150
151			`#ifndef CONFIG_PROC_NUM`
152			`#define CONFIG_PROC_NUM 1`
153			`#endif`
154
155			`#ifndef CONFIG_IU_NWINDOWS`
156			`#define CONFIG_IU_NWINDOWS 8`
157			`#endif`
158
159			`#ifndef CONFIG_IU_RSTADDR`
160			`#define CONFIG_IU_RSTADDR 8`
161			`#endif`
162
163			`#ifndef CONFIG_IU_LDELAY`
164			`#define CONFIG_IU_LDELAY 1`
165			`#endif`
166
167			`#ifndef CONFIG_IU_WATCHPOINTS`
168			`#define CONFIG_IU_WATCHPOINTS 0`
169			`#endif`
170
171			`#ifdef CONFIG_IU_V8MULDIV`
172			`#ifdef CONFIG_IU_MUL_LATENCY_4`
173			`#define CFG_IU_V8 1`
174			`#elif defined CONFIG_IU_MUL_LATENCY_5`
175			`#define CFG_IU_V8 2`
176			`#elif defined CONFIG_IU_MUL_LATENCY_2`
177			`#define CFG_IU_V8 16#32#`
178			`#endif`
179			`#else`
180			`#define CFG_IU_V8 0`
181			`#endif`
182
183			`#ifndef CONFIG_PWD`
184			`#define CONFIG_PWD 0`
185			`#endif`
186
187			`#ifndef CONFIG_IU_MUL_MAC`
188			`#define CONFIG_IU_MUL_MAC 0`
189			`#endif`
190
191			`#ifndef CONFIG_IU_SVT`
192			`#define CONFIG_IU_SVT 0`
193			`#endif`
194
195			`#if defined CONFIG_FPU_GRFPC1`
196			`#define CONFIG_FPU_GRFPC 1`
197			`#elif defined CONFIG_FPU_GRFPC2`
198			`#define CONFIG_FPU_GRFPC 2`
199			`#else`
200			`#define CONFIG_FPU_GRFPC 0`
201			`#endif`
202
203			`#if defined CONFIG_FPU_GRFPU_INFMUL`
204			`#define CONFIG_FPU_GRFPU_MUL 0`
205			`#elif defined CONFIG_FPU_GRFPU_DWMUL`
206			`#define CONFIG_FPU_GRFPU_MUL 1`
207			`#elif defined CONFIG_FPU_GRFPU_MODGEN`
208			`#define CONFIG_FPU_GRFPU_MUL 2`
209			`#else`
210			`#define CONFIG_FPU_GRFPU_MUL 0`
211			`#endif`
212
213			`#if defined CONFIG_FPU_GRFPU_SH`
214			`#define CONFIG_FPU_GRFPU_SHARED 1`
215			`#else`
216			`#define CONFIG_FPU_GRFPU_SHARED 0`
217			`#endif`
218
219			`#if defined CONFIG_FPU_GRFPU`
220			`#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL)`
221			`#elif defined CONFIG_FPU_MEIKO`
222			`#define CONFIG_FPU 15`
223			`#elif defined CONFIG_FPU_GRFPULITE`
224			`#define CONFIG_FPU (8+CONFIG_FPU_GRFPC)`
225			`#else`
226			`#define CONFIG_FPU 0`
227			`#endif`
228
229			`#ifndef CONFIG_FPU_NETLIST`
230			`#define CONFIG_FPU_NETLIST 0`
231			`#endif`
232
233			`#ifndef CONFIG_ICACHE_ENABLE`
234			`#define CONFIG_ICACHE_ENABLE 0`
235			`#endif`
236
237			`#if defined CONFIG_ICACHE_ASSO1`
238			`#define CFG_IU_ISETS 1`
239			`#elif defined CONFIG_ICACHE_ASSO2`
240			`#define CFG_IU_ISETS 2`
241			`#elif defined CONFIG_ICACHE_ASSO3`
242			`#define CFG_IU_ISETS 3`
243			`#elif defined CONFIG_ICACHE_ASSO4`
244			`#define CFG_IU_ISETS 4`
245			`#else`
246			`#define CFG_IU_ISETS 1`
247			`#endif`
248
249			`#if defined CONFIG_ICACHE_SZ1`
250			`#define CFG_ICACHE_SZ 1`
251			`#elif defined CONFIG_ICACHE_SZ2`
252			`#define CFG_ICACHE_SZ 2`
253			`#elif defined CONFIG_ICACHE_SZ4`
254			`#define CFG_ICACHE_SZ 4`
255			`#elif defined CONFIG_ICACHE_SZ8`
256			`#define CFG_ICACHE_SZ 8`
257			`#elif defined CONFIG_ICACHE_SZ16`
258			`#define CFG_ICACHE_SZ 16`
259			`#elif defined CONFIG_ICACHE_SZ32`
260			`#define CFG_ICACHE_SZ 32`
261			`#elif defined CONFIG_ICACHE_SZ64`
262			`#define CFG_ICACHE_SZ 64`
263			`#elif defined CONFIG_ICACHE_SZ128`
264			`#define CFG_ICACHE_SZ 128`
265			`#elif defined CONFIG_ICACHE_SZ256`
266			`#define CFG_ICACHE_SZ 256`
267			`#else`
268			`#define CFG_ICACHE_SZ 1`
269			`#endif`
270
271			`#ifdef CONFIG_ICACHE_LZ16`
272			`#define CFG_ILINE_SZ 4`
273			`#else`
274			`#define CFG_ILINE_SZ 8`
275			`#endif`
276
277			`#if defined CONFIG_ICACHE_ALGORND`
278			`#define CFG_ICACHE_ALGORND 2`
279			`#elif defined CONFIG_ICACHE_ALGOLRR`
280			`#define CFG_ICACHE_ALGORND 1`
281			`#else`
282			`#define CFG_ICACHE_ALGORND 0`
283			`#endif`
284
285			`#ifndef CONFIG_ICACHE_LOCK`
286			`#define CONFIG_ICACHE_LOCK 0`
287			`#endif`
288
289			`#ifndef CONFIG_ICACHE_LRAM`
290			`#define CONFIG_ICACHE_LRAM 0`
291			`#endif`
292
293			`#ifndef CONFIG_ICACHE_LRSTART`
294			`#define CONFIG_ICACHE_LRSTART 8E`
295			`#endif`
296
297			`#if defined CONFIG_ICACHE_LRAM_SZ2`
298			`#define CFG_ILRAM_SIZE 2`
299			`#elif defined CONFIG_ICACHE_LRAM_SZ4`
300			`#define CFG_ILRAM_SIZE 4`
301			`#elif defined CONFIG_ICACHE_LRAM_SZ8`
302			`#define CFG_ILRAM_SIZE 8`
303			`#elif defined CONFIG_ICACHE_LRAM_SZ16`
304			`#define CFG_ILRAM_SIZE 16`
305			`#elif defined CONFIG_ICACHE_LRAM_SZ32`
306			`#define CFG_ILRAM_SIZE 32`
307			`#elif defined CONFIG_ICACHE_LRAM_SZ64`
308			`#define CFG_ILRAM_SIZE 64`
309			`#elif defined CONFIG_ICACHE_LRAM_SZ128`
310			`#define CFG_ILRAM_SIZE 128`
311			`#elif defined CONFIG_ICACHE_LRAM_SZ256`
312			`#define CFG_ILRAM_SIZE 256`
313			`#else`
314			`#define CFG_ILRAM_SIZE 1`
315			`#endif`
316
317
318			`#ifndef CONFIG_DCACHE_ENABLE`
319			`#define CONFIG_DCACHE_ENABLE 0`
320			`#endif`
321
322			`#if defined CONFIG_DCACHE_ASSO1`
323			`#define CFG_IU_DSETS 1`
324			`#elif defined CONFIG_DCACHE_ASSO2`
325			`#define CFG_IU_DSETS 2`
326			`#elif defined CONFIG_DCACHE_ASSO3`
327			`#define CFG_IU_DSETS 3`
328			`#elif defined CONFIG_DCACHE_ASSO4`
329			`#define CFG_IU_DSETS 4`
330			`#else`
331			`#define CFG_IU_DSETS 1`
332			`#endif`
333
334			`#if defined CONFIG_DCACHE_SZ1`
335			`#define CFG_DCACHE_SZ 1`
336			`#elif defined CONFIG_DCACHE_SZ2`
337			`#define CFG_DCACHE_SZ 2`
338			`#elif defined CONFIG_DCACHE_SZ4`
339			`#define CFG_DCACHE_SZ 4`
340			`#elif defined CONFIG_DCACHE_SZ8`
341			`#define CFG_DCACHE_SZ 8`
342			`#elif defined CONFIG_DCACHE_SZ16`
343			`#define CFG_DCACHE_SZ 16`
344			`#elif defined CONFIG_DCACHE_SZ32`
345			`#define CFG_DCACHE_SZ 32`
346			`#elif defined CONFIG_DCACHE_SZ64`
347			`#define CFG_DCACHE_SZ 64`
348			`#elif defined CONFIG_DCACHE_SZ128`
349			`#define CFG_DCACHE_SZ 128`
350			`#elif defined CONFIG_DCACHE_SZ256`
351			`#define CFG_DCACHE_SZ 256`
352			`#else`
353			`#define CFG_DCACHE_SZ 1`
354			`#endif`
355
356			`#ifdef CONFIG_DCACHE_LZ16`
357			`#define CFG_DLINE_SZ 4`
358			`#else`
359			`#define CFG_DLINE_SZ 8`
360			`#endif`
361
362			`#if defined CONFIG_DCACHE_ALGORND`
363			`#define CFG_DCACHE_ALGORND 2`
364			`#elif defined CONFIG_DCACHE_ALGOLRR`
365			`#define CFG_DCACHE_ALGORND 1`
366			`#else`
367			`#define CFG_DCACHE_ALGORND 0`
368			`#endif`
369
370			`#ifndef CONFIG_DCACHE_LOCK`
371			`#define CONFIG_DCACHE_LOCK 0`
372			`#endif`
373
374			`#ifndef CONFIG_DCACHE_SNOOP`
375			`#define CONFIG_DCACHE_SNOOP 0`
376			`#endif`
377
378			`#ifndef CONFIG_DCACHE_SNOOP_FAST`
379			`#define CONFIG_DCACHE_SNOOP_FAST 0`
380			`#endif`
381
382			`#ifndef CONFIG_DCACHE_SNOOP_SEPTAG`
383			`#define CONFIG_DCACHE_SNOOP_SEPTAG 0`
384			`#endif`
385
386			`#ifndef CONFIG_CACHE_FIXED`
387			`#define CONFIG_CACHE_FIXED 0`
388			`#endif`
389
390			`#ifndef CONFIG_DCACHE_LRAM`
391			`#define CONFIG_DCACHE_LRAM 0`
392			`#endif`
393
394			`#ifndef CONFIG_DCACHE_LRSTART`
395			`#define CONFIG_DCACHE_LRSTART 8F`
396			`#endif`
397
398			`#if defined CONFIG_DCACHE_LRAM_SZ2`
399			`#define CFG_DLRAM_SIZE 2`
400			`#elif defined CONFIG_DCACHE_LRAM_SZ4`
401			`#define CFG_DLRAM_SIZE 4`
402			`#elif defined CONFIG_DCACHE_LRAM_SZ8`
403			`#define CFG_DLRAM_SIZE 8`
404			`#elif defined CONFIG_DCACHE_LRAM_SZ16`
405			`#define CFG_DLRAM_SIZE 16`
406			`#elif defined CONFIG_DCACHE_LRAM_SZ32`
407			`#define CFG_DLRAM_SIZE 32`
408			`#elif defined CONFIG_DCACHE_LRAM_SZ64`
409			`#define CFG_DLRAM_SIZE 64`
410			`#elif defined CONFIG_DCACHE_LRAM_SZ128`
411			`#define CFG_DLRAM_SIZE 128`
412			`#elif defined CONFIG_DCACHE_LRAM_SZ256`
413			`#define CFG_DLRAM_SIZE 256`
414			`#else`
415			`#define CFG_DLRAM_SIZE 1`
416			`#endif`
417
418
419			`#ifdef CONFIG_MMU_ENABLE`
420			`#define CONFIG_MMUEN 1`
421
422			`#ifdef CONFIG_MMU_SPLIT`
423			`#define CONFIG_TLB_TYPE 0`
424			`#endif`
425			`#ifdef CONFIG_MMU_COMBINED`
426			`#define CONFIG_TLB_TYPE 1`
427			`#endif`
428
429			`#ifdef CONFIG_MMU_REPARRAY`
430			`#define CONFIG_TLB_REP 0`
431			`#endif`
432			`#ifdef CONFIG_MMU_REPINCREMENT`
433			`#define CONFIG_TLB_REP 1`
434			`#endif`
435
436			`#ifdef CONFIG_MMU_I2`
437			`#define CONFIG_ITLBNUM 2`
438			`#endif`
439			`#ifdef CONFIG_MMU_I4`
440			`#define CONFIG_ITLBNUM 4`
441			`#endif`
442			`#ifdef CONFIG_MMU_I8`
443			`#define CONFIG_ITLBNUM 8`
444			`#endif`
445			`#ifdef CONFIG_MMU_I16`
446			`#define CONFIG_ITLBNUM 16`
447			`#endif`
448			`#ifdef CONFIG_MMU_I32`
449			`#define CONFIG_ITLBNUM 32`
450			`#endif`
451
452			`#define CONFIG_DTLBNUM 2`
453			`#ifdef CONFIG_MMU_D2`
454			`#undef CONFIG_DTLBNUM`
455			`#define CONFIG_DTLBNUM 2`
456			`#endif`
457			`#ifdef CONFIG_MMU_D4`
458			`#undef CONFIG_DTLBNUM`
459			`#define CONFIG_DTLBNUM 4`
460			`#endif`
461			`#ifdef CONFIG_MMU_D8`
462			`#undef CONFIG_DTLBNUM`
463			`#define CONFIG_DTLBNUM 8`
464			`#endif`
465			`#ifdef CONFIG_MMU_D16`
466			`#undef CONFIG_DTLBNUM`
467			`#define CONFIG_DTLBNUM 16`
468			`#endif`
469			`#ifdef CONFIG_MMU_D32`
470			`#undef CONFIG_DTLBNUM`
471			`#define CONFIG_DTLBNUM 32`
472			`#endif`
473			`#ifdef CONFIG_MMU_FASTWB`
474			`#define CFG_MMU_FASTWB 1`
475			`#else`
476			`#define CFG_MMU_FASTWB 0`
477			`#endif`
478
479			`#else`
480			`#define CONFIG_MMUEN 0`
481			`#define CONFIG_ITLBNUM 2`
482			`#define CONFIG_DTLBNUM 2`
483			`#define CONFIG_TLB_TYPE 1`
484			`#define CONFIG_TLB_REP 1`
485			`#define CFG_MMU_FASTWB 0`
486			`#endif`
487
488			`#ifndef CONFIG_DSU_ENABLE`
489			`#define CONFIG_DSU_ENABLE 0`
490			`#endif`
491
492			`#if defined CONFIG_DSU_ITRACESZ1`
493			`#define CFG_DSU_ITB 1`
494			`#elif CONFIG_DSU_ITRACESZ2`
495			`#define CFG_DSU_ITB 2`
496			`#elif CONFIG_DSU_ITRACESZ4`
497			`#define CFG_DSU_ITB 4`
498			`#elif CONFIG_DSU_ITRACESZ8`
499			`#define CFG_DSU_ITB 8`
500			`#elif CONFIG_DSU_ITRACESZ16`
501			`#define CFG_DSU_ITB 16`
502			`#else`
503			`#define CFG_DSU_ITB 0`
504			`#endif`
505
506			`#if defined CONFIG_DSU_ATRACESZ1`
507			`#define CFG_DSU_ATB 1`
508			`#elif CONFIG_DSU_ATRACESZ2`
509			`#define CFG_DSU_ATB 2`
510			`#elif CONFIG_DSU_ATRACESZ4`
511			`#define CFG_DSU_ATB 4`
512			`#elif CONFIG_DSU_ATRACESZ8`
513			`#define CFG_DSU_ATB 8`
514			`#elif CONFIG_DSU_ATRACESZ16`
515			`#define CFG_DSU_ATB 16`
516			`#else`
517			`#define CFG_DSU_ATB 0`
518			`#endif`
519
520			`#ifndef CONFIG_LEON3FT_EN`
521			`#define CONFIG_LEON3FT_EN 0`
522			`#endif`
523
524			`#if defined CONFIG_IUFT_PAR`
525			`#define CONFIG_IUFT_EN 1`
526			`#elif defined CONFIG_IUFT_DMR`
527			`#define CONFIG_IUFT_EN 2`
528			`#elif defined CONFIG_IUFT_BCH`
529			`#define CONFIG_IUFT_EN 3`
530			`#elif defined CONFIG_IUFT_TMR`
531			`#define CONFIG_IUFT_EN 4`
532			`#else`
533			`#define CONFIG_IUFT_EN 0`
534			`#endif`
535			`#ifndef CONFIG_RF_ERRINJ`
536			`#define CONFIG_RF_ERRINJ 0`
537			`#endif`
538
539			`#ifndef CONFIG_FPUFT_EN`
540			`#define CONFIG_FPUFT 0`
541			`#else`
542			`#ifdef CONFIG_FPU_GRFPU`
543			`#define CONFIG_FPUFT 2`
544			`#else`
545			`#define CONFIG_FPUFT 1`
546			`#endif`
547			`#endif`
548
549			`#ifndef CONFIG_CACHE_FT_EN`
550			`#define CONFIG_CACHE_FT_EN 0`
551			`#endif`
552			`#ifndef CONFIG_CACHE_ERRINJ`
553			`#define CONFIG_CACHE_ERRINJ 0`
554			`#endif`
555
556			`#ifndef CONFIG_LEON3_NETLIST`
557			`#define CONFIG_LEON3_NETLIST 0`
558			`#endif`
559
560			`#ifdef CONFIG_DEBUG_PC32`
561			`#define CFG_DEBUG_PC32 0`
562			`#else`
563			`#define CFG_DEBUG_PC32 2`
564			`#endif`
565			`#ifndef CONFIG_IU_DISAS`
566			`#define CONFIG_IU_DISAS 0`
567			`#endif`
568			`#ifndef CONFIG_IU_DISAS_NET`
569			`#define CONFIG_IU_DISAS_NET 0`
570			`#endif`
571
572
573			`#ifndef CONFIG_AHB_SPLIT`
574			`#define CONFIG_AHB_SPLIT 0`
575			`#endif`
576
577			`#ifndef CONFIG_AHB_RROBIN`
578			`#define CONFIG_AHB_RROBIN 0`
579			`#endif`
580
581			`#ifndef CONFIG_AHB_IOADDR`
582			`#define CONFIG_AHB_IOADDR FFF`
583			`#endif`
584
585			`#ifndef CONFIG_APB_HADDR`
586			`#define CONFIG_APB_HADDR 800`
587			`#endif`
588
589			`#ifndef CONFIG_AHB_MON`
590			`#define CONFIG_AHB_MON 0`
591			`#endif`
592
593			`#ifndef CONFIG_AHB_MONERR`
594			`#define CONFIG_AHB_MONERR 0`
595			`#endif`
596
597			`#ifndef CONFIG_AHB_MONWAR`
598			`#define CONFIG_AHB_MONWAR 0`
599			`#endif`
600
601			`#ifndef CONFIG_DSU_UART`
602			`#define CONFIG_DSU_UART 0`
603			`#endif`
604
605
606			`#ifndef CONFIG_DSU_JTAG`
607			`#define CONFIG_DSU_JTAG 0`
608			`#endif`
609
610			`#ifndef CONFIG_MCTRL_LEON2`
611			`#define CONFIG_MCTRL_LEON2 0`
612			`#endif`
613
614			`#ifndef CONFIG_MCTRL_SDRAM`
615			`#define CONFIG_MCTRL_SDRAM 0`
616			`#endif`
617
618			`#ifndef CONFIG_MCTRL_SDRAM_SEPBUS`
619			`#define CONFIG_MCTRL_SDRAM_SEPBUS 0`
620			`#endif`
621
622			`#ifndef CONFIG_MCTRL_SDRAM_INVCLK`
623			`#define CONFIG_MCTRL_SDRAM_INVCLK 0`
624			`#endif`
625
626			`#ifndef CONFIG_MCTRL_SDRAM_BUS64`
627			`#define CONFIG_MCTRL_SDRAM_BUS64 0`
628			`#endif`
629
630			`#ifndef CONFIG_MCTRL_8BIT`
631			`#define CONFIG_MCTRL_8BIT 0`
632			`#endif`
633
634			`#ifndef CONFIG_MCTRL_16BIT`
635			`#define CONFIG_MCTRL_16BIT 0`
636			`#endif`
637
638			`#ifndef CONFIG_MCTRL_5CS`
639			`#define CONFIG_MCTRL_5CS 0`
640			`#endif`
641
642			`#ifndef CONFIG_MCTRL_EDAC`
643			`#define CONFIG_MCTRL_EDAC 0`
644			`#endif`
645
646			`#ifndef CONFIG_MCTRL_PAGE`
647			`#define CONFIG_MCTRL_PAGE 0`
648			`#endif`
649
650			`#ifndef CONFIG_MCTRL_PROGPAGE`
651			`#define CONFIG_MCTRL_PROGPAGE 0`
652			`#endif`
653
654			`#ifndef CONFIG_DDRSP`
655			`#define CONFIG_DDRSP 0`
656			`#endif`
657
658			`#ifndef CONFIG_DDRSP_INIT`
659			`#define CONFIG_DDRSP_INIT 0`
660			`#endif`
661
662			`#ifndef CONFIG_DDRSP_FREQ`
663			`#define CONFIG_DDRSP_FREQ 100`
664			`#endif`
665
666			`#ifndef CONFIG_DDRSP_COL`
667			`#define CONFIG_DDRSP_COL 9`
668			`#endif`
669
670			`#ifndef CONFIG_DDRSP_MBYTE`
671			`#define CONFIG_DDRSP_MBYTE 8`
672			`#endif`
673
674			`#ifndef CONFIG_DDRSP_RSKEW`
675			`#define CONFIG_DDRSP_RSKEW 0`
676			`#endif`
677			`#ifndef CONFIG_AHBROM_ENABLE`
678			`#define CONFIG_AHBROM_ENABLE 0`
679			`#endif`
680
681			`#ifndef CONFIG_AHBROM_START`
682			`#define CONFIG_AHBROM_START 000`
683			`#endif`
684
685			`#ifndef CONFIG_AHBROM_PIPE`
686			`#define CONFIG_AHBROM_PIPE 0`
687			`#endif`
688
689			`#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1)`
690			`#define CONFIG_ROM_START 100`
691			`#else`
692			`#define CONFIG_ROM_START 000`
693			`#endif`
694
695
696			`#ifndef CONFIG_AHBRAM_ENABLE`
697			`#define CONFIG_AHBRAM_ENABLE 0`
698			`#endif`
699
700			`#ifndef CONFIG_AHBRAM_START`
701			`#define CONFIG_AHBRAM_START A00`
702			`#endif`
703
704			`#if defined CONFIG_AHBRAM_SZ1`
705			`#define CFG_AHBRAMSZ 1`
706			`#elif CONFIG_AHBRAM_SZ2`
707			`#define CFG_AHBRAMSZ 2`
708			`#elif CONFIG_AHBRAM_SZ4`
709			`#define CFG_AHBRAMSZ 4`
710			`#elif CONFIG_AHBRAM_SZ8`
711			`#define CFG_AHBRAMSZ 8`
712			`#elif CONFIG_AHBRAM_SZ16`
713			`#define CFG_AHBRAMSZ 16`
714			`#elif CONFIG_AHBRAM_SZ32`
715			`#define CFG_AHBRAMSZ 32`
716			`#elif CONFIG_AHBRAM_SZ64`
717			`#define CFG_AHBRAMSZ 64`
718			`#else`
719			`#define CFG_AHBRAMSZ 1`
720			`#endif`
721
722			`#ifndef CONFIG_UART1_ENABLE`
723			`#define CONFIG_UART1_ENABLE 0`
724			`#endif`
725
726			`#if defined CONFIG_UA1_FIFO1`
727			`#define CFG_UA1_FIFO 1`
728			`#elif defined CONFIG_UA1_FIFO2`
729			`#define CFG_UA1_FIFO 2`
730			`#elif defined CONFIG_UA1_FIFO4`
731			`#define CFG_UA1_FIFO 4`
732			`#elif defined CONFIG_UA1_FIFO8`
733			`#define CFG_UA1_FIFO 8`
734			`#elif defined CONFIG_UA1_FIFO16`
735			`#define CFG_UA1_FIFO 16`
736			`#elif defined CONFIG_UA1_FIFO32`
737			`#define CFG_UA1_FIFO 32`
738			`#else`
739			`#define CFG_UA1_FIFO 1`
740			`#endif`
741
742			`#ifndef CONFIG_IRQ3_ENABLE`
743			`#define CONFIG_IRQ3_ENABLE 0`
744			`#endif`
745			`#ifndef CONFIG_IRQ3_NSEC`
746			`#define CONFIG_IRQ3_NSEC 0`
747			`#endif`
748			`#ifndef CONFIG_GPT_ENABLE`
749			`#define CONFIG_GPT_ENABLE 0`
750			`#endif`
751
752			`#ifndef CONFIG_GPT_NTIM`
753			`#define CONFIG_GPT_NTIM 1`
754			`#endif`
755
756			`#ifndef CONFIG_GPT_SW`
757			`#define CONFIG_GPT_SW 8`
758			`#endif`
759
760			`#ifndef CONFIG_GPT_TW`
761			`#define CONFIG_GPT_TW 8`
762			`#endif`
763
764			`#ifndef CONFIG_GPT_IRQ`
765			`#define CONFIG_GPT_IRQ 8`
766			`#endif`
767
768			`#ifndef CONFIG_GPT_SEPIRQ`
769			`#define CONFIG_GPT_SEPIRQ 0`
770			`#endif`
771			`#ifndef CONFIG_GPT_ENABLE`
772			`#define CONFIG_GPT_ENABLE 0`
773			`#endif`
774
775			`#ifndef CONFIG_GPT_NTIM`
776			`#define CONFIG_GPT_NTIM 1`
777			`#endif`
778
779			`#ifndef CONFIG_GPT_SW`
780			`#define CONFIG_GPT_SW 8`
781			`#endif`
782
783			`#ifndef CONFIG_GPT_TW`
784			`#define CONFIG_GPT_TW 8`
785			`#endif`
786
787			`#ifndef CONFIG_GPT_IRQ`
788			`#define CONFIG_GPT_IRQ 8`
789			`#endif`
790
791			`#ifndef CONFIG_GPT_SEPIRQ`
792			`#define CONFIG_GPT_SEPIRQ 0`
793			`#endif`
794
795			`#ifndef CONFIG_GPT_WDOGEN`
796			`#define CONFIG_GPT_WDOGEN 0`
797			`#endif`
798
799			`#ifndef CONFIG_GPT_WDOG`
800			`#define CONFIG_GPT_WDOG 0`
801			`#endif`
802
803			`#ifndef CONFIG_GRGPIO_ENABLE`
804			`#define CONFIG_GRGPIO_ENABLE 0`
805			`#endif`
806			`#ifndef CONFIG_GRGPIO_IMASK`
807			`#define CONFIG_GRGPIO_IMASK 0000`
808			`#endif`
809			`#ifndef CONFIG_GRGPIO_WIDTH`
810			`#define CONFIG_GRGPIO_WIDTH 1`
811			`#endif`
812
813			`#ifndef CONFIG_ATA_ENABLE`
814			`#define CONFIG_ATA_ENABLE 0`
815			`#endif`
816
817			`#ifndef CONFIG_ATAIO`
818			`#define CONFIG_ATAIO 0`
819			`#endif`
820
821			`#ifndef CONFIG_ATAIRQ`
822			`#define CONFIG_ATAIRQ 0`
823			`#endif`
824
825			`#ifndef CONFIG_ATA_MWDMA`
826			`#define CONFIG_ATA_MWDMA 0`
827			`#endif`
828
829			`#ifndef CONFIG_ATA_FIFO`
830			`#define CONFIG_ATA_FIFO 8`
831			`#endif`
832
833			`#ifndef CONFIG_DEBUG_UART`
834			`#define CONFIG_DEBUG_UART 0`
835			`#endif`