OpenCores
URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk

Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-altera-ep3c25/] [Makefile] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dimamali
GRLIB=../..
2
TOP=leon3mp
3
BOARD=altera-ep3c25
4
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
6
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
7
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
8
EFFORT=std
9
XSTOPT=
10
SYNPOPT="set_option -pipe 1; set_option -retiming 1"
11
VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
12
VHDLSIMFILES=testbench.vhd
13
SIMTOP=testbench
14
SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
15
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
16
CLEAN=soft-clean
17
 
18
TECHLIBS = altera altera_mf cycloneiii
19
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF fmf gsi \
20
        tmtc openchip ihp gleichmann stratixii stratixiii usbhc spw eth spansion dw02
21
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
22
        grusbhc spacewire haps net greth ata usb
23
FILESKIP = grcan.vhd
24
 
25
include $(GRLIB)/software/leon3/Makefile
26
include $(GRLIB)/bin/Makefile
27
 
28
 
29
##################  project specific targets ##########################
30
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.