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dimamali |
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This leon3 design is tailored to the Altera NiosII Cyclone III
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Embedded Evaluation Kit, with 16-bit DDR SDRAM and 1 Mbyte of SSRAM.
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The kit consists of a Cyclone III FPGA starter board and the LCD
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Multimedia Daughter Card.
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0. Introduction
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---------------
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The leon3 design can be synthesized with quartus or synplify,
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and can reach 60 - 70 MHz depending on configuration and synthesis
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options. Use 'make quartus' or 'make quartus-synp' to run the
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complete flow. To program the FPGA in batch mode, use
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'make quartus-prog-fpga' or
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'make quartus-prog-fpga-ref (reference config).
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This template design does not require modification of the logic in the
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daughter card CPLD. The CPLD is assumed to have its default configuration.
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The daughter card documentation has the following notice to avoid
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bus contention:
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"There are two LVDS termination resistors on the Cyclone III FPGA
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Starter Board, R3 and R4. R3 connects HC_RX_CLK and HC_TD_27MHZ;
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R4 connects HC_ADC_PENIRQ_n and HC_TX_CLK."
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When using Disable Setting
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Video decoder Ethernet PHY HC_ETH_RESET_N to 0
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Touch panel Ethernet PHY HC_ETH_RESET_N to 0
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Ethernet PHY Video decoder HC_TD_RESET to 0 and do not
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use the touch panel function
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when the ethernet PHY is
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enabled.
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In the template design, HC_TD_RESET is always driven to '0'.
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The user is responsible for not using the touch panel at
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the same time as the Ethernet PHY is in use.
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1. Unsupported peripherals / Further development
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------------------------------------------------
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The video decoder and audio decoder are not used.
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2. System
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---------
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The output from grmon should look something like this:
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grmon -altjtag -jtagdevice 1 -ramrws 1 -normw
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GRMON LEON debug monitor v1.1.30
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Copyright (C) 2004-2008 Gaisler Research - all rights reserved.
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For latest updates, go to http://www.gaisler.com/
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Comments or bug-reports to support@gaisler.com
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using Altera JTAG cable
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Selected cable 1 - USB-Blaster [USB 1-1.1]
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JTAG chain:
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@1: EP3C25 (0x020F30DD)
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GRLIB build version: 3050
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initialising ................
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detected frequency: 50 MHz
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Component Vendor
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LEON3 SPARC V8 Processor Gaisler Research
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AHB Debug JTAG TAP Gaisler Research
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SVGA frame buffer Gaisler Research
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GR Ethernet MAC Gaisler Research
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LEON2 Memory Controller European Space Agency
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AHB/APB Bridge Gaisler Research
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LEON3 Debug Support Unit Gaisler Research
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DDR266 Controller Gaisler Research
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Generic APB UART Gaisler Research
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Multi-processor Interrupt Ctrl Gaisler Research
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Modular Timer Unit Gaisler Research
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General purpose I/O port Gaisler Research
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Keyboard PS/2 interface Gaisler Research
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AMBA Wrapper for OC I2C-master Gaisler Research
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SPI Controller Gaisler Research
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SPI Controller Gaisler Research
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Use command 'info sys' to print a detailed report of attached cores
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grlib> inf sys
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00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0)
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ahb master 0
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01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x0)
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ahb master 1
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02.01:063 Gaisler Research SVGA frame buffer (ver 0x0)
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ahb master 2
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apb: 80000b00 - 80000c00
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clk0: 33.20 MHz
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03.01:01d Gaisler Research GR Ethernet MAC (ver 0x0)
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ahb master 3, irq 10
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apb: 80000a00 - 80000b00
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edcl ip 192.168.0.57, buffer 2 kbyte
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00.04:00f European Space Agency LEON2 Memory Controller (ver 0x1)
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ahb: 00000000 - 20000000
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ahb: 20000000 - 40000000
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ahb: a0000000 - b0000000
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apb: 80000000 - 80000100
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16-bit prom @ 0x00000000
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32-bit static ram: 1 * 1024 kbyte @ 0xa0000000
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01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0)
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ahb: 80000000 - 80100000
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02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1)
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ahb: 90000000 - a0000000
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AHB trace 128 lines, stack pointer 0xa00ffff0
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CPU#0 win 8, hwbp 2, itrace 128, V8 mul/div, lddel 1
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icache 2 * 8 kbyte, 32 byte/line lru
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dcache 2 * 4 kbyte, 16 byte/line lru
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03.01:025 Gaisler Research DDR266 Controller (ver 0x0)
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ahb: 40000000 - 50000000
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ahb: fff00100 - fff00200
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16-bit DDR : 1 * 32 Mbyte @ 0x40000000
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100 MHz, col 9, ref 7.8 us
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01.01:00c Gaisler Research Generic APB UART (ver 0x1)
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irq 2
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apb: 80000100 - 80000200
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baud rate 38343
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02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3)
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apb: 80000200 - 80000300
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03.01:011 Gaisler Research Modular Timer Unit (ver 0x0)
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irq 8
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apb: 80000300 - 80000400
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8-bit scaler, 2 * 32-bit timers, divisor 50
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05.01:01a Gaisler Research General purpose I/O port (ver 0x0)
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apb: 80000500 - 80000600
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06.01:060 Gaisler Research Keyboard PS/2 interface (ver 0x1)
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irq 6
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apb: 80000600 - 80000700
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08.01:028 Gaisler Research AMBA Wrapper for OC I2C-master (ver 0x0)
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irq 11
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apb: 80000800 - 80000900
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09.01:02d Gaisler Research SPI Controller (ver 0x1)
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irq 9
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apb: 80000900 - 80000a00
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FIFO depth: 4, 1 slave select signals
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Controller index for use in GRMON: 1
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0c.01:02d Gaisler Research SPI Controller (ver 0x1)
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irq 12
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apb: 80000c00 - 80000d00
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FIFO depth: 4, 2 slave select signals
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Controller index for use in GRMON: 2
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grlib>
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3. DDR interface
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----------------
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The DDR interface is supported and runs at 100 MHz.
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The read data clock phase shift should be set to 90' (rskew = 2500).
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4. SSRAM interface
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| 157 |
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------------------
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The SSRAM can be accessed using the standard LEON2 MCTRL core.
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One read waitstate is needed, start grmon with :
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grmon -altjtag -jtagdevice 1 -ramrws 1 -normw
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5. Flash memory
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---------------
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The 16-bit flash memory can be accessed and programmed by grmon,
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if the SSRAM is working. The output from the 'flash' command is
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listed below:
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grlib> fla
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Intel-style 16-bit flash on D[31:16]
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Manuf. Intel
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Device 0x881B
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Device ID 70a6ffff00684403
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User ID ffffffffffffffff
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1 x 16 Mbyte = 16 Mbyte total @ 0x00000000
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CFI info
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| 186 |
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flash family : 1
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flash size : 128 Mbit
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erase regions : 2
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erase blocks : 131
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write buffer : 64 bytes
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region 0 : 4 blocks of 32 Kbytes
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region 1 : 127 blocks of 128 Kbytes
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5.1 How to program the flash prom with a FPGA programming file
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--------------------------------------------------------------
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There are two ways of programming the Flash memory. One using
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Altera's Parallel Flash Loader and one using GRMON.
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Programming the Flash using Altera's Parallel Flash Loader:
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| 202 |
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1. Start Quartus II and select File -> Convert Programming Files
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2. Make the following settings:
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| 207 |
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Programming File Type: Programmer Object file (.pof)
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| 208 |
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Mode: Active Parallel
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Configuration device: CFI_128MB
|
| 210 |
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3. Select "Configuration Master" under "Input files to convert" and click
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"Add file"
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4. Select the leon3mp.sof file and click OK
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| 216 |
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5. Select "SOF data" and click "Properties"
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6. Change the following properties:
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Address mode for selected pages: Start
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Start address: 0x020000
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7. Generate the programmer object file by clicking "Generate"
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8. Start the Quartus II programmer
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9. Click "Auto Detect"
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10. Right-click on the detected EP3C25 device and select "Attach Flash Device"
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11. Select Flash Memory, CFI_128MB and click "OK"
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12. Right click on the added CFI_128MB Flash device and select "Change File"
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13. Select the .pof file that was generated in step 7 and click "OK".
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14. Check the "Program/Configure" box for the added file under the Flash
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| 238 |
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device. Checking this box will change the Device File to "Factory
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| 239 |
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default PFL image"
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| 240 |
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15. Click "Start"
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| 242 |
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16. When programming has successfully finished press "Reconfigure" on the
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| 244 |
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board to load the leon3mp design.
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| 245 |
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| 246 |
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Programming the Flash with GRMON:
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| 247 |
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| 248 |
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1. Create a hex file of the programming file with Quartus. Choose
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| 249 |
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"Active Parallel" as the Mode. This mode is available in Quartus II 7.2
|
| 250 |
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| 251 |
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2. Convert the Intel Hex file to srecord format. The hexfile needs to be byte
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| 252 |
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swapped. This can be done with a tool from the SRecord package which can be
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| 253 |
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downloaded from http://srecord.sourceforge.net/. Issue the command:
|
| 254 |
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| 255 |
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srec_cat output_file.hexout -Intel -byteswap > fpga.srec
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| 256 |
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| 257 |
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If the resulting fpga.srec file does not have the correct offset, the
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| 258 |
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offset may have to be given as an argument to srec_cat:
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| 259 |
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| 260 |
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srec_cat output_file.hexout -Intel -byteswap -offset 0x20000 > fpga.srec
|
| 261 |
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| 262 |
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To see that the data has the correct offset, issue the command:
|
| 263 |
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| 264 |
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srec_info fpga.srec
|
| 265 |
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| 266 |
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The "Data:" area should start at 020000.
|
| 267 |
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| 268 |
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3. Program the flash memory using grmon:
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| 270 |
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flash unlock all
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flash erase 0x20000 0x100000
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| 272 |
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flash load fpga.srec
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| 274 |
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The programming is slow, and will take at approximately 30 minutes with a JTAG
|
| 275 |
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connection. The ethernet debug link is significantly faster.
|
| 276 |
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6. SPI SD Card interface
|
| 278 |
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----------------
|
| 279 |
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| 280 |
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The design instantiates a SPICTRL core which is connected to the SD card slot.
|
| 281 |
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The user may deselect the SPI controller (SPICTRL) and enable the SPI memory
|
| 282 |
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controller instead. SPIMCTRL allows reading SD cards without additonal software
|
| 283 |
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support. The design will not synthesize if both cores are enabled.
|
| 284 |
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|
| 285 |
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Suitable configuration values for SPIMCTRL are; SD Card = 1, Clock divisor = 2,
|
| 286 |
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Alt. clock divisor = 7. Note that the SPIMCTRL core will insert a large amount
|
| 287 |
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of wait states on the system bus if AMBA SPLIT support is not enabled.
|
| 288 |
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| 289 |
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7. Ethernet interface
|
| 290 |
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---------------------
|
| 291 |
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| 292 |
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The design can be configured to instantiate a GRETH. Note that if the
|
| 293 |
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LCD touch panel interface is enabled the GRETH is not instantiated
|
| 294 |
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even if it is selected in xconfig. See the note about bus contention
|
| 295 |
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in section 0. Introduction of this file.
|
| 296 |
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|
| 297 |
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| 298 |
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8. I2C interface
|
| 299 |
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----------------
|
| 300 |
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| 301 |
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The design instantiates an I2C-master that is connected to the daughter
|
| 302 |
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card EEPROM. The daughter card uses uni-directional I2C clock lines
|
| 303 |
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and this prevents slaves from stretching the master clock.
|
| 304 |
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|
| 305 |
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grlib> i2c read 0x50 0 16
|
| 306 |
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| 307 |
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00: 10 10 00 07
|
| 308 |
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04: ed 08 07 6d
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| 309 |
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08: 0f 6a 0f 09
|
| 310 |
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0c: 00 84 00 94
|
| 311 |
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| 312 |
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9. LCD support
|
| 313 |
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---------------
|
| 314 |
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|
| 315 |
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Two cores must be instantiated to fully support all the functionality
|
| 316 |
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of the LCD touch panel. For video display an SVGACTRL core is
|
| 317 |
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instantiated. The 3-wire interface and panel ADC is interfaced with
|
| 318 |
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an instantiation of a SPICTRL core. The designer can configure the
|
| 319 |
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design to exclude any of these cores.
|
| 320 |
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|
| 321 |
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The 3-wire serial interface and the touch panel ADC are wired to
|
| 322 |
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share the same clock. The touch panel slave select signal is wired
|
| 323 |
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to the first slave select signal of the SPICTRL core. The three wire
|
| 324 |
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enable signal is wired to the second slave select signal.
|
| 325 |
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|
| 326 |
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The ADC busy and interrupt signals are connected to GPIO 3 and 4,
|
| 327 |
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respectively, and can be accessed via the GRGPIO core.
|
| 328 |
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|
| 329 |
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10. VGA support
|
| 330 |
|
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---------------
|
| 331 |
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|
| 332 |
|
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The designer can enable a SVGACTRL core to drive the VGA DAC.
|
| 333 |
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|
| 334 |
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|
| 335 |
|
|
11. Loading and starting an OS from GRMON
|
| 336 |
|
|
-----------------------------------------
|
| 337 |
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|
| 338 |
|
|
Before loading an OS with GRMON it may be necessary to adjust
|
| 339 |
|
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the stack pointer. This can be done by supplying the flag
|
| 340 |
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|
| 341 |
|
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-stack 0x41ffff00
|
| 342 |
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|
| 343 |
|
|
or by using the GRMON command
|
| 344 |
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|
|
| 345 |
|
|
stack 0x41ffff00
|
| 346 |
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|
| 347 |
|
|
after a connection has been made to the board.
|
| 348 |
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|
|
